A High-Conversion Ratio Multiphase Converter Realized with Generic Modular Cells

Abstract

This paper introduces a high-conversion ratio multiphase nonisolated converter built from generic LC cells. The unique architecture that hinges on a generic capacitor inductor switching module enables the high modularity of the topology, providing a quick extension of the converter design in an interleaved configuration for lower ripple and higher current output. The generic module comprises the basic power components of a nonisolated DC–DC converter, where the unique interaction between the capacitor and the inductor results in a soft charging operation, which curbs the losses of the converter, and contributes to a higher efficiency. Additional features of the new converter include a significantly extended effective duty ratio, and a lower voltage stress on the switches, a very high output current, and architecture-inherent output current sharing that balances the loading between the phases. In addition, a power extension using a paralleling and interleaving approach is presented to provide higher output current capabilities. Simulation and experimental results of a modular interleaved three-phase prototype demonstrate an excellent proof of concept and agree well with the theoretical analyzes developed in this study.

1. Introduction

With the development of cloud computing and data centers, the demand for efficient, high-power conversion has significantly grown up [1,2,3,4,5]. In recent years, DC distribution systems have been widely used to replace the traditional AC systems in data centers due to their higher efficiency. The increased popularity of using a 48 V DC power distribution network in today’s computing industry, where multiple CPUs and DRAMs are part of the main consumer, has reinforced the need for DC–DC Point of Load (PoL) systems capable of carrying the conversion of 48 V-to-1.x V. The majority of modern supply methods are using either a two-stage conversion in series such as 48 V-to-12 V and then 12 V-to-1.x V [6,7,8,9,10,11,12,13,14,15], or a direct-conversion approach 48 to 1.x V that could be magnetically isolated or not [16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34].

Recently, step-down conversion solutions based on unregulated switched-capacitor converters (SCC) as a first stage, followed by an inductor based regulated stage, i.e., derivatives of buck converters, have been introduced [6,8,10,35]. Multiphase interleaved buck converters are generally used for the point of load stage [12,36,37], achieving fast dynamic response and delivering a high current to the load, while reducing the output filter volume and obtaining a high efficiency over wide load range. In a two-step high-conversion approach, the objective of the first-stage converter is to maintain a high efficiency and loosely hit the operation region of the second stage [16,17]. Even though the first and the second stages are efficient on their own, the overall conversion efficiency after both conversions is insufficient for many competitive applications, due to the multiplication of the two efficiencies. In addition, bulky transformers or heat sinks [10,24,25] are not desirable for applications that require both power density and large conversion ratios.

The development of GaN-based FETs enables the use of high-density single-stage conventional buck converters for the direct-conversion approach. Yet, applying a single-stage buck converter or using multilevel buck converters for the full 48 V-to-1.x V conversion remains impractical due to the time resolution challenges, associated with narrow “on” times and very high switching frequencies that require PWM generation hardware with precision on the order of ten picoseconds in both the duty cycle and jitter of the signal [31,38]. In addition, duty cycles on the order of 1/48 are still very challenging in terms of RMS losses in the circuit. Some prior art suggests using advanced control methods to improve the efficiency of the conventional buck converters [39,40,41,42,43,44,45,46]. Other solutions consist of combinations of the buck topology with flying capacitor topology, offering several advantages over the two-stage conversion solutions [12,21], such as extended conversion ratio, wide dynamic range, and the integration of multilevel and multiphase architecture features in a single conversion stage, which reduce inductor voltage swing and lower the switching loss. One derivative of the multiphase buck converter with extended-duty cycles—known as the series-capacitor buck converter—performs better than a buck converter and stands out as an attractive solution [23,26,27]. This converter can produce fast dynamic response to load changes, along with symmetrical operation and natural current sharing between phases, and reduce transistors’ voltage stress. However, previously documented topologies with extended-duty ratio are somewhat limited for application in high-power cases, where a very high conversion ratio and high currents are involved. One solution to higher voltage gain is presented in [34] using a three-phase series-capacitor buck converter. However, it lacks the current extension and architecture generalization. This work presents a full architecture analysis and generalization of a series-capacitor buck to higher orders, increasing both the conversion ratio and current output capabilities. In addition, this work covers advanced topics and analyzes those such as soft charging, boundary operation, voltage versus duty cycle evaluation, component stress analysis, and a modularization method using a generic cell.

From a design perspective, many power converters can be analyzed as being constructed around a fundamental cell [10,45,46,47]. This fundamental cell enables the implementation of several different topologies, which share a mode of operation and provide various conversion ratios by reconfiguring its connection orientation. For instance, common converter topologies such as buck, boost, and buck–boost share a core structure comprising a single inductor and two switches [48,49,50]. Despite utilizing the same basic components, these converters achieve different functionalities through distinct topological arrangements.

A power design methodology based on a fundamental cell provides numerous advantages, including modularity, which simplifies the design process and supports easy scalability. It promotes standardization, reducing design complexity while ensuring consistent performance across various applications. This approach enhances effectiveness by enabling component reuse, minimizes development time, and streamlines validation and testing efforts. Furthermore, it improves manufacturability by maintaining uniformity during fabrication and reduces costs through shared design and testing efforts, making it a highly effective strategy for power system development.

The objective of this study is to introduce a modular construction approach of a very-high conversion ratio multiphase converter, based on a generic, switched LC cell. The converter (Figure 1) is constructed from a chain of identical building blocks, each consisting of a switched inductor–capacitor pair that forms a stacked series-capacitor converter frontend whereas the backend of the converter is a set of parallel or interleaved inductors. This modular stacking of generic cells allows flexibility in the design, enabling high-power and high-conversion ratio without sacrificing the end-to-end efficiency of the converter, since the operation relies on single-cycle power processing from source to load, regardless of the number of modules stacked. Current sharing is maintained throughout the multiphase backend, allowing state-of-the-art performance in terms of power considerations and converter sizing for operation in both steady-state and transient modes.

The rest of the paper is organized as follows. Section 2 presents the operation principle and the construction methodology of modular stacking of identical switched inductor–capacitor cells. In Section 3, a full steady-state analysis of a three-level converter is delineated. The generalization of voltage and power stacking is analyzed in Section 4. Simulation and experimental results are provided in Section 5, and Section 6 concludes the paper.

2. Modular Multiphase Step-Down Converter

The development of a generic cell as a basic building block is shown in Figure 2. The cell includes an inductor, a capacitor, and a pair of complementary switches. Multiple cells can be connected for increased energy processing. This unique approach of designing with a generic cell enables the extension of the converter to any number of phases, with the benefit of higher duty ratio resolution, lower voltage stress on the transistors, and inherent current balancing [51]. These benefits make the multiphase topology an ideal candidate for high output current and high conversion ratio applications. The combination of generic cells for the implementation of a high conversion ratio DC–DC converter is described and analyzed in the following sections. Throughout this paper, the concept is presented and analyzed on a configuration of three cells, namely, a three-phase buck converter, as illustrated in Figure 1. The main building block is a generic cell (Figure 2) comprised of an inductor, a capacitor, and two complementary switches. The cells connection follows a simple procedure. Port “a” of the cell (Figure 2) is connected to the previous cell (to V_in in the case of the first cell), port “b” of the cell is connected to the next cell, and port “c” is connected to the load. To complete the converter, one additional switch per converter (S_2-3 in Figure 1) is added. It provides a discharge path for the last cell capacitor.

The operation of the proposed topology is described using the ideal timing diagram in Figure 3 and the sub-circuits with highlighted current paths in Figure 4. For simplicity, this analysis assumes that the voltage ripple across all capacitors is negligible compared to their DC levels. The switching period is divided into six intervals, corresponding to six states (I–VI). Odd-numbered intervals represent the charging phases for each cell, while even-numbered intervals correspond to balancing states. In this context, a “cell” refers to an individual building block, whereas a “phase” denotes the electrical components within a single cell that contributes to supplying the load current.

As in typical multiphase converters, all phases deliver a continuous current to the output in an interleaved buck type connection. Since the charging and discharging of the capacitors is carried out via an inductance at all states, the charge transfer is referred to as soft charging [51,52], which is highly advantageous in terms of efficient energy processing [53].

State I (Figure 4a) is the charging state for phase 1, and phases 2 and 3 are discharging to the load during this state. The switches S_1H, S_2L, and S_3L are turned ON, and capacitor C₁ and inductor L₁ are charging from the input and at the same time deliver current to the load. Inductors L₂ and L₃ are delivering current to the load.

States II, IV, and VI (Figure 4b) are balancing states. No phases are charged during these states. Switches S_1L, S_2L, and S_3L are ON, and all the inductors are delivering current to the load.

State III (Figure 4c) is the charging state for phase 2, and phases 1 and 3 are discharging. Switches S_1L, S_2H, S_2-3, and S_3L are ON, and inductor L₂ is charged from two parallel sources: capacitor C₃, and a series connection of C₁ and C₂ (where C₁ is connected in a positive direction, and C₂ is connected in a negative direction). As a result of this configuration, C₁ transfers charge to capacitor C₂, and the voltage relationship between the three capacitors is as follows:

$$V_{\mathrm{C}1}-V_{\mathrm{C}2}=V_{\mathrm{C}3}.$$

(1)

Inductors L₁ and L₃ are delivering current to the load in this state.

State V (Figure 4d) is the charging state for phase 3, and phases 1 and 2 are discharging. Switches S_1L, S_2L, and S_3H are ON, and capacitor C₂ charges capacitor C₃ and inductor L₃, while at the same time this chain C₂, C₃, and L₃ delivers current to the load. Inductors L₁ and L₂ are delivering current to the load during this state.

3. Steady State Analysis

3.1. Conversion Ratio

The current ripple of inductors L₁, L₂, and L₃ during “on” and “off” intervals can be expressed as follows:

$$\Delta i_{L1}=\left|{\displaystyle \frac{-V_{\mathrm{o}}}{L_1}}\right|\left(1-D_1\right)=\left|{\displaystyle \frac{\left(V_{\mathrm{in}}-V_{\mathrm{C}1}\right)-V_{\mathrm{o}}}{L_1}}\right|D_1,$$

(2)

$$\Delta i_{L2}=\left|{\displaystyle \frac{-V_{\mathrm{o}}}{L_2}}\right|\left(1-D_2\right)=\left|{\displaystyle \frac{\left(V_{\mathrm{C}1}-V_{\mathrm{C}2}\right)-V_{\mathrm{o}}}{L_2}}\right|D_2,$$

(3)

$$\Delta i_{L3}=\left|{\displaystyle \frac{-V_{\mathrm{o}}}{L_3}}\right|\left(1-D_3\right)=\left|{\displaystyle \frac{\left(V_{\mathrm{C}2}-V_{\mathrm{C}3}\right)-V_{\mathrm{o}}}{L_3}}\right|D_3,$$

(4)

where L₁ is discharged during states II, III, IV, V, and VI, and charged during state I. Inductor L₂ is discharged during states I, II, IV, V, and VI, and charged during state III. Similarly, inductor L₃ is discharged during states I, II, III, IV, and VI, and charged during state V.

Without losing the generality, and assuming equal inductance values, substituting (1), into (3), the following voltage relationship can be derived from (2)–(4):

$$\left\{\begin{array}{l}{V}_{\mathrm{o}}=D_1\left(V_{\mathrm{in}}-V_{\mathrm{C}1}\right)\\ V_{\mathrm{o}}=D_2{V}_{\mathrm{C}3} \\ V_{\mathrm{o}}=D_3\left(V_{\mathrm{C}2}-V_{\mathrm{C}3}\right)\end{array}\right.,$$

(5)

where D₁ = T_on1/T_s, D₂ = T_on2/T_s, and D₃ = T_on3/T_s. Solving (5) for the average capacitors’ voltages, yields the following:

$$\begin{array}{l}{V}_{\mathrm{C}1}=\left[{\displaystyle \frac{2}{D_2}}+{\displaystyle \frac{1}{D_3}}\right]V_o, \\ V_{\mathrm{C}2}=\left[{\displaystyle \frac{1}{D_2}}+{\displaystyle \frac{1}{D_3}}\right]V_o, \\ V_{\mathrm{C}3}={\displaystyle \frac{1}{D_2}}{V}_o.\end{array}$$

(6)

Combining (5) and (6), converter voltage gain can be expressed as follows:

$$M={\displaystyle \frac{V_{\mathrm{o}}}{V_{\mathrm{in}}}}=1/\left({\displaystyle \frac{1}{D_1}}+{\displaystyle \frac{2}{D_2}}+{\displaystyle \frac{1}{D_3}}\right),$$

(7)

For the private case of equal duty ratios for all three phases, D₁ = D₂ = D₃ = D, average capacitors voltages are converged to V_C1 = 3V_in/4, V_C2 = 2V_in/4, and V_C3 = V_in/4, and the expression for converter voltage gain is reduced to the following:

$$M={\displaystyle \frac{V_{\mathrm{o}}}{V_{\mathrm{in}}}}={\displaystyle \frac{D}{4}}.$$

(8)

The effect of the series-capacitor stacking can be analyzed using (8), which implies that the conversion ratio of the new topology is four times higher than a typical buck converter.

3.2. Inductors’ Currents and Balancing

For simplicity, it is assumed that the converter is loaded with a very light load at the output. The load current I_out is delivered from all three phases and equals to the sum of the average inductors’ currents. This relationship can be expressed by the following equation:

$$I_{\mathrm{out}}=I_{L1}+I_{L2}+I_{L3}.$$

(9)

The average value of each of the inductor’s currents at a steady state can be calculated using the fact that the charge balance is achieved for each of the capacitors [54]. For example, the charge delivered to C₂ during state III must be equal to the charge consumed from C₂ (by C₃) during state V. Thus, charge equations can be summarized as follows:

$$\begin{gathered} {\mathrm{Q}}_{\mathrm{C}1},{\left.{\displaystyle \frac{1}{2}}{I}_{L_2}{\displaystyle \frac{D_2}{f_s}}\right|}_{\mathrm{charge}}={\left. I_{L_1}{\displaystyle \frac{D_1}{f_s}}\right|}_{\mathrm{discharge}}, \\ {\mathrm{Q}}_{\mathrm{C}2}, {\left.{\displaystyle \frac{1}{2}}{I}_{L_2}{\displaystyle \frac{D_2}{f_s}}\right|}_{\mathrm{charge}}={\left.I_{L_3}{\displaystyle \frac{D_3}{f_s}}\right|}_{\mathrm{discharge}}, \\ { \mathrm{Q}}_{\mathrm{C}3}, {\left.I_{L_3}{\displaystyle \frac{D_3}{f_s}}\right|}_{\mathrm{charge}}={\left.{\displaystyle \frac{1}{2}}{I}_{L_2}{\displaystyle \frac{D_2}{f_s}}\right|}_{\mathrm{discharge}}. \end{gathered}$$

(10)

Solving the system using Equation (9) yields the average inductors’ currents:

$$\begin{gathered} I_{L1}={\displaystyle \frac{D_2{D}_3}{D_2{D}_3+D_1{D}_2+2D_1{D}_3}}{I}_{\mathrm{out}}, \\ {I}_{L2}={\displaystyle \frac{2D_1{D}_3}{2D_1{D}_3+D_2{D}_3+D_1{D}_2}}{I}_{\mathrm{out}}, \\ {I}_{L3}={\displaystyle \frac{D_1{D}_2}{D_2{D}_3+D_1{D}_3+2D_1{D}_3}}{I}_{\mathrm{out}}. \end{gathered}$$

(11)

Therefore, in the most straightforward private case where duty cycles are equal, D₁ = D₂ = D₃ = D, the three-phase converter average inductor currents become I_L1 = I_out/4, I_L2 = I_out/2 and I_L3 = I_out/4. It should be mentioned that phase 2 carries double the current compared to phases 1 and 3. This is a result of both capacitors C₁ and C₃ discharging at state III, through inductor L₂. The inductors’ current balance between phases can be achieved by setting the duty cycle of phase 2 to be half of the duty cycle of phases 1 and 3. The duty cycles in this case are summarized in (12), and the voltage ratio of the converter becomes M = D₂/6 = D₁/3.

$$D_1=D_3=D_2/2.$$

(12)

3.3. Soft Charge/Discharge

The condition for soft charging is based on the ratio between each charging time and time constant of the capacitance loop [51,52,53]. When the switching time is much shorter than the time constant of the loop circuit, the current is practically constant during the switching time and hence the RMS value is the lowest possible. This condition can be expressed as follows:

$$T_j<<R_j{C}_j,$$

(13)

where R_j and C_j are the total ESR and capacitance in each switching state, respectively, and T_j is the time interval. Hard charging occurs when two branches of capacitors are connected in parallel. In the case of imperfect symmetry between the capacitor voltages in the circuit, state III (Figure 4) may experience hard switching for some short periods upon state changes. There, high current spikes may arise as a result of voltage mismatch between branches (C₁ + C₂ in parallel to C₃). Applying generic cell structure in schematic and in physical layout are some of the measures to remedy this issue as it significantly reduces voltage mismatches due to parasitical elements. The use of low ESR capacitors is recommended to further reduce the potential voltage mismatch as a result of component uncertainties, when paralleling capacitors.

3.4. Switches Voltage Stress

The expression for maximum voltage stress across each of the converter switches during each converter state, along with an example of maximum voltage stresses in the application of 48 V-to-1 V (right most column), are summarized in

Table 1. Switches voltages of each state in the 3ph. converter.

	State						Stress (Vin = 48 V, M = 1/48)
Switch	I	II	III	IV	V	VI	Vmax [V]
S1L	Vin-VC1	0	0	0	0	0	12
S1H	0	Vin-VC1	Vin-VC1	Vin-VC1	Vin-VC1	Vin-VC1	12
S2L	0	0	VC3	0	0	0	12
S2H	Vin-VC2	VC1-VC2	0	VC1-VC2	VC1-VC2	VC1-VC2	24
S2-3	VC3	VC3	0	VC3	VC2	VC3	24
S3L	0	0	0	0	VC2-VC3	0	12
S3H	VC2-VC3	VC2-VC3	VC2	VC2-VC3	0	VC2-VC3	24

The blue shade indicates the highest stress per switch.

. Low-side switches S_1L, S_2L, S_3L, and S_1H operate with a very low voltage stress of V_in/4, while the high-side switches S_2H, S_2-3, and S_3H experience higher stresses of V_in/2 during one of the switching states. The maximum voltage stress values express the highest possible voltage that appears across the switch at any of the switching stages. The presence of the flying capacitors is the key factor in reducing the voltage stress across each of the MOSFETs, and the stress can be further reduced if a higher number of cells is used.

3.5. CCM–DCM Boundary

For a new converter operation in the continuous conduction mode (CCM), the inductor current needs to be always positive. The boundary between CCM and discontinuous conduction mode (DCM) is considered when the inductor current falls to zero at the end of the switching cycle. Setting the I_{L (min)} to zero [48,49,50], results in an expression for the average inductor current for the CCM–DCM boundary:

$$I_{L(av)}={\displaystyle \frac{1}{T}}\left({\displaystyle \frac{1}{2}}{I}_{\max }{D}_{on}T+{\displaystyle \frac{1}{2}}{I}_{\max }{D}_{off}T\right)={\displaystyle \frac{1}{2}}{I}_{\max }\left(D_{on}+D_{off}\right).$$

(14)

Assuming that the duty cycles are equal for all converter phases, the average current of inductors L₁, L₂, L₃, can be expressed as I_L1 = V_o/4R_o, I_L2 = V_o/2R_o, and I_L3 = V_o/4R_o, respectively, according to (11). At steady state, the ΔI_L in the charge stage is equal to the discharged stage. For inductor L₁, the expression for I_L1(max) can be summarized as follows:

$$I_{L1(\max )}={\displaystyle \frac{\left(V_{in}-V_{C1}\right)-V_0}{L_1}}{D}_{on}T,$$

(15)

The boundary condition is calculated for each inductor from the charge or discharge equations using the expressions in (2), (3), and (4). Substituting (15) into (14), using Equation (2), and after some manipulations, the boundary condition can be summarized as follows:

$$\begin{array}{ll}{\displaystyle \frac{Vo}{4Ro}}={\displaystyle \frac{\left(V_{in}-V_{c1}\right)-V_0}{2L_1}}{D}_{1on}T\hfill & \left(D_{1on}+D_{1off}\right)=\\ \hfill & \hfill ={\displaystyle \frac{V_0}{2L_1}}{D}_{1off}T\left(D_{1on}+D_{1off}\right)\end{array}.$$

(16)

Note that at the boundary between the CCM to DCM modes, the sum of the duty ratios can still be written as D_1on + D_1off = 1; hence, Equation (16) can be also expressed as follows:

$$L_{1\min }={\displaystyle \frac{2R_o\left(1-D_{1on}\right)}{f_S}},$$

(17)

where L_1(min) is the minimum inductance required for CCM mode operation. The boundaries for L₂ and L₃ can be calculated using Equations (3), (4), (11), and (14), in the similar manner as described for L₁. The expressions for L₂ and L₃ are summarized below:

$$\begin{array}{l}{L}_{2\min }={\displaystyle \frac{R_o\left(1-D_{2on}\right)}{f_S}},\\ L_{3\min }={\displaystyle \frac{2R_o\left(1-D_{3on}\right)}{f_S}}.\end{array}$$

(18)

4. Extension for Higher Order Converters

The cell of Figure 2 enables converter extension along multiple directions. The first extension addresses a higher conversion ratio. It is achieved by chaining several cells one after another. The number of cells is defined as n (Figure 5), and the chaining procedure follows the method outlined in Section 2, using the cell described in Figure 2, where all inductors are connected in parallel at the output, and the high-side voltage of the flying capacitor of a preceding cell connects to the high-side switch (S_xH), of the next one (Figure 1). To provide a discharge path for the last cell capacitor, one additional switch per converter is added S_{(n–1)–(n)} Figure 5.

The expression for the conversion ratio, in a generalized form for a single module with n cells in series, 1 × n topology, and assuming equal duty cycle is applied to all the cells, takes the form of (19):

$$M_n={\displaystyle \frac{V_{\mathrm{o}}}{V_{in}}}={\displaystyle \frac{D}{n+1}},$$

(19)

where n is the number of cells of one converter module, and D is the common duty cycle applied to all the cells.

Average capacitor voltages per phase can be expressed as follows:

$$V_{Ci}={\displaystyle \frac{n-(i-1)}{n+1}}{V}_{in},$$

(20)

where i is the index of the cell number. For example, in a two-cell topology, n = 2 [20], the conversion ratio M is equal to M = D/3 and capacitor voltages are V_C1 = 2V_in/3 and V_C2 = V_in/3. For a three-phase case, n = 3, the ratio M equals to M = D/4, and the average capacitor voltages are V_C1 = 3V_in/4, V_C2 = 2V_in/4, and V_C3 = V_in/4, as summarized in Section 3.1. The average inductors’ currents for each phase (except phase n-1) can be represented as follows:

$$I_{Li}={\displaystyle \frac{1}{n+1}}{I}_{out},$$

(21)

where the average inductor current for phase n-1 will be twice that of the other phases (assuming again equal duty cycle) due to a slightly different operation mode of the last two cells. For example, for a single module, m = 1, and two cells, n = 2, the average inductors currents are I_L1 = I_out/3 and I_L2 = 2I_out/3, and for the case of three cells, n = 3, inductors currents at steady state are I_L1 = I_out/4, I_L2 = I_out/2, and I_L3 = I_out/4, as mentioned in Section 3.2.

The second extension covers the power capability of the converter, i.e., output current. Higher power to the load is facilitated by paralleling modules. Paralleling is carried out on the module level, where the inputs and the outputs of all the modules are connected in parallel to the source and the load, respectively. In this manner, the outputs of the modules share the same capacitor. The number of modules in parallel are referred to here as m (Figure 5).

The total output current in the case of the m × n system can be calculated by summing up all output currents from all the modules, where each module output current consists of the sum of its inductors currents. The expression for multi module total output current is summarized in (22):

$$I_{outT}={\displaystyle \sum _{\mathrm{Module}=1}^m\left({\displaystyle \sum _{\mathrm{Ph} =1}^n{I}_{L(Ph)}}\right)}$$

(22)

A parallel connection of multiple modules can significantly lower the voltage and current component stresses, enabling a higher output power with better efficiency.

The third expansion provides a degree of freedom where the per-phase duty ratio is independently set. This assists in balancing the currents along the cells, facilitates targeted current sharing control that could be unbalanced, for example, and enables a better thermal management. The current mismatch between the phases can be adjusted by tuning the duty cycle of each phase, as mentioned in Section 3.2. An example of a three-phase converter response to non-equal duty cycle among the phases is demonstrated in Figure 6. Similar conversion ratios can be achieved by applying a different combination of D₁, D₂, and D₃ (Figure 6a). Since, as mentioned earlier, the n-1 phase always carries double the current of the rest of the phases, in three-phase converter it makes sense to separate its duty cycle from the rest of the phases. This case is demonstrated in Figure 6b, where D₁ and D₃ are equal and being changed together (represented by the x axis). The solid traces represent the resulting conversion ratio of several selected duty cycles of the n-1 phase. Horizontal dashed red lines demonstrate three conversion ratios, and as can be observed, there are many intersections with the solid black traces, which are the operation points of different duty cycles that result in the same conversion ratio. Using this degree of freedom, the inherent current of the n-1 phase could be dialed down to be equal to the rest of the phases. This is beneficial since a current mismatch between phases and between modules can lead to a higher output current ripple. Taking advantage of these expansion possibilities offers three degrees of freedom in the converter architecture, allowing the design objectives to remain independent of one another. For example, going with a higher conversion ratio does not penalize the efficiency or phase balance of the converter.

The general expression for maximum voltage stress as a function of V_in across each of the converter switches, relative to the converter order, is summarized in

Table 2. An example of maximum switch voltages vs. the number of cells.

	# of Cells	2	3	4	5	6	7	8
Switch
SxL (x ≥ 1) 1		(1/3)Vin	(1/4)Vin	(1/5)Vin	(1/6)Vin	(1/7)Vin	(1/8)Vin	(1/9)Vin
SxH (x > 1) 2		(2/3)Vin	(2/4)Vin	(2/5)Vin	(2/6)Vin	(2/7)Vin	(2/8)Vin	(2/9)Vin

¹ Includes S_1H; ² includes the switch between the last cell to the previous one, S_{(n−1) – (n)}.

. A higher converter order results in a lower voltage stress on both low-side and high-side switches. It is worth noting that low-side switches (S_xL) conduct for much longer periods of time and as a result carry a much higher average current during the discharge states. They are exposed to twice as low a voltage stress as their high-side counterparts, allowing them to select a lower resistance switch to further reduce the losses. High-side switches (S_xH)—except for S_1H and S_{(n−1) – (n)}—experience higher voltage stresses during one of the switching states.

5. Simulation and Experimental Results

The verification and proof-of-concept demonstration of the design methodology are carried out by a simulation and experiments of a three-phase buck converter.

A steady-state simulation waveforms of 40 W, 48 V-to-1 V converter for an output current of 40 A with equal duty ratios of 1/12 is shown in Figure 7. The output voltage, inductors currents, and the sum of the inductor currents in the CCM mode are shown in Figure 7a. Note that due to the three-phase interleaved operation of the converter, the effective switching frequency at the output of the converter triples from 500 kHz to 1.5 MHz. From the results, natural current sharing is observed between phases and a ratio of 2:1 between I_L2 to I_L1 and I_L3 can be seen. The simulation includes switch resistances R_{DS (on)} as outlined in

Table 3. Experimental prototype parameters.

	Power Stage
Component	P/N	Value/Type
Input voltage-Vin		48 V
Output voltage-Vout		1–1.5 V
Switching freq.-fsw		333 kHz per Ph.
Input capacitor-Cin	EEE-FK2A221AV	220 µF, 100 V
Output capacitor-Cout	EEF-GX0D561R	560 µF, 2 V
Inductors-L1, L2, L3	XAL1580_401MEB	0.4 µH, 60 A
Capacitors-C1, C2, C3	C5750X7S2A106M	10 µF, 100 V
MOSFETs (RDS on)	NVMFD5C446NL	2.2 mΩ, 145 A
Load resistance-Rload		10–100 mΩ
	Floating Driver
Driver	2EDF7275F
Isolated DC/DC	TDR 3-1212SM
	Digital Section
Microcontroller	dsPIC33FJ16GS502	16 bit, 40 MIPS
Buffers and Drivers	MC74VHC244DWR2G

, so that the output voltage and current are slightly lower than theoretically expected. The maximum voltage stress of V_in/2 on the switches S_2H, S_2-3, and S_3H is demonstrated in Figure 7b.

A simulation of a multiphase converter with two 1 × 3 modules is shown in Figure 8. The converter is rated at 80 W, steps the voltage down from 48 V-to-1 V, and operates at a switching frequency of 500 kHz per-phase. The converter consists of two modules (m = 2) that are connected in parallel, each with a chain of three cells (n = 3). Both converters are identical and operate with the same duty ratio that results in an output voltage of 1 V. Simulation results of Figure 8 demonstrate equal current levels and shapes for each of the modules, and the total output current is the sum of the two currents from each module, i.e., I_outT = I_o1 + I_o2.

To demonstrate the current sharing robustness of the topology in a presence of inductors mismatch, a simulation of the converter operating under heavy load conditions of V_in = 48 V, V_out = 1 V, and I_out = 100 A, with equal duty ratio and different inductance values of L₁ = 0.6 µH, L₂ = 0.2 µH, and L₃ = 0.5 µH is shown in Figure 9. The simulation demonstrates a difference between L₁ and L₃ on the level of a component tolerance mismatch, and a major inductance disproportion is demonstrated using a very low inductance of L₂ comparing to L₁ and L₃. The average currents are equal to I_L1 = I_L3 = I_out/4 = 25 A and I_L2 = 2I_out/4 = 50 A, similar to the case of equal inductances, maintaining current sharing for even the high inductance difference. The change that could be observed is in the current ripple. It should be noted that a CCM operation mode needs to be maintained to ensure current sharing and overall correct converter operation.

To validate the operation of the three-phase topology at a high voltage and high conversion ratio, a 100 W laboratory prototype that operates at a switching frequency of 333 kHz per phase was built and tested. Table 3 lists the components’ values and nominal parameters of the experimental prototype. Each phase in the converter has been designed to be identical, as can be seen in the photograph of the experimental prototype (Figure 10). Each cell is comprised of an inductor, a flying capacitor that consists of two 10 µF capacitors connected in parallel to reduce the ESR, and a dual N-Channel MOSFET. A microchip dsPIC33 controller is used to generate complementary gate waveforms for switches S_xL and S_xH. The experiments are performed with an output voltage range of 1–1.5 V and maximum load of 100 A. Figure 11 shows the three-phase inductors currents and the output current, which is the sum of all three-inductors currents, (interleaved mode), i.e., I_o = 10 A and V_o = 1.5 V. We measured average capacitors voltages, and the output voltages are V_C1 ≈ 36 V, V_C2 ≈ 24 V, V_C3 ≈ 12 V, and V_o ≈ 1.5 V, as demonstrated in Figure 12, and fully support the theoretical derivations. The existence of soft charge has been demonstrated by measuring the capacitors currents (Figure 13). Please note that the minor spikes in Figure 13 are the result of a nonideal current measurement setup. The measured voltages on all the switches are shown in Figure 14. As can be seen from the experimental results, the maximum voltage stress on switches S_1L, S_2L, S_1H, and S_3L is V_in/4 and the maximum voltage stress on switches S_2H, S_2-3, and S_3H is V_in/2. The results align well with the theoretical analysis that is summarized in Table 1. The power stage efficiency is shown in Figure 15. Three output voltages of 1.0 V, 1.2 V, and 1.5 V are demonstrated operating off a constant input voltage of 48 V.

Table 4. A performance review of state-of-the-art single-stage wide conversion ratio solutions.

Topology /Reference	Voltage Ratio (Vo/Vin)	Regulated	Tested Range (Vin to Vo)	# L 1	# C 1	Capacitors Stress 2	Active Components	Switches Stress 2 (Vblocking)	Peak Efficiency [%] (Power Stage)
This Work -x3 LC Cells	D/4	Yes	48 to 1–1.8 V	3	3	(3Vin/4), (Vin/2), (Vin/4)	7 SW	5 × (Vin/4), 2 × (Vin/2)	97.8 (40 A/1.8 V) 95.6 (38 A/1 V)
Multiphase Buck-5ph. [55]	D	Yes	12 to 1.8 V	5	0	--	10 SW	10 × (Vin)	94.8 (55 A/1.8 V)
Series Cap Buck-3ph. [27]	D/3	Yes	19 to 1.2 V; 16.8 to 0.9 V	3	2	(2Vin/3), (Vin/3)	6 SW	2 × (2Vin/3), 4 × (Vin/3)	93 (5 A/1.2 V)
Multi-Resonant- Doubler [16]	Fixed- ratio	No	48 to 6 V	1	3	(4Vo), (2Vo), (Vo)	10 SW	4 × (4Vo), 3 × (2Vo), 3 × (Vo)	98.6 (5 A/6 V)
Multi-Resonant Cascaded Series-Parallel Converter [17]	Fixed- ratio	No	48 to 8 V	1	3	1 × (3Vo), 2 × (Vo)	10 SW	4 × (3Vo), 2 × (2Vo), 4 × (Vo)	99 (5 A/8 V)
Cross-Coupled Series-Capacitor Quadruple Buck Converter [19]	D/4	Yes	48 to 1 V	2	3	1 × (Vin/2), 2 × (Vin/3)	8 SW, 2x Diodes	6 × (Vin/4), 2 × (Vin/2)	94.5 (15 A/1 V) 95.1 (17 A/1.8 V)
Seven-Level Multiphase Multi-Inductor Hybrid Converter [21]	D/6	Yes	48 to 1–2 V	3	5	(5Vin/6), (4Vin/6), (3Vin/6), (2Vin/6), (Vin/6)	9 SW	NA	94.6 (8 A/2 V) 92 (7 A/1 V)

¹ The total number of inductors or capacitors in the power stage. ² The stress on the capacitors and switches is quantified as the product of the number of components and their respective voltage stress. For example, the stress is calculated as N × (V_in/k), where N capacitors or switches equally share a voltage stress of V_in/k.

presents a performance review of state-of-the-art single-stage wide conversion ratio solutions and this work.

6. Conclusions

A modular construction approach of a very-high conversion ratio multiphase converter, based on a generic, switched LC cell is presented. The converter is built from a chain of identical building blocks, each consisting of a switched inductor–capacitor pair that forms a stacked series-capacitor converter at the input; while at the output, the converter has a structure of parallel or interleaved inductors. This modular stacking of generic cells allows flexibility in the design, enabling a high-power and high-conversion ratio without sacrificing the efficiency of the converter. It becomes possible due to the single-cycle power processing from the source to load operation principle, regardless of the number of modules stacked. Additional features of the architecture include the soft charging operation of the series capacitors, a voltage stress reduction of the switches due to the series capacitor’s structure, and current sharing across the phases. Current sharing is maintained throughout the multiphase output, allowing state-of-the-art performance in terms of power considerations and converter sizing for operation in both steady-state and transient modes. These characteristics contribute to a more compact system design and higher efficiency, particularly in direct 48 V-to-1.x V conversions, commonly required in data centers and other advanced applications. The performance of the proposed approach is validated through an interleaved three-phase modular prototype, which demonstrates excellent agreement with theoretical predictions and simulation results.

The technique of generic cell copying and multiplication presented here significantly reduces the complexity of the design and implementation of switched-mode power converters for multiple use cases. The concept of generalization extends the capability of supporting higher currents and power by connecting the m number of modules in parallel. Mismatches between phases or between modules can be adjusted by controlling the duty cycle of each cell independently if needed. The resulting architecture enables one to seamlessly achieve any conversion ratio using identical cells or modules. This ultimately establishes the enabling technology for reliable, fast, and power-oriented design of high conversion ratio power-converters, as a new baseline in the field.