Search Results (318)

As the deployment of Internet of Things (IoT) ecosystems accelerates, safeguarding distributed networks against pervasive security and privacy threats has become a paramount concern. Integrating robust cryptographic protocols directly onto resource-limited edge devices offers a promising line of defense. However, severe hardware constraints historically complicate practical implementation. Because finite-field arithmetic fundamentally dictates the speed and efficiency of these cryptographic primitives, optimizing underlying multiplication techniques remains critical. To address these challenges, this paper presents an innovative, highly regular bit-serial systolic architecture tailored specifically for Dickson modular multiplication in binary extension fields. This is achieved via a streamlined systolic mapping over $GF\left(2^l\right)$ using dependency graph extraction, scheduling vectors, and projection directions. With localized pathways, the structure is highly optimized for VLSI integration. The performance and effectiveness of the proposed system are thoroughly evaluated and validated through comprehensive simulation results. Based on analytical and gate-level modeling, the design significantly enhances efficiency, lowering area by at least $162.8\%$, power by at least $214.3\%$, Area–Time Product by at least $5\%$, and Time–Power Product by at least $25.6\%$. These findings confirm that the proposed architecture substantially outperforms state-of-the-art bit-serial multipliers across these key evaluation metrics. Consequently, this solution serves as an ideal cryptographic engine for tightly constrained IoT hardware and embedded nodes, reinforcing secure and energy-aware data processing. By fostering resilient infrastructure and green digital practices, the work directly supports sustainable digital transformation and robust edge computing security. Full article

This paper presents an FPGA (Field-Programmable Gate Array) implementation of a low-power VLSI (Very Large-Scale Integration) architecture for medical image scaling in portable diagnostic systems. The proposed architecture employs bilinear interpolation optimized through FSM (Finite-State-Machine)-based control, a clock-enable technique, and selective block activation to reduce switching activity and dynamic power consumption while preserving image quality. The architecture is described in Verilog HDL, synthesized using Vivado 2024.1, and implemented on the Xilinx Zynq-7000-based ZedBoard platform. A controlled post-implementation power analysis on the same FPGA platform demonstrates a reduction in estimated total on-chip power from 3.739 W for the unoptimized baseline architecture to 1.053 W for the optimized architecture, corresponding to an approximately 71.8% reduction. The system supports multiple operational modes, including original image display, grayscale conversion, Sobel X filtering, and Sobel Y filtering, providing enhanced diagnostic flexibility. Quantitative assessment of the exemplary X-ray Image 1 yielded PSNR (Peak Signal-to-Noise Ratio) of 42.97 dB and SSIM (Structural Similarity Index) of 0.9557, demonstrating satisfactory image-quality preservation after scaling. The proposed architecture demonstrates the feasibility of low-power FPGA-based medical image scaling for portable diagnostic and telemedicine imaging systems, offering an effective balance between energy efficiency and image fidelity. Full article

The transition to a globalized, fabless semiconductor manufacturing model has integrated third-party foundries and external intellectual property (IP) vendors into the integrated circuit (IC) design cycle. While this collaborative system promotes innovation, it also exposes layouts to security threats. Protecting these designs is paramount; however, applying traditional encryption methodologies fundamentally alters the syntactic hierarchy of the industry-standard GDSII stream format, causing electronic design automation (EDA) tools to crash. Furthermore, a full encryption hinders modern system-on-chip (SoC) development, where different teams require access to specific modules of the design, without exposing the entire IP. To resolve this issue between collaborative layout sharing and zero-trust security, this paper presents a software implementing an encryption engine. By applying the NIST-standardized FF1 Format-Preserving Encryption (FPE) algorithm directly to the geometric data, the proposed software obfuscates sensitive spatial coordinates and structural nomenclature while maintaining the native GDSII format. The engine embeds multi-tiered cryptographic access control directly into the layout, utilizing native metadata properties. This framework allows proprietary logic to be securely compartmentalized, ensuring that interacting parties only view the specific structures they possess the clearance to decrypt. Full article

This paper, after an overview of most of the improved Domino Logic topologies with keeper, provides an in-depth and comprehensive comparison of the simplest keeper architectures: the Delayed Keeper, the Conditional Keeper, the Split Keeper and their combined variants. A design strategy for setting the keeper aspect ratio to satisfy a target noise immunity requirement is presented in the paper. All the considered topologies are then evaluated through extensive Monte Carlo simulations, assessing delay and its standard deviation, power consumption and Power–Delay–Product, as well as noise immunity and sensitivity to layout-dependent parasitics, implementing a wide set of logic gates in a 28 nm CMOS technology. A further comparison of the topologies, when the gates are cascaded to realize a simple Datapath, suggests that the Split Keeper, while being the simplest topology, generally provides a very favorable speed–power trade-off. In particular, although the speed advantage with respect to the more complex Delayed topologies is marginal, it generally results in less than half the power consumption and PDP. Full article

Logic synthesis is a critical stage in the VLSI design flow. Logic synthesis methods without considering physical information would result in inferior solutions with timing violations and fail to meet high-performance design requirements. In this paper, we present an analytical placement algorithm that generates timing-friendly physical information to promote high-performance logic synthesis solutions. To address the crucial congestion issue, we first propose a fence-region-aware density model. Then, a boundary-based quadratic penalty model is constructed to ensure the cells do not violate the legal boundaries. Finally, we develop a Polak–Ribière-based placement algorithm to guide the cell movement while optimizing circuit timing. Compared to the advanced placement work, the experimental results on industrial benchmarks show that our proposed algorithm achieves 7% WNS improvement and 12% TNS optimization with 3% better logic depth. Full article

This article aims to synthesize the current ecosystem of open-source tools for Integrated Circuit (IC) design, covering the entire digital design flow from Register-Transfer Level (RTL) description to fabricable layouts. The survey categorizes and analyzes tools across major stages of design, including code-generation tools, logic synthesis, simulation, and physical design flow. Special emphasis is given to the fabricable open-source Process Design Kit (PDK), which enables the physical realization of open-hardware projects. By examining interoperability, limitations, and maturity across this toolchain, the article provides a comprehensive overview of the Electronic Design Automation (EDA) landscape and identifies the research and educational opportunities that arise from democratizing silicon design through open and reproducible workflows. Full article

Tunnel Field-Effect Transistors (TFETs) are being explored for ultra-low-power very-large-scale integrated circuits (VLSI) because their band-to-band tunnelling (BTBT) transport permits subthreshold swings (SS) below the 60 mV/dec thermionic limit at room temperature, along with significantly lower leakage than MOSFETs. This paper presents a systematic TCAD study of DG-TFETs that maps how four primary knobs–gate dielectric materials, silicon channel thickness, temperature variation, and different channel material shape key figures of merit: the ON current (I_ON), OFF current (I_OFF), threshold voltage (V_TH), SS, and the I_ON/I_OFF switching ratio. High-k gate enhances gate-to-channel coupling and boost tunnelling efficiency; rigorous body scaling enhances electrostatic control; and targeted source-proximal doping profiles elevate I_ON while minimizing leakage. We also measure the trade-offs between I_ON, SS, and I_OFF that occur when scaling is performed at the same time. This shows that careful coordination is needed instead of just tuning one parameter. This is a simulated work, and the physical models are calibrated to experimental TFET data and all parameters are checked against previously reported results. The device reaches SS = 31.4 mV/dec, V_TH = 0.46 V, I_ON = 5.91 × 10⁻⁵ A and an I_ON/I_OFF of about 4.5 × 10¹¹. This shows that it can switch quickly with little leakage. The design insights that come from this work provide useful advice regarding how to choose gate dielectric material, structures, and doping strategies to add DG-TFETs to the next generation of low-power semiconductor technologies. Full article

The downscaling of VLSI technologies has exacerbated the susceptibility of integrated circuits (ICs) to radiation-induced Single-Event Transients (SETs). This work presents UPSET, a comprehensive and technology-independent EDA framework for probabilistic SET analysis using Static Timing Analysis (STA). Unlike traditional simulation-based methods that suffer from prohibitive runtimes, UPSET leverages graph-based propagation with advanced logical, electrical, and timing-window masking models to evaluate circuit sensitivity efficiently. Key contributions include a novel “Electrical Masking Window” (EMW) criterion that effectively filters non-full-rail pulses early in reconvergent logic and a TimeStamp-based propagation mode that accurately handles complex signal reconvergence with Boolean evaluation. The experimental results over some featured benchmarks demonstrate a speedup of more than 25,000× compared with SPICE while maintaining a tight 4.56% error bound in pulse width estimation. Moreover, experimental validation on 50 benchmarks across varying complexities showcases that EMW enhancement reduces the pessimism to circuit sensitivity by up to 25% on average, providing tighter upper bounds while maintaining scalability to million-gate designs. By integrating seamlessly with standard industrial formats (LEF, DEF, LIB, or SPEF), UPSET enables scalable, accurate soft SET sensitivity assessment for modern digital designs, establishing a robust foundation for automated radiation hardening flows. Full article

The increasing complexity of modern Very Large-Scale Integration (VLSI) circuits, combined with unavoidable variations in physical and manufacturing parameters, poses significant challenges for accurate and efficient circuit simulation. Parametric model order reduction (PMOR) provides a viable solution by enabling the construction of compact reduced-order models that remain valid across a prescribed parameter space. However, the computational cost of generating such models can become prohibitive for large-scale circuits, particularly when high-fidelity projection subspaces are required. In this work, we present an efficient PMOR framework based on the Asymmetric Extended Krylov Subspace (AEKS). The proposed approach exploits structural sparsity imbalances between system matrices to guide the subspace expansion toward computationally favorable directions, thereby significantly reducing the cost of repeated linear system solves. By integrating AEKS within a concatenation-of-basis PMOR strategy, this method enables the rapid construction of accurate parametric reduced-order models for large-scale circuit systems. The proposed AEKS-PMOR framework is evaluated on industrial power distribution network benchmarks, where it demonstrates substantial reductions in model construction time compared to conventional EKS-based PMOR, while maintaining high approximation accuracy over the entire parameter space. Full article

This paper presents new fast algorithms for the type VII discrete cosine transform (DCT-VII) applied to input data sequences of lengths ranging from 3 to 8. Fast algorithms for small-sized trigonometric transforms enable the processing of small data blocks in image and video coding with low computational complexity. To process the information in image and video coding standards, the fast DCT-VII algorithms can be used, taking into account the relationships between the DCT-VII and the type II discrete cosine transform (DCT-II). Additionally, such algorithms can be used in other digital signal processing tasks as components for constructing algorithms for large-sized transforms, leading to reduced system complexity. Existing fast odd DCT algorithms have been designed using relationships among discrete cosine transforms (DCTs), discrete sine transforms (DSTs), and the discrete Fourier transform (DFT); among different types of DCTs and DSTs; and between the coefficients of the transform matrix. However, these algorithms require a relatively large number of multiplications and additions. The process of obtaining such algorithms is difficult to understand and implement. To overcome these shortcomings, this paper applies a structural approach to develop new fast DCT-VII algorithms. The process begins by expressing the DCT-VII as a matrix-vector multiplication, then reshaping the block structure of the DCT-VII matrix to align with matrix patterns known from the basic papers in which the structural approach was introduced. If the matrix block structure does not match any known pattern, rows and columns are reordered, and sign changes are applied as needed. If this is insufficient, the matrix is decomposed into the sum of two or more matrices, each analyzed separately and transformed similarly if required. As a result, factorizations of DCT-VII matrices for different input sequence lengths are obtained. Based on these factorizations, fast DCT-VII algorithms with reduced arithmetic complexity are constructed and presented with pseudocode. To illustrate the computational flow of the resulting algorithms and their modular design, which is suitable for VLSI implementation, data-flow graphs are provided. The new DCT-VII algorithms reduce the number of multiplications by approximately 66% compared to direct matrix-vector multiplication, although the number of additions decreases by only about 6%. Full article

With continued transistor scaling and increasing interconnect density in very large-scale integration (VLSI) circuits, the parasitic capacitance of interconnect has become a major contributor to circuit delay and signal integrity degradation. Fast and accurate parasitic capacitance extraction is therefore essential in the back-end-of-line (BEOL) stage. Currently, 2.5D parasitic capacitance extraction flow based on the pattern matching method is widely used by commercial tools, which still suffer from lengthy pattern library construction, cross-section preprocessing, pattern mismatch, and poor accuracy for small capacitance extraction. To overcome these limitations, this work proposes an end-to-end parasitic capacitance extraction workflow, named residual multilayer perceptron interconnect parasitic capacitance extraction (RMLP-Cap), which leverages a residual multilayer perceptron (ResMLP) to enhance traditional workflow. RMLP-Cap integrates parasitic extraction (PEX) window acquisition, pattern definition, feature extraction, dataset generation, ResMLP model training, and capacitance aggregation into a unified flow. Experimental results show that RMLP-Cap can automatically define and model complex 2D patterns with 100% matching accuracy. Compared with a field solver based on the boundary element method (BEM), the ResMLP model achieves an average relative error below 0.9%, a standard deviation under 0.2%, and less than 0.5% error for small capacitances, while providing a 900% speed improvement for extraction speed. Full article

This paper presents an enhanced Ant Colony Optimization (ACO) algorithm tailored for optimizing CMOS physical design in VLSI circuits. As device complexity escalates, traditional placement techniques struggle with multiobjective goals such as minimizing layout area, wirelength, and achieving effective aspect ratios. The proposed ACO framework simulates artificial ant colonies exploring layout configurations and reinforcing promising solutions through a pheromone-guided heuristic. Evaluated on a benchmark containing ten typical logic blocks—Adder, Multiplier, Shifter, MUX, Register, ALU, Decoder, Control, Cache, and Buffer—the ACO method achieves a maximum layout area reduction of 27.27% (from 1760 to 1280 units²) and improves the aspect ratio from 3.64 to 5.0 compared to traditional layouts. The mean area reduction observed across different parameter settings is approximately 20%. The system also includes a fully configurable and modular automation tool designed for flexible parameter tuning and the rapid benchmarking of the ACO algorithm. This tool enables users to easily adjust key parameters such as number of ants, iteration count, pheromone evaporation rate, and heuristic influences, allowing for a comprehensive exploration of the optimization space. Experimental results demonstrate ACO’s scalability, adaptability, and effectiveness, establishing it as a viable approach for automation in complex physical designs. Future work will focus on hybrid algorithms and multi-objective optimization extensions. Full article

In this review, we focus on group IV one-dimensional devices for quantum technology. We outline the foundational principles of quantum computing before delving into materials, architectures and fabrication routes, separately, by comparing the bottom-up and top-down approaches. We demonstrate that due to easily tunable composition and crystal/interface quality and relatively less demanding fabrications, the study of grown nanowires such as core–shell Ge-Si and Ge hut wires has created a very fruitful field for studying unique and foundational quantum phenomena. We discuss in detail how these advancements have set the foundations and furthered realization of SETs and qubit devices with their specific operational characteristics. On the other hand, top-down processed devices, mainly as Si fin/nanowire field-effect transistor (FET) architectures, showed their potential for scaling up the number of qubits while providing ways for very large-scale integration (VLSI) and co-integration with conventional CMOS. In all cases we compare the fin/nanowire qubit architectures to other closely related approaches such as planar (2D) or III–V qubit platforms, aiming to highlight the cutting-edge benefits of using group IV one-dimensional morphologies for quantum computing. Another aim is to provide an informative pedagogical perspective on common fabrication challenges and links between common FET device processing and qubit device architectures. Full article

As the complexity of Very-Large-Scale Integration (VLSI) circuits escalates, Design-for-Test (DFT) faces significant challenges. Traditional script-based automation flows are increasingly complex and present a high technical barrier for non-specialists. In order to overcome the above issue, this paper introduces DFTAgent, a novel framework that leverages Large Language Models to intelligently orchestrate a DFT toolchain. DFTAgent is evaluated on the ISCAS’85, ISCAS’89, and ITC’99 benchmarks. The results demonstrate that DFTAgent successfully completes the complete ATPG task cycle, achieving fault coverage comparable to a manually scripted baseline while exhibiting significant advantages in flexibility and error handling. By abstracting complex DFT tools behind a natural language interface and a visual workflow, this approach promises to democratize access to advanced VLSI testing methodologies and accelerate design cycles. Full article

Adverse climate events have recently highlighted an increasing need to deploy sustainable energetic infrastructures. The existing electric conversion circuits for solar energy provide high efficiency; however, gaps in sustainability and robustness can be identified by considering their operation during intense perturbations, potentially occurring for interplanetary energy transfer. Additionally, charging characteristics for energy storage units influence differently the operation life of battery arrays, with increased stability providing favorable operating conditions. Therefore, the present study develops an alternative controller for managing solar energy as well as a prototype for tracking the maximum power point, both constrained by robustness and renewability studies. For the presented design, stability analyses and simulations validated the management of electric energy from solar panels and the developed configuration resulted in improving current peak integral transient characteristics by using an alternative control method, demonstrating stability for an indefinite number of energy storage units. Furthermore, the estimation for VLSI (Very-Large-Scale Integration) of this constrained design has been concluded to potentially provide a solution with adequate performance, comparable to state-of-the-art computational circuits. However, certain limitations could arise when substituting the main computation parts with analyzed solutions and proceeding with integration-based manufacturing. Full article