Next Article in Journal
Cross-Course Knowledge Tracing for Student Performance Prediction in MOOCs
Previous Article in Journal
A Novel Intersection-Statistics-Based Indoor TOA Localization Algorithm with Adaptive Error Correction for NLOS Environments
Previous Article in Special Issue
Novel Low-Power CNFET-GAAFET Based Ternary 9T SRAM Design for Computing-in-Memory Systems
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

Parametric Model Order Reduction for Large-Scale Circuit Models Using Extended and Asymmetric Extended Krylov Subspace

by
Chrysostomos Chatzigeorgiou
1,*,
Pavlos Stoikos
1,
George Floros
2,
Nestor Evmorfopoulos
1 and
George Stamoulis
1
1
Department of Electrical and Computer Engineering, University of Thessaly, 38221 Volos, Greece
2
Department of Electronic and Electrical Engineering, Trinity College Dublin, D02 PN40 Dublin, Ireland
*
Author to whom correspondence should be addressed.
Electronics 2026, 15(3), 640; https://doi.org/10.3390/electronics15030640
Submission received: 16 December 2025 / Revised: 25 January 2026 / Accepted: 27 January 2026 / Published: 2 February 2026
(This article belongs to the Special Issue Modern Circuits and Systems Technologies (MOCAST 2024))

Abstract

The increasing complexity of modern Very Large-Scale Integration (VLSI) circuits, combined with unavoidable variations in physical and manufacturing parameters, poses significant challenges for accurate and efficient circuit simulation. Parametric model order reduction (PMOR) provides a viable solution by enabling the construction of compact reduced-order models that remain valid across a prescribed parameter space. However, the computational cost of generating such models can become prohibitive for large-scale circuits, particularly when high-fidelity projection subspaces are required. In this work, we present an efficient PMOR framework based on the Asymmetric Extended Krylov Subspace (AEKS). The proposed approach exploits structural sparsity imbalances between system matrices to guide the subspace expansion toward computationally favorable directions, thereby significantly reducing the cost of repeated linear system solves. By integrating AEKS within a concatenation-of-basis PMOR strategy, this method enables the rapid construction of accurate parametric reduced-order models for large-scale circuit systems. The proposed AEKS-PMOR framework is evaluated on industrial power distribution network benchmarks, where it demonstrates substantial reductions in model construction time compared to conventional EKS-based PMOR, while maintaining high approximation accuracy over the entire parameter space.

1. Introduction

The continuous scaling of semiconductor technologies has enabled the realization of highly complex integrated circuits with dense interconnected structures and extensive power delivery networks. As feature sizes shrink and operating frequencies increase, the accurate modeling of these large-scale electrical systems becomes increasingly critical for ensuring performance, signal integrity, and reliability [1]. Such models, often derived from detailed physical descriptions, can involve millions of state variables, making direct numerical simulation computationally prohibitive in terms of both runtime and memory consumption [2]. This challenge is further exacerbated in modern design flows, where repeated analyses are required during verification, optimization, and variability assessment.
Model order reduction (MOR) has therefore become an indispensable tool for efficient circuit simulation [3]. By projecting a high-dimensional system onto a suitably chosen low-dimensional subspace, MOR enables the construction of compact reduced-order models that preserve the essential input–output behavior of the original circuit. Projection-based techniques founded on moment matching (MM) and Krylov subspaces are particularly well suited to large-scale circuit problems, as they exploit matrix sparsity and scale favorably with system size [4]. While these methods have proven highly effective for reducing nominal circuit models over a prescribed frequency range, their applicability becomes limited when variations in circuit parameters must be taken into account [5].
In particular, circuit behavior is strongly influenced by parametric variations arising from manufacturing tolerances, material uncertainties, geometric deviations, and operating conditions such as temperature [6]. A reduced model constructed for a single nominal configuration may therefore lose accuracy when evaluated under perturbed conditions. Recomputing a reduced model for each parameter realization is computationally expensive and undermines the efficiency benefits of MOR. To address this limitation, research shifted towards Parametric MOR (PMOR), allowing parameters to be retained as symbolic variables within the reduced-order model, as comprehensively surveyed by Benner [7]. However, the construction of accurate and compact parametric models remains challenging, particularly as the number of parameters and ports increases [8].
Early PMOR techniques often relied on multi-parameter moment matching or Taylor-series expansions with respect to both frequency and design parameters [5,9,10]. Although these approaches can achieve high accuracy, they frequently lead to rapid growth in model dimensions due to the proliferation of cross-parameter moments. Sampling-based strategies, such as the concatenation of locally reduced bases obtained at different points in the parameter space, alleviate some of these issues by avoiding explicit multi-parameter expansions [11,12]. Nevertheless, the computational cost associated with generating multiple high-quality local bases can still be substantial, especially for large-scale circuit models.
The conflict between spectral accuracy and model compactness constitutes a central bottleneck for modern parametric systems. To address this, the Extended Krylov Subspace (EKS) has been proposed as a solution [4,13,14]. This method improves approximation quality by combining information from both low and high frequencies. Consequently, it achieves superior accuracy compared to standard Krylov techniques. However, the direct application of EKS in a parametric setting is computationally prohibitive [15]. Constructing an EKS basis requires the inversion of system matrices. In a parametric context, these matrices depend on variable quantities. This renders the inversion operationally expensive or symbolically intractable. Although Asymmetric EKS (AEKS) techniques maximize efficiency for static systems, no existing framework has successfully extended this efficiency to the parametric domain.
In this work, we propose a parametric model order reduction framework that integrates the Asymmetric Extended Krylov Subspace (AEKS) into the PMOR process. The proposed AEKS-PMOR methodology exploits sparsity in order to significantly reduce the computational runtimes and memory requirements. More specifically, the main contributions are summarized hereafter:
  • We introduce a parametric model order reduction methodology that integrates the AEKS into a projection-based PMOR framework, enabling the efficient construction of reduced-order models that remain accurate across a prescribed parameter space.
  • The proposed approach exploits structural sparsity imbalances between circuit system matrices to guide the Krylov subspace expansion toward computationally cheaper linear solves, substantially reducing the cost of basis generation compared to other Krylov methods.
  • AEKS is combined with a concatenation-of-basis strategy to generate a single global projection subspace from multiple parameter samples, allowing accurate parametric modeling without explicit multi-parameter moment expansions.
  • We demonstrate, experimentally, using industrial IBM power grid benchmarks [16], that the AEKS-PMOR method achieves significant runtime speedup compared to EKS-PMOR, while maintaining negligible approximation error.
The remainder of this paper is organized as follows. Section 2 presents the relevant background on MOR and PMOR. Section 3 analyzes the proposed AEKS methodology and its integration into PMOR. Section 4 presents our experimental results on the IBM benchmarks, and Section 5 summarizes the conclusions.

2. Background

2.1. Model Order Reduction

In the time domain, using the Modified Nodal Analysis (MNA), the state space model is described by a Partial Differential Equation:
G x ( t ) + C d x ( t ) d t = Bu ( t ) y ( t ) = L x ( t )
where n N is the number of nodes in the system, p N is the number of ports, G R n × n is the conductance matrix, C R n × n is the capacitance matrix, B R n × p is the input-to-state connectivity matrix, q N is the number of monitor points, and  L R q × n is the state-to-output connectivity matrix.
The objective of MOR is to produce a reduced-order model similar to (1):
G ˜ x ˜ ( t ) + C ˜ d x ˜ ( t ) d t = B ˜ u ( t ) y ˜ ( t ) = L ˜ x ˜ ( t )
where G ˜ , C ˜ R r × r , B ˜ R r × p , L ˜ R q × r .
The reduced model has order r < < N , and the output error is bounded by | | y ˜ ( t ) y ( t ) | | 2 and it is small.
In the frequency domain, the transfer functions of the original ( H ( s ) ) and the reduced-order model ( H ˜ ( s ) ) are
H ( s ) = L ( s C G ) 1 B H ˜ ( s ) = L ˜ ( s C ˜ G ˜ ) 1 B ˜
The output error in the frequency domain is
| | H ˜ ( s ) H ( s ) | |
where | | . | | is the induced L 2 matrix norm, or  H norm, of a rational transfer function.
From (1), after taking the Laplace transformation:
s CX ( s ) X ( 0 ) = G X ( s ) + B U ( s ) Y ( s ) = L X ( s )
Assuming we have zero initial conditions, X ( 0 ) = 0 , the above system of Equation (5) becomes
( s C G ) X ( s ) = B
Y ( s ) = L X ( s )
From Taylor expansion X ( s ) around zero, we derive the below equation:
( s C G ) ( x 0 + x 1 s + x 2 s 2 + x 3 s 3 + ) = B
The transfer function of (1) is a function of s, and can be expanded into a moment expansion around s = 0 as follows:
H ( s ) = M 0 + M 1 s + M 2 s 2 + M 3 s 3
where M 0 , M 1 , M 2 , M 3 , … are the moments of the transfer function. Finally, M i is connected to the system matrices as
M i = L ( G 1 C ) i G 1 B
The purpose of MM reduction approaches is to derive a reduced-order model in which certain moments M ˜ i of the reduced-order transfer function H ˜ ( s ) correspond to some moments of the original transfer function H ( s ) [4,15].

2.2. Parametric Model Order Reduction

Parameterization is crucial in integrated circuit (IC) design, as even minor deviations in geometry or physical attributes can significantly alter system performance. Traditional approaches, which require recalculating the model from scratch for every parameter variation, are computationally inefficient and impractical due to strict time-to-market constraints. Consequently, there is a strong need for parametric discretized systems that can inherently accommodate parameter changes. Such systems eliminate the burden of repeating the entire modeling and reduction process for each design scenario, thereby drastically reducing the simulation time. To derive a parametric reduced model, the original system in (1) must be reformulated to explicitly include parameter dependencies. This allows for the modification of parameter values directly within the model structure without necessitating a re-assembly of the system equations or a fresh reduction step. The parametric state-space representation is given by
G ( λ ) x ( t , λ ) + C d x ( t , λ ) d t = B u ( t ) y ( t , λ ) = L x ( t , λ )
where G , C R n × n matrices represent conductance and capacitance, B R n × p is the power distribution matrix, and L R q × n is the state-to-output connectivity matrix. The elements of G and C , as well as the states of the system x , rely on a parameter set λ = λ 1 , , λ m , reflecting the impact of different materials analyzed for each part of the device during simulation. To be more precise, each parameter λ i is associated with a particular scaling factor for conductance or capacitance. Similarly to (2), the parametric transfer function of the original model is computed as
H ( s , λ ) = L ( s C ( λ ) G ( λ ) ) 1 B
for which we seek to generate a Reduced Order Model (ROM) approximation, which will be able to accurately capture the input/output behavior of the system for any possible combination in the parameter space:
H ˜ ( s , λ ) = L ˜ ( s C ˜ ( λ ) G ˜ ( λ ) ) 1 B ˜
Finally, parametric and non-parametric parts can be written as
( s ( C 0 + i = 1 m C i λ i ) ) ( G 0 + i = 1 m G i λ i ) x ( s , λ ) = B u ( s ) y ( s , λ ) = L x ( s , λ )
where C 0 and G 0 are the non-parametric components’ capacitance and conductance values, while C i and G i are the parameter-scaled values. The procedure can produce a similar ROM using a projection matrix and different parameter values.
( s ( C ˜ 0 + i = 1 m C ˜ i λ i ) ) ( G ˜ 0 + i = 1 m G ˜ i λ i ) x ( s , λ ) = B ˜ u ( s ) y ( s , λ ) = L ˜ x ( s , λ )
where G ˜ 0 , G ˜ 1 , , G ˜ m , C ˜ 0 , C ˜ 1 , , C ˜ m R r × r , B ˜ R r × p , and  L ˜ R q × r are the reduced matrices, with  r < < N .

3. Proposed Methodology

3.1. EKS

In order to compute a projection subspace of a matrix, we use a Krylov sequence. However, this sequence is not orthonormal. For this reason there are appropriate methods, which make these sequences orthonormal. We use this orthonormal basis as a projection matrix to calculate the reduced-order model of the system using MM methods. From the desired order of the reduced system r, the number of ports of the system p, and the number of moments k = r p , we calculate the projection matrix V R N × r ( r < < N ), whose columns span the k-dimensional Krylov subspace:
K k ( A E , R E ) = s p a n { R E , A E R E , A E 2 R E , , A E k 1 R E }
where
A E G 1 C , R E G 1 B
Then, for the reduced-order model, we have
C ˜ = V T C V , G ˜ = V T G V , B ˜ = V T B , L ˜ = L V
where C ˜ , G ˜ R r × r , B ˜ R r × p , L ˜ R q × r [4].
The subspace selection has no bearing on the projection process, but it has a significant impact on how well it works. Therefore, one option is to take into account the rational Krylov subspace [17,18]. However, a set of shift parameters must be input into this projection subspace; the choice of these shift parameters has a significant impact on the final reduced-order model. The typical Krylov subspace [19,20] K k ( A E , R E ) must be enhanced with knowledge from the subspace K k ( A E 1 , R E ) , which corresponds to the inverse matrix A E 1 , in order to handle this problem, resulting in EKS:
K k E ( A E , R E ) = K k ( A E , R E ) + K k ( A E 1 , R E ) = s p a n { R E , A E 1 R E , A E R E , A E 2 R E , A E 2 R E , , A E ( k 1 ) R E , A E k 1 R E }
The initial state of the EKS approach [21] starts with { R E , A E 1 R E } and then constructs a series of extended subspaces K k E ( A E , R E ) to calculate the matrix V R N × 2 r and build the reduced-order model as explained in (16). The EKS procedure, characterized by the presence of two expansion points: one at zero and another at infinity, as shown in the Algorithm 1 [4,15].
Algorithm 1: Extended Krylov Subspace procedure
Electronics 15 00640 i001

3.2. AEKS

Here, we present the Asymmetric EKS (AEKS) technique. This method minimizes computational cost by assessing the sparsity of matrices A and E and biasing the subspace expansion toward the direction ( A E or A E 1 ) that affords sparser linear solves [22]. The expansion follows a weighted pattern: for every m blocks generated via the sparser solve, only one block is added via the denser solve. Indicatively, for  m = 3 , in a case where E is sparser than A , the method generates one moment block of A E = A 1 E after three blocks of A E 1 = E 1 A , creating the k-dimensional subspace:
K k A E ( A E , B E ) = K k / 4 ( A E , B E ) + K 3 k / 4 ( A E 1 , B E ) = span { B E , A E 1 B E , A E 2 B E , A E 3 B E , A E B E , , A E ( k / 4 ) 1 B E , A E ( 3 k / 4 2 ) B E , , A E 3 k / 4 B E }
Algorithm 2 implements the adaptive AEKS method for a given pair of system matrices ( G , C ), with the goal of constructing a reduced orthonormal basis that adapts dynamically to the properties of the problem. The algorithm first examines the relative sparsity of the conductance and capacitance matrices to determine an efficient ordering of linear system solves (steps 2–10). During the iterative subspace expansion, the block size m is dynamically adjusted according to the sparsity imbalance ratio ρ , which reflects the relative computational cost of solving linear systems associated with G and C (steps 13–17). This adaptive adjustment allows the method to balance computational efficiency and subspace enrichment. At each iteration, new candidate basis vectors are generated through a sequence of linear solves, orthogonalized against the existing subspace, and appended to the current basis (steps 12–40). To assess the quality of the evolving reduced subspace, the algorithm evaluates the approximation accuracy at a set of representative test frequencies selected by Algorithm 3. The approximation error is then estimated using Algorithm 4, which computes a residual-based measure by evaluating how well the reduced solution satisfies the original system equations at the selected frequencies. The adaptive expansion process terminates once the estimated error falls below a prescribed tolerance or the maximum allowable reduced order is reached, yielding a reduced basis that achieves the desired accuracy with minimal computational cost (steps 41–42). The resulting subspace is then returned as the final reduced basis.
Algorithm 2: Adaptive AEKS for a Given ( G , C )
Electronics 15 00640 i002
Algorithm 3: Select Test Points
Electronics 15 00640 i003
Algorithm 4: Estimate Error Indicator
Electronics 15 00640 i004

3.3. PMOR Implementation

In the context of projection matrices with the concatenation of basis technique, the goal is to reduce the dimensionality of a system while preserving its essential dynamics. This technique involves combining or concatenating local basis matrices that capture the behavior of the system under different parameter values. Let us denote the local basis matrices corresponding to parameters p 1 , p 2 , , p k as V 1 , V 2 , , V k . The concatenation of basis technique aims to construct unified projection matrices V using the following equations:
V = [ V 1 , V 2 , , V k ]
Here is an example to illustrate the PMOR algorithm. Suppose we have random sampling of k points and m parameters:
G 0 , G 1 , , G m C 0 , C 1 , , C m
Then, after the matrices G 0 , G 1 , , G m and C 0 , C 1 , , C m have been created, using the E K S and A E K S algorithms, matrices V 1 , V 2 , , V k are obtained. We have to concatenate these matrices to create the matrix V = [ V 1 , V 2 , , V k ] , where V R N × k 2 r .
The final projection matrix V results from the q r ( V ) decomposition into the concatenate matrix. At the end, we take the final reduced matrices:
C ˜ i = V T C i V G ˜ i = V T G i V B ˜ = V T B
Algorithm 5 presents a PMOR framework for large-scale power grid models whose system matrices admit an affine parameterization with respect to a set of scaling factors that capture geometric variations in the underlying interconnect structure. For each parameter λ i , the bounds λ i min and λ i max define the acceptable range of geometric variations (steps 2–4). In the considered power grid setting, each scaling factor corresponds to variations in the width of the power grid lines, which directly affect both the conductance and capacitance matrices. The algorithm first generates an m-dimensional scaling-factor λ (steps 5–7). Using this vector, in steps 8–9, the parameter-dependent system matrices are assembled as G ( λ ) = G 0 + i = 1 m λ i G i and C ( λ ) = C 0 + i = 1 m λ i C i . Next, a projection subspace V is constructed using one of two Krylov-based techniques, selected via the input parameter subspace_method (steps 10–13). If subspace_method = EKS, EKS is generated using the matrix pair G ( λ ) 1 C ( λ ) , G ( λ ) 1 B . Otherwise, if subspace_method = AEKS, an adaptive AEKS is computed based on a stopping criterion controlled by the tolerance ε tol . Finally, the reduced-order parametric model is obtained by projecting all parametric conductance and capacitance matrices, as well as the input matrix, onto subspace V (steps 14–17). The resulting reduced matrices C ˜ i , G ˜ i , and  B ˜ preserve the affine parametric structure of the original system while enabling efficient simulation across different geometric deviations in the power grid.
Algorithm 5: Parametric Model Order Reduction with Adaptive AEKS and EKS
Electronics 15 00640 i005

4. Experimental Results

4.1. System Modeling and Parameterization Setup

The evaluation of the proposed AEKS-PMOR methodology was conducted using a set of industrial IBM power grid benchmarks [16]. The analysis focuses on the simulation of power distribution networks, where the resistive parameters are physically determined by the cross-sectional geometric characteristics of the interconnects at each metal layer.
It is important to note that geometric variations (such as width and thickness) are the primary source of parametric uncertainty in on-chip interconnects, as they directly modify the resistance and capacitance matrices ( G and C ). Therefore, validating the method against these variations effectively captures the dominant physical instabilities expected in the manufacturing process.
Accordingly, using Modified Nodal Analysis (MNA), the power grid is formulated as a linear dynamical system, consistent with the mathematical formulation and affine parametric dependence presented in Section 2.
To incorporate the physical dependency of the circuit on geometry, we defined a vector of m parameters, λ = λ 1 , , λ m , which capture variations in the interconnect cross-section. Each parameter λ i acts as a scaling factor for the conductor width (W) in specific regions of the chip.
The physical structure of the interconnects is depicted in Figure 1, illustrating the key geometric parameters: width (W), spacing (S), thickness (T), and dielectric height (H).
The effect of these geometric variations on the electrical circuit model is conceptualized in Figure 2. As the width scales by λ , the conductance and capacitance matrices are modified accordingly.
The impact of these parameters on the system matrices is direct:
  • Conductance ( G ): Since electrical conductance is proportional to the cross-sectional area ( A r e a = W · T ), any variation in conductor width translates to a linear modification of the conductance matrix.
  • Capacitance ( C ): Similarly, the parasitic ground capacitance depends on the surface area of the cross-section, following a corresponding linear relationship.
Consequently, this physical dependency aligns directly with the affine parametric structure established in Section 2.
In the experimental setup, the parameter λ varies within the range λ [ 0.2 ,   1.4 ] , simulating significant manufacturing deviations in the cross-sectional geometry. This specific interval was selected to represent severe process variations while maintaining the physical validity of the circuit model. Extreme values beyond these bounds were excluded, as they would correspond to geometric configurations that violate manufacturing constraints, such as minimum spacing rules between power grid conductors (preventing short circuits due to layout collapse).
As the original IBM benchmarks primarily contain resistive elements, the capacitance matrices C m were synthesized using realistic values in the picofarad ( p F ) range to complete the dynamic model, while maintaining consistency with the geometric scaling described above.

4.2. Simulation Environment and Results Analysis

All computations were performed using MATLAB R2025b on a Linux workstation (Intel Core i7 2.7 GHz, 32 GB RAM). For comparative evaluation, the EKS-PMOR, Adaptive AEKS-PMOR, and conventional MM-PMOR methodologies were applied.
The technical specifications of the benchmarks are presented in columns 2–5 of Table 1, while the remaining columns summarize the reduction results:
  • ROM Order: Indicates the order of the reduced systems. To ensure a fair comparison, the final reduced order q was kept strictly identical across all methods (EKS, AEKS, MM). Although Krylov methods may generate larger initial subspaces, the truncation step was calibrated to yield reduced models of the exact same dimension for all comparisons.
  • Max Error (Columns 7, 9, 11): Records the maximum error (infinity norm) between the transfer function of the original and the reduced model ( | | H ˜ ( s ) H ( s ) | | ).
  • Runtime (Columns 8, 10, 12): Displays the model construction time (in seconds).
The results demonstrate that, for a fixed ROM order, both EKS-PMOR and Adaptive AEKS-PMOR achieve significantly lower errors compared to the MM method. Notably, the Adaptive AEKS-PMOR method offers a speedup of 4× to 7× relative to EKS-PMOR, while maintaining error at negligible levels.
The superiority of the proposed methods is illustrated in the Bode plots of Figure 3, Figure 4 and Figure 5. As observed in the error analysis, at the bottom of Figure 4 and Figure 5, the MM method exhibits satisfactory accuracy at low frequencies; however, its error increases rapidly at high frequencies. In contrast, the EKS-PMOR and Adaptive AEKS-PMOR approaches maintain high accuracy across the entire frequency spectrum (broadband accuracy), making them ideal for the reliable simulation of parametric power grid networks.
To further validate the robustness and stability of the proposed method, time-domain transient simulations were conducted. The industrial IBM power grid benchmarks, along with their corresponding ROMs, were simulated in the time range [ 0 , 100 ] seconds using the backward-Euler numerical integration scheme with a fixed timestep of 0.5 s.
Regarding the experimental setup, sinusoidal current sources were applied to a selected subset of the defined input ports of the network to emulate a realistic switching activity scenario during the transient simulation. Specifically, for the validation presented in Figure 6, a total of 10 input ports were excited simultaneously, and the resulting voltage response was monitored at a single output port, as depicted in Figure 6.
As evidenced by the results, the reduced AEKS-PMOR model tracks the response of the original large-scale system with negligible deviation across the entire parameter space. Regarding the physical reliability of the reduced models, extensive numerical validation confirmed that the proposed method yields stable and passive models across the entire parametric variation range λ [ 0.2 , 1.4 ] . Specifically, the reduced systems maintain bounded behavior without exhibiting numerical divergence, effectively preserving the stability properties of the original RC networks, even under significant parametric perturbations.
Finally, beyond the error performance, the proposed AEKS method demonstrates significant advantages in terms of computational resources and memory usage. By selectively expanding the projection subspace only along dominant spectral directions and employing QR decomposition for robust orthogonalization, it avoids the storage of redundant vectors typical of standard symmetric Krylov approaches. This reduction in the memory footprint is critical for large-scale deployment, as it alleviates the bottleneck often faced in parallel computing environments where memory bandwidth is a limiting factor.

5. Conclusions

In this paper, we presented a robust parametric model order reduction (PMOR) methodology based on the Asymmetric Extended Krylov Subspace (AEKS), specifically designed to handle large-scale RC circuits under manufacturing variations. The proposed framework overcomes the computational limitations of standard Extended Krylov methods, enabling the efficient construction of high-fidelity projection subspaces. Experimental results on industrial IBM power grid benchmarks demonstrated that the AEKS-PMOR approach achieves accuracy nearly identical to original large-scale models, maintaining negligible errors across a large wideband frequency spectrum and parameter range.
Furthermore, extensive time-domain validation confirmed that the reduced models remain strictly passive and stable across the entire parametric space, effectively preserving the reliability of the original networks. Future work will focus on exploring the integration of the proposed method with parallel distributed solvers to further enhance scalability.

Author Contributions

Conceptualization, C.C. and P.S.; methodology, C.C., P.S. and G.F.; software, C.C. and P.S.; experimental evaluation, C.C., P.S. and G.F.; writing and manuscript preparation, C.C., P.S. and G.F.; review and editing, G.F., P.S., N.E. and G.S. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Data Availability Statement

The original contributions presented in this study are included in the article; further inquiries can be directed to the corresponding author.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Lanzillo, N.A.; Chu, A.; Bhosale, P.; Dechene, D. Power Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2022, 30, 60–67. [Google Scholar] [CrossRef] [Scilit]
  2. Achar, R.; Nakhla, M.S. Simulation of high-speed interconnects. Proc. IEEE 2001, 89, 693–728. [Google Scholar] [CrossRef] [Scilit]
  3. Floros, G.; Evmorfopoulos, N.; Stamoulis, G. Frequency-Limited Reduction of Regular and Singular Circuit Models Via Extended Krylov Subspace Method. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2020, 28, 1610–1620. [Google Scholar] [CrossRef] [Scilit]
  4. Chatzigeorgiou, C.; Garyfallou, D.; Floros, G.; Evmorfopoulos, N.; Stamoulis, G. Exploiting extended krylov subspace for the reduction of regular and singular circuit models. In Proceedings of the 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, 18–21 January 2021; Association for Computing Machinery: New York, NY, USA, 2021; pp. 773–778. [Google Scholar]
  5. Leung, A.T.-M.; Khazaka, R. Parametric model order reduction technique for design optimization. In Proceedings of the 2005 IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, 23–26 May 2005; IEEE: New York, NY, USA, 2005; Volume 2, pp. 1290–1293. [Google Scholar]
  6. Shi, C.-J.R.; Tian, M.W. Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis. ACM Trans. Des. Autom. Electron. Syst. 1999, 4, 280–312. [Google Scholar] [CrossRef] [Scilit]
  7. Benner, P.; Gugercin, S.; Willcox, K. A survey of projection-based model reduction methods for parametric dynamical systems. SIAM Rev. 2015, 57, 483–531. [Google Scholar] [CrossRef] [Scilit]
  8. Villena, J.F.; Schilders, W.H.A.; Silveira, L.M. Parametric structure-preserving model order reduction. In Proceedings of the 2007 IFIP International Conference on Very Large Scale Integration, Atlanta, GA, USA, 15–17 October 2007; IEEE: New York, NY, USA, 2007; pp. 31–36. [Google Scholar]
  9. Li, P.; Liu, T.; Li, X.; Pileggi, L.T.; Nassif, S.R. Modeling interconnect variability using efficient parametric model order reduction. In Proceedings of the Design, Automation and Test in Europe, Munich, Germany, 7–11 March 2005; IEEE: New York, NY, USA, 2005; pp. 958–963. [Google Scholar]
  10. Daniel, L.; Siong, O.; Chay, L.; Lee, K.; White, J. A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2004, 23, 678–693. [Google Scholar] [CrossRef]
  11. Feng, L.; Yue, Y.; Banagaaya, N.; Meuris, P.; Schoenmaker, W.; Benner, P. Parametric modeling and model order reduction for (electro-)thermal analysis of nanoelectronic structures. J. Math. Ind. 2016, 6, 10. [Google Scholar] [CrossRef] [Scilit]
  12. Gunupudi, P.; Khazaka, R.; Nakhla, M.; Smy, T.; Celo, D. Passive parameterized time-domain macromodels for high-speed transmission-line networks. IEEE Trans. Microw. Theory Tech. 2004, 51, 2347–2354. [Google Scholar] [CrossRef]
  13. Druskin, V.; Knizhnerman, L. Extended Krylov subspaces: Approximation of the matrix square root and related functions. SIAM J. Matrix Anal. Appl. 1998, 19, 755–771. [Google Scholar] [CrossRef] [Scilit]
  14. Simoncini, V. Extended Krylov subspace for parameter dependent systems. Appl. Numer. Math. 2010, 60, 550–560. [Google Scholar] [CrossRef] [Scilit]
  15. Chatzigeorgiou, C.; Floros, G.; Chatzigeorgiou, D.; Evmorfopoulos, N.; Stamoulis, G. Efficient Parametric Model Order Reduction for Large-Scale Circuit Models using Extended Krylov Subspace. In Proceedings of the 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD), Volos, Greece, 2–5 July 2024; IEEE: New York, NY, USA, 2024; pp. 1–4. [Google Scholar]
  16. Nassif, S.R. Power grid analysis benchmarks. In Proceedings of the Asia and South Pacific Design Automation Conference, Seoul, Republic of Korea, 21–24 March 2008; IEEE: New York, NY, USA, 2008; pp. 376–381. [Google Scholar]
  17. Mei, S.; Ismail, Y.I. Stable Parallelizable Model Order Reduction for Circuits with Frequency-Dependent Elements. IEEE Trans. Circuits Syst. I Regul. Pap. 2009, 56, 1214–1220. [Google Scholar]
  18. Zhao, W.; Pang, G.K.H.; Wong, N. Automatic adaptive multi-point moment matching for descriptor system model order reduction. In Proceedings of the International Symposium on VLSI Design, Automation, and Test, Hsinchu, Taiwan, 22–24 April 2013; IEEE: New York, NY, USA, 2013; pp. 1–4. [Google Scholar]
  19. Odabasioglu, A.; Celik, M.; Pileggi, L.T. PRIMA: Passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 1998, 17, 645–654. [Google Scholar] [CrossRef] [Scilit]
  20. Banagaaya, N.; Ali, G.; Schilders, W.H.A.; Tischendorf, C. Implicit index-aware model order reduction for RLC/RC networks. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Dresden, Germany, 24–28 March 2014; IEEE: New York, NY, USA, 2014; pp. 1–6. [Google Scholar]
  21. Golub, G.; Loan, C.F.V. Matrix Computations; Johns Hopkins University Press: Baltimore, MD, USA, 1996. [Google Scholar]
  22. Davis, T.A.; Natarajan, E.P. Algorithm 907: KLU, A Direct Sparse Solver for Circuit Simulation Problems. ACM Trans. Math. Softw. 2010, 37, 36. [Google Scholar] [CrossRef] [Scilit]
Figure 1. Three-dimensional illustration of the interconnect structure parameters. W: Conductor width, S: spacing, T: thickness, H: dielectric height. Variations in parameter λ scale the width W, directly affecting the electrical characteristics.
Figure 1. Three-dimensional illustration of the interconnect structure parameters. W: Conductor width, S: spacing, T: thickness, H: dielectric height. Variations in parameter λ scale the width W, directly affecting the electrical characteristics.
Electronics 15 00640 g001
Figure 2. Impact of geometric variation on the RC circuit model. Left: Nominal case ( w 0 ) with resistance R = 1 / w 0 and capacitance C = w 0 . Right: Parametric case ( w = λ · w 0 ), resulting in the affine formulations G ( λ ) and C ( λ ) .
Figure 2. Impact of geometric variation on the RC circuit model. Left: Nominal case ( w 0 ) with resistance R = 1 / w 0 and capacitance C = w 0 . Right: Parametric case ( w = λ · w 0 ), resulting in the affine formulations G ( λ ) and C ( λ ) .
Electronics 15 00640 g002
Figure 3. Comparison of ROM transfer functions obtained by EKS-PMOR, AEKS-PMOR, and MM-PMOR for ibmpg1 ports (7,7) in the interval [ 10 0 , 10 16 ] .
Figure 3. Comparison of ROM transfer functions obtained by EKS-PMOR, AEKS-PMOR, and MM-PMOR for ibmpg1 ports (7,7) in the interval [ 10 0 , 10 16 ] .
Electronics 15 00640 g003
Figure 4. (Top) Comparison of ROM transfer functions obtained by EKS-PMOR, AEKS-PMOR, and MM-PMOR for ibmpg3 ports (16,16) in the interval [ 10 0 , 10 12 ] . (Bottom) Comparison of absolute error magnitudes for ROMs generated by EKS-PMOR, Adaptive AEKS-PMOR, and MM-PMOR for the ibmpg3 benchmark (port 16,16) within the frequency band [ 10 0 , 10 12 ] .
Figure 4. (Top) Comparison of ROM transfer functions obtained by EKS-PMOR, AEKS-PMOR, and MM-PMOR for ibmpg3 ports (16,16) in the interval [ 10 0 , 10 12 ] . (Bottom) Comparison of absolute error magnitudes for ROMs generated by EKS-PMOR, Adaptive AEKS-PMOR, and MM-PMOR for the ibmpg3 benchmark (port 16,16) within the frequency band [ 10 0 , 10 12 ] .
Electronics 15 00640 g004aElectronics 15 00640 g004b
Figure 5. (Top) Comparison of ROM transfer functions obtained by EKS-PMOR, AEKS-PMOR, and MM-PMOR for ibmpg4 ports (47,47) in the interval [ 10 0 , 10 12 ] . (Bottom) Comparison of absolute error magnitudes for ROMs generated by EKS-PMOR, Adaptive AEKS-PMOR, and MM-PMOR for the ibmpg4 benchmark (port 47,47) within the frequency band [ 10 0 , 10 12 ] .
Figure 5. (Top) Comparison of ROM transfer functions obtained by EKS-PMOR, AEKS-PMOR, and MM-PMOR for ibmpg4 ports (47,47) in the interval [ 10 0 , 10 12 ] . (Bottom) Comparison of absolute error magnitudes for ROMs generated by EKS-PMOR, Adaptive AEKS-PMOR, and MM-PMOR for the ibmpg4 benchmark (port 47,47) within the frequency band [ 10 0 , 10 12 ] .
Electronics 15 00640 g005
Figure 6. Comparison of the transient response for the ibmpg1 benchmark for: (a) λ = 0.2 ; (b) λ = 0.6 ; (c) λ = 1 ; and (d) λ = 1.4 . The output is monitored at port (1,1), while the network is excited by sinusoidal current sources at a selected subset of 10 input ports to emulate a realistic switching activity scenario. The proposed AEKS-PMOR method is compared against EKS-PMOR, MM-PMOR, and the original system, for various parameter values spanning the range λ [ 0.2 , 1.4 ] .
Figure 6. Comparison of the transient response for the ibmpg1 benchmark for: (a) λ = 0.2 ; (b) λ = 0.6 ; (c) λ = 1 ; and (d) λ = 1.4 . The output is monitored at port (1,1), while the network is excited by sinusoidal current sources at a selected subset of 10 input ports to emulate a realistic switching activity scenario. The proposed AEKS-PMOR method is compared against EKS-PMOR, MM-PMOR, and the original system, for various parameter values spanning the range λ [ 0.2 , 1.4 ] .
Electronics 15 00640 g006
Table 1. Reduction results of MM-PMOR, EKS-PMOR, and AEKS-PMOR for the industrial IBM power grid benchmarks.
Table 1. Reduction results of MM-PMOR, EKS-PMOR, and AEKS-PMOR for the industrial IBM power grid benchmarks.
NameDimension#PortsMetal
Layers
ResistorsROM
Order
MM-PMOREKS-PMORAEKS-PMOR
Max
Error
Runtime
(s)
Max
Error
Runtime
(s)
Max
Error
Runtime
(s)
ibmpg144,946600230,02712000.0290.2320.0130.2430.0210.041
ibmpg2127,5685005208,32520000.2181.2140.1291.2850.0730.254
ibmpg3852,53980051,401,57216000.22619.5120.14518.9760.1142.578
ibmpg4954,54560061,560,64524000.22216.8710.03318.0060.0964.448
ibmpg51,618,39760031,076,84812000.23715.9880.05717.1830.0893.003
ibmpg62,506,733100031,649,00260000.14818.7620.12420.9810.1364.721
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

Share and Cite

MDPI and ACS Style

Chatzigeorgiou, C.; Stoikos, P.; Floros, G.; Evmorfopoulos, N.; Stamoulis, G. Parametric Model Order Reduction for Large-Scale Circuit Models Using Extended and Asymmetric Extended Krylov Subspace. Electronics 2026, 15, 640. https://doi.org/10.3390/electronics15030640

AMA Style

Chatzigeorgiou C, Stoikos P, Floros G, Evmorfopoulos N, Stamoulis G. Parametric Model Order Reduction for Large-Scale Circuit Models Using Extended and Asymmetric Extended Krylov Subspace. Electronics. 2026; 15(3):640. https://doi.org/10.3390/electronics15030640

Chicago/Turabian Style

Chatzigeorgiou, Chrysostomos, Pavlos Stoikos, George Floros, Nestor Evmorfopoulos, and George Stamoulis. 2026. "Parametric Model Order Reduction for Large-Scale Circuit Models Using Extended and Asymmetric Extended Krylov Subspace" Electronics 15, no. 3: 640. https://doi.org/10.3390/electronics15030640

APA Style

Chatzigeorgiou, C., Stoikos, P., Floros, G., Evmorfopoulos, N., & Stamoulis, G. (2026). Parametric Model Order Reduction for Large-Scale Circuit Models Using Extended and Asymmetric Extended Krylov Subspace. Electronics, 15(3), 640. https://doi.org/10.3390/electronics15030640

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop