Search Results (41)

The growing demand for energy-efficient memory systems in artificial intelligence (AI) accelerators has intensified research into novel device technologies and computing-in-memory (CIM) architectures. While conventional binary SRAM architectures using CMOS and FinFET devices have been widely explored, ternary-based designs offer potential benefits in terms of storage density and computational efficiency. This work presents a low-power analysis of a sense-amplifier embedded (SE) 9-transistor (9T) ternary SRAM architecture implemented using Carbon Nanotube Field-Effect Transistors (CNFETs) and Gate-All-Around Field-Effect Transistors (GAAFETs). The comparative results show a substantial reduction in total power consumption—from 109.2 $\mathsf{\mu }$W in FinFET to 26.73 $\mathsf{\mu }$W in GAAFET—and an ultra-low power of only 0.0004 $\mathsf{\mu }$W in CNFET, representing a 99% reduction compared to FinFET designs. Similarly, the total delay decreases from 0.01108 ns in FinFET to 0.004 ns in GAAFET, while the CNFET design shows a modest delay of 0.017 ns. Overall, GAAFET offers the best trade-off between power and delay, whereas CNFET achieves the lowest power consumption, making it highly suitable for ultra-low-power AI applications. These findings emphasize the superior energy efficiency and scalability potential of CNFET- and GAAFET-based designs over traditional FinFETs, offering a promising pathway toward next-generation ternary CIM-enabled SRAM architectures. Furthermore, fabrication challenges related to CNFET and GAAFET technologies are discussed, providing insights into their practical feasibility for large-scale integration. Full article

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications—such as speech recognition, facial recognition, and object detection—has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to significant challenges in terms of memory access time and power consumption. Compute-in-Memory (CIM) architectures have emerged as an alternative by executing computations directly within memory arrays, thereby reducing the expensive data transfer between memory and processor units. In this work, we present a 6T SRAM-based CIM architecture implemented using FinFET technology, aiming to reduce both power consumption and access delay. We explore and simulate three different SRAM cell structures—PLNA (P-Latch N-Access), NLPA (N-Latch P-Access), and SE (Single-Ended)—to assess their suitability for CIM operations. Compared to a reference 10T XNOR-based CIM design, our results show that the proposed structures achieve an average power consumption approximately 70% lower, along with significant delay reduction, without compromising functional integrity. A comparative analysis is presented to highlight the trade-offs between the three configurations, providing insights into their potential applications in low-power AI accelerator design. Full article

In this paper, a novel Tunneling-Drift-Diffusion Field-Effect Transistor (TDDFET) based on the combination of the quantum tunneling and conventional drift-diffusion mechanisms is proposed for the design of ternary logic circuits. The working principle of the TDDFET is analyzed in detail. Then, the device is packaged as a “black box” based on the table lookup method and further embedded into the HSPICE platform using the Verilog-A language. The basic unit circuits, such as the Standard Ternary Inverter (STI), Negative Ternary Inverter (NTI), Positive Ternary Inverter (PTI), Ternary NAND gate (T-NAND), and Ternary NOR gate (T-NOR), are designed. In addition, based on the designed unit circuits, the combinational logic circuits, such as the Ternary Encoder (T-Encoder), Ternary Decoder (T-Decoder), and Ternary Half Adder (T-HA), and the sequential logic circuits, such as the Ternary D-Latch and edge-triggered Ternary D Flip-Flop (T-DFF), are built, which has important significance for the subsequent investigation of ternary logic circuits. Full article

In the present study, a polarization rotation switch (PRS)-based all-optical ternary inverter circuit and ternary clocked SR flip-flop (TCSR) are proposed and discussed. The present scheme is designed by the polarization rotation of light in a waveguide coupled with a micro-ring resonator (MRR). The proposed scheme uses linear polarization-encoded light. Here, the ternary (radix = 3) logical states are expressed by the different polarized light. PRS-MRR explores the polarization-encoded methodology, which depends on polarization conversion from one state to another. All-optical ultrafast switching technology is employed to design the ternary NAND gate. We develop the ternary clocked SR flip-flop by employing the NAND gate; it produces a greater number of possible outputs as compared to the binary logic clocked SR flip-flop circuit. The performance of the proposed design is measured by the Jones parameter and Stokes parameter. The results of the polarization rotation-based ternary inverter and clocked SR flip-flop are realized using a pump–probe structure in the MRR. The numerical simulation results are confirmed by the well-known Jones vector (azimuth angle and ellipticity angle) and Stokes parameter (S₁, S₂, S₃) using Ansys Lumerical Interconnect simulation software. Full article

For data-intensive applications like edge AI and image processing, we present a new reconfigurable 8T SRAM-based in-memory computing (IMC) macro designed for high-performance and energy-efficient operation. This architecture mitigates von Neumann limitations through numerous major breakthroughs. We built a new architecture with an adjustable capacitance array to substantially increase the multiply-and-accumulate (MAC) engine’s accuracy. It achieves 10–20 TOPS/W and >95% accuracy for 4–10-bit operations and is robust across PVT changes. By supporting binary and ternary neural networks (BNN/TNN) with XNOR-and-accumulate logic, a dual-mode inference engine further expands capabilities. With sub-5 ns mode switching, it can achieve up to 30 TOPS/W efficiency and >97% accuracy. In-memory Hamming error correction is implemented directly using integrated XOR circuitry. This technique eliminates off-chip ECC with >99% error correction and >98% MAC accuracy. Machine learning-aided co-optimization ensures sense amplifier dependability. To ensure CMOS compatibility, the macro may perform Boolean logic operations using normal 8T SRAM cells. Comparative circuit-level simulations show a 31.54% energy efficiency boost and a 74.81% delay reduction over other SRAM-based IMC solutions. These improvements make our macro ideal for real-time AI acceleration, cryptography, and next-generation edge computing, enabling advanced compute-in-memory systems. Full article

To enhance the safety of lithium ternary battery cases in new energy vehicles, this study designed a temperature monitoring and fault warning system based on NiCr/NiSi thin-film thermocouples. The system integrates six modules—sensor, amplifier, data acquisition, microprocessor (using the KPCA nonlinear dimensionality reduction algorithm), communication and monitoring, and alarm control—to monitor temperature, voltage, and humidity changes in real time. Multi-level warning thresholds are established (e.g., Level 1: initial temperature 35–55 °C rising to 42–65 °C after 10 min; initial voltage 400–425 V dropping to 398–375 V after 10 min). Experimental results demonstrate that the NiCr/NiSi thermocouple exhibits high sensitivity (average Seebeck coefficient: 41.42 μV/°C) and low repeatability error (1.04%), with a dense and uniform surface structure (roughness: 3.2–5.75 nm). The warning logic, triggered in four levels based on dynamic temperature and voltage changes, achieves an 80% accuracy rate and a low false/missed alarm rate of 4%. Long-term operation tests show stable monitoring deviations (±0.2 °C for temperature and ±0.02 V for voltage over 24 h). The system also adapts to varying humidity environments, with peak sensitivity (41.3 μV/°C) at 60% RH. This research provides a highly reliable solution for battery safety management in new energy vehicles. Full article

Natural language spatial relations are often ambiguous and polysemic. They are also pluralistic and subjective in nature. Their descriptive methods are crucial but difficult in cartography, geographic information science, and map generalization. “Between” is a context-concerned spatial concept which is widely used to describe the arrangement of spatial objects. It involves the spatial distribution of at least three spatial objects and describes a scenario in which one (or more) object(s) is surrounded by objects on both sides. Existing models based on RCC and the n-intersection model are mainly used to describe binary spatial logic and are inadequate in describing the “between” ternary relation effectively. At present, although existing models can describe and reason about such ternary spatial relations, their limitations still exist. The description capability of ternary spatial relations is unspecific and polysemic, and certain results are inconsistent with spatial cognition and perception and application requirements. Therefore, this paper proposes a 4 Sides Intersection Model (4SIM) to express the spatial relation among ternary buildings in detail. Theoretically, 4SIM can effectively describe 45 spatial relations among ternary objects through the topological distances among the four boundaries of the region formed by the intermediate object and the two adjacent objects. The 4SIM has been demonstrated to offer a superior degree of accuracy in the depiction of spatial relations in comparison to the extant RIM method, thus providing new possibilities for map generalization. Full article

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power–Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs. Full article

This study investigates the phase equilibria of the Al-Mo-Hf ternary system at 400 °C and 600 °C using X-ray diffraction (XRD) and electron probe microanalysis (EPMA/WDS) techniques. Seven three-phase and five two-phase regions were identified at 400 °C, while eight three-phase and four two-phase regions were identified at 600 °C. Despite variations in the solid solubility ranges of certain compounds, the distribution of phase zones in the isothermal cross-section remained consistent at both temperatures. Using the experimental results and logical deductions, isothermal cross-sections were constructed for the Al-Mo-Hf ternary system at 600 °C and 400 °C. Full article

In this paper, a novel transistor based on a hybrid conduction mechanism of band-to-band tunneling and drift-diffusion is proposed and investigated with the aid of TCAD tools. Besides the on and off states, the proposed device presents an additional intermediate state between the on and off states. Based on the tri-state behavior of the proposed TDFET (tunneling and drift-diffusion field-effect transistor), a ternary inverter is designed and its operation principle is studied in detail. It was found that this device achieves ternary logic with only two components, and its structure is simple. In addition, the influence of the supply voltage and the key device parameters are also investigated. Full article

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied. Full article

The positive effect of decarbonizing the transport sector by using bio-based fuels is high. Currently, biodiesel and ethanol are the two biofuels that are blended with fossil fuels. Another technology, namely, hydroprocessing, is also gaining momentum for producing biofuels. Hydrotreated vegetable oil (HVO) produced using this process is a potential drop-in fuel due to its improved physiochemical properties. This study aimed to reduce the fossil diesel content by blending 20% and 30% HVO and 5%, 10% and 15% waste cooking oil biodiesel on a volume basis. The blends were used to conduct a thorough performance examination of a single-cylinder compression ignition engine. The thermal efficiency of the engine was enhanced by the addition of biodiesel to the blend. The efficiency increased as the proportion of biodiesel in the mix increased, although it was still less efficient than diesel. The maximum improvement in thermal efficiency of 4.35% was observed with 20% blending of HVO and 15% blending of biodiesel compared with 20% blending of HVO and diesel. However, the HC (decrease of 30%), CO (decrease of 23.5%) and smoke (decrease of 21.1%) emissions were observed to be the lowest with 30% blending of HVO and 15% blending of biodiesel. A fuzzy-logic-based Taguchi method and Grey’s method were then applied to find the best blend of HVO, biodiesel and diesel. The combination of the two methods made it easier to carry out multi-objective optimization. The brake thermal efficiency (BTE), smoke and NO emissions were selected as the output parameters to optimize the HVO and biodiesel blend. The optimization study showed that 30% blending of HVO and 15% blending of biodiesel was the best blend, which was authenticated using the confirmation experiment. Full article

This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme. Full article

The study aimed to determine groundwater’s suitability for irrigation and cattle rearing in Kuwait. In this regard, groundwater samples were collected from Umm Al Aish (UA) and adjoining Rawdhatain (RA) water wellfields to develop groundwater suitability maps for irrigation purposes using the fuzzy logic technique in ArcGIS. RA was dominated by Na-Cl, Na-Ca, and Ca-SO₄ water types, whereas UA was dominated by the Ca-Mg water type. Due to the influence of the temperature and pCO₂, the carbonates were inferred to be more susceptible to precipitation in the soil than the sulfates. The ternary plots for both regions revealed that the samples’ suitability ranged from good to unsuitable. Spatial maps of nine significant parameters governing the irrigation suitability of water were mapped and integrated using the fuzzy membership values for both regions. The final suitability map derived by overlaying all the considered parameters indicated that 8% of the RA region was categorized as excellent, while UA showed only 5%. Samples situated in the study areas showed an excellent to very satisfactory range for livestock consumption. Developing a monitoring system along with innovative water resource management systems is essential in maintaining the fertility of the soil and existing groundwater reserves. Full article

This research article presents a modified novel crisscross augmented ladder (CCAL) structured multilevel inverter (MLI). MLIs can be operated in symmetric and asymmetric binary and ternary voltage ratios. The modified structure comprises a generalized unit (CCAL) and an extendable structure; this structure can be extended to generate more stair case waveform. The foremost benefit of this modified structure is to curb the conduction path of active switches. The utilized structure uses only four active conduction paths in all modes. However, an MLI has complexity, such as a higher number of switches and bulky controlling driver circuits which need superior controls. This article suggests a prominent solution for the above issues. The subtle CCAL is a governed multicarrier pulse width modulation scheme with the savvy fuzzy logic controller and, therefore, added benefits, such as lower switch stress, lower switching loss, and lower dv/dt stress. Hitherto, many topologies are emerging to curb the component count reduction structure; among them it is an attempt to curtail the active conduction path. The working capability of the presented system is substantiated with a simulation study carried out in MATLAB R2017a and viability hardware (Xilinx FPGA) proof of concept to validate the effectiveness. Full article