Symmetric and Asymmetric Crisscross Augmented Ladder Multilevel Inverter with Fuzzy Logic Controller Optimization

Abstract

This research article presents a modified novel crisscross augmented ladder (CCAL) structured multilevel inverter (MLI). MLIs can be operated in symmetric and asymmetric binary and ternary voltage ratios. The modified structure comprises a generalized unit (CCAL) and an extendable structure; this structure can be extended to generate more stair case waveform. The foremost benefit of this modified structure is to curb the conduction path of active switches. The utilized structure uses only four active conduction paths in all modes. However, an MLI has complexity, such as a higher number of switches and bulky controlling driver circuits which need superior controls. This article suggests a prominent solution for the above issues. The subtle CCAL is a governed multicarrier pulse width modulation scheme with the savvy fuzzy logic controller and, therefore, added benefits, such as lower switch stress, lower switching loss, and lower dv/dt stress. Hitherto, many topologies are emerging to curb the component count reduction structure; among them it is an attempt to curtail the active conduction path. The working capability of the presented system is substantiated with a simulation study carried out in MATLAB R2017a and viability hardware (Xilinx FPGA) proof of concept to validate the effectiveness.

1. Introduction

Multilevel inverters have been the prevailing topologies in industrial applications for the last four decades, with much research still on going. In recent years, the demand for multi-level inverters has grown substantially in high-voltage and high-power applications such as industrial drives, e-vehicles, renewable energy conversion systems, UPS systems etc. [1]. Archetypally, the complexity of the circuit increases, which leads to an increase in the step levels. The common mode voltage elimination technique is reported to have a lower switch count, as presented in [2]. Cascading the 1-phase sub multilevel converter module with a full-bridge produces 49 level output with a reduced switch count, a smaller number of separate dc sources SDC’s, and a reduction in converter cost, and it occupies a smaller area [3]. Among many topologies, cascading the diode clamped inverter and low voltage conventional inverter can generate 19 levels with a lower number of switches, which assures a good quality output with low THD [4]. Further, a new innovative topology to cater to the bi-directional power flow is carried out with a series of parallel switched multi-level dc link topology employed with sub harmonic PWM technique, which has good sinusoidal output [5]. Besides the common MLIs, the new hybrid symmetric and asymmetric topologies, which handle high power with reduced switch count, were proposed in [6,7]. The injection of third harmonics to cascaded H bridge multilevel inverter CHBMLI reduces 75% of dc link capacitance, and is the effective method of implementation without any excess components [8,9]. To overcome the limitations of the traditional MLI, the cross switched MLI using the switched capacitors with symmetric and asymmetric fashion reduces the TSV and stress on the power switches. This SCMLI generates 37 level output and is suitable for drive utilities, PV based pumping system, and in UPS system [10,11]. The new variant of the MLI topology based on the crisscross technique in the cascaded semi half bridge aims to produce a higher voltage level with reduced standing voltage. This arrangement has a reduced switch count with 21 level output [12] DSTATCOM based on CSMLI, and is presented with an effective voltage balancing control scheme which reduces the harmonics and is suitable for this application [13]. Low total standing voltage TSV on switches can be lengthy and increase the number of levels [14]. Furthermore, peak inverse voltage PIV is lower, with a reduction in voltage drop and power loss [15]. New innovative topologies, with the transformer less distribution static synchronous compensator three dissimilar modules, have been suggested for MLIs: stipulation based sources insertion topology; level count increasing topology; and inter-linking H-bridge topology, along with SDC’s yields 15 levels with component waning [16]. Cross-switched multilevel inverter topology does not uses high voltage switches and achieves the lowest standing voltage [17]. CHBMLI with FLC and PI controller effectively reduces the THD by employing a level shifting phase disposition pulse width modulation LS-PD-PWM technique, generating 5 and 9 levels [18]. A new E type module for an asymmetrical MLI produces 13 levels with 10 switches, which can have low voltage stress employed with selective harmonic elimination pulse width modulation SHEPWM, achieves high quality output [19]. A level dependent sources concoction multilevel inverter (LDSCMLI) can also utilize fewer switches with minimal common mode voltage. Low EMI with the capability to medium/high voltage from low voltage sources is presented in [20]. A blend of single-phase T-Type inverter and an H-Bridge module with sub switches has less TSV, less THD, utilizes fewer power switches, and can produce17 levels [21]. A blend of a single-phase T-Type inverter and an H-Bridge module form an MLI structure formed with sub switches [22]. A new MLI structure, with lower voltage rating components is used to overcome the complexity in conventional multilevel inverter [23,24]. A new produce of MLI with lower blocking voltage and higher number voltage level is proposed with SHE technique [25]. A novel multilevel inverter with fewer switches is developed with a modification of conventional diode clamped inverter for industrial applications [26]. A single-phase power factor corrector (PFC) is employed with a fuzzy logic controller to overcome cost effect [27].

In this article, a novel MLI topology adopted with multicarrier pulse width modulation technique and FLC controller is presented and compared. The proposed topology is extendable and enabled to increase the levels. This paper is organized as follows: Section 2 demonstrates the planned topology with its generalized structure along with the operating modules. The modulation and control strategy explaining the operation of the fuzzy logic controller is described in Section 3. Section 4 presents the simulation and experimental investigations, with the comparative study with the other topologies in both configurations. The conclusion is presented in Section 5.

2. Proposed CCAL Topology

In a multilevel inverter, the number of switching devices and separated dc voltage sources are directly proportional to the output stair case waveform; this leads to the control circuit complexity, switching losses, and bulky size of the inverter. As a prominent solution to the above problem, modified novel crisscross augmented ladder topologies are portrayed in Figure 1. The suggested topology has the benefits of a lesser conducting path, which suggests a solution for circuit complexity and is well suited to operate in both binary and ternary voltage ratios. The crisscross ladder structure is formulated with an option of flexible and extendable in row and column wise, the separated dc sources (SDC’s) are connected in the cross links. The cross linked SDCs are enabled to perform additive and subtractive with crisscross to generate the intermediate levels. The SDCs are placed in columns, while the power switches are placed in rows. The first column consists of (Vb1,1, Vb1,2, Vb1,n),the second column is connected, and in between the structure consists of a nuance voltage Vdc,1 and extendable Vdc,n. The last column consists of (Va1,1, Va1,2, Va1,n). The upper segments switches (Sa1,1, Sa1, Sa2, Sb1,1) are constant and the lower segment switches(Sa1,+n, Sb1, Sb2, Sb1,+n) are extendable. The intermediate cross section switches are (Sa3, Sa4, Sb3, Sb4). The various operation modes are shown in Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11. The clue to understanding the various operating modes, such as Figure 3 operating mode V ± 2 (Vb1,1-Vdc,1) and −(Va1,1-Vdc,1),is that the positive side conducting switches are colored in green while the negative cycle conducting switches are colored in brown, the cross connecting switches are colored in red and blue, and the pink colored areas in the row and column can be an expandable portion, as shown in schematic diagram 1.

In a similar way, all the other operating modes work as shown in Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11. The suggested skeleton works in both symmetric and asymmetric voltage ratio, and is capable of producing various stair case voltage. The topology is undergone with symmetric voltage ratio (1:1:1:1), keeping all SDCs the same (Va1,1, Va1,2, Vdc1, Vb1,1 = 75 Volts), which results ((2 × n) + 1), i.e., 9 levels. The asymmetric voltage ratio with binary values (1:2:2:2) (Va1,1 = 43 Volts, Va1,2, Vdc1, Vb1,1 = 86 Volts) produces ((4 × n) − 1), i.e., 15 levels, with ternary voltage ratio (1:3:3:3); (Va1,1 = 30 Volts, Va1,2, Vdc1, Vb1,1 = 90 Volts) produces ((6 × n) − 3), i.e., 21 levels. The switching pattern for the 21 level is tabulated in

Table 1. CCAL switching pattern for 21 level with ternary voltage ratio (1:3:3:3).

SDCs	Conducting Switches	‘m’ Level		Conducting Switches	SDCs
Va1,1 + Va1,2 + Vb1,1 + Vdc1	Sb1, Sa1,1, Sb1,2, Sa2	+10	−10	Sa1, Sa1,3, Sb1,1, Sb2	−(Va1,1 + Va1,2 + Vb1,1 + Vdc,1)
Va1,1 + Va1,2 + Vb1,1	Sb1, Sa1,1, Sb1,2, Sb4	+9	−9	Sa3, Sa1,3, Sb1,1, Sb2	−(Va1,1 + Va1,2 + Vb1,1)
Va1,1 + Va1,2 + Vb1,1 − Vdc,1	Sb4, Sa1,1, Sb1,2, Sb3	+8	−8	Sa4, Sa1,3, Sb1,1, Sa3	−(Va1,1 + Va1,2 + Vb1,1 − Vdc,1)
Va1,1 + Va1,2 + Vdc,1	Sb1, Sa1,1, Sb1,1, Sa2	+7	−7	Sa1, Sa1,3, Sb1,2, Sb2	−(Va1,1 + Va1,2 + Vdc,1)
Va1,1 + Va1,2	Sb1, Sa1,1, Sb1,2, Sb2	+6	−6	Sa1, Sb1,1, Sa1,3, Sa2	−(Va1,1 + Va1,2)
Va1,2 + Vb1,1 − Vdc,1	Sb4, Sa1,2, Sb1,2, Sb3	+5	−5	Sb1,1, Sa4, Sb1, Sa1,2	−(Va1,2 + Vb1,1 − Vdc,1)
Vb1,1 + Vdc,1	Sb1, Sa1,3, Sb1,2, Sa2	+4	−4	Sb2, Sa1,1, Sb1,1, Sa1	−(Vb1,1 + Vdc,1)
Vb1,1	Sa2, Sa1,1, Sb1,2, Sa1	+3	−3	Sb2, Sb1,1, Sa1,3, Sb1	−Vb1,1
Vb1,1 − Vdc,1	Sb4, Sa1,1, Sb1,2, Sa1	+2	−2	Sa3, Sa1,2, Sb1,1, Sa2	−(Va1,1-Vdc,1)
Vdc,1	Sb1, Sa1,3, Sb1,1, Sa2	+1	−1	Sa1, Sa1,1, Sb1,2, Sb2	−Vdc,1
	Sa1, Sa1,1, Sb1,1, Sa2	0		Sa1, Sa1,1, Sb1,1, Sa2

.

Table 2. Comparison between the CCAL MLI and other prevailing topologies “m” stair case level.

MLI Structure	Cascaded H Bridge MLI Structure	Diode Clamped MLI Structure	Capacitor Clamped MLI Structure	Proposed Crisscross MLI Structure
Active power Switches	2(m − 1)	2(m − 1)	2(m − 1)	(m + 17)/2
Passing diodes		-
Coupling diodes		2(m − 3)
Voltage splitting capacitors		(m − 1)/2	(m − 1)/2
Coupling capacitors			(2m − 6)/2
Number of sources	(m − 1)/2	1	1	(m − 1)/2

compares the number of devices which are required for the proposed and other topologies; it is evident that the proposed topologies use a lower number of devices in all conduction paths.

3. Modulation and Control Strategy

The multicarrier pulse width method (MCPWM) and fuzzy logic controller are used for the proposed topology, with a simple switching control algorithm technique. The control of complex nonlinear systems with knowledge based fuzzy logic controller is adopted here to reduce the total harmonic distortion in the output stair case waveform. FLC uses common mode harmonic approach strategy, focusing the corrections of deviation in active conduction path in the circuit. Three different voltage magnitude robust algorithms are suggested to demonstrate the feasibility of the proposed topology. The steps for the FLC interfacing diagram is shown in Figure 12. Seven fuzzy subsets are used to assign the membership function values to the linguistic variables: negative big (nb), negative medium (nm), negative small (ns), zero (zr), positive small (ps), positive medium (pm), and positive big (pb). The input variables are chosen to be variable e and ∆e, where e represents the error and ∆e is the change in error. The reference signal for the PWM generator is the output variable. For each of these processes, triangular membership functions have been chosen.

Table 3. Fuzzy associate memory for the proposed system.

e	∆e
	nb	nm	ns	zr	ps	pm	pb
nb	nb	nb	nb	nm	nm	ns	zr
nm	nb	nb	nm	nm	ns	zr	ps
ns	nb	nm	nm	ns	zr	ps	pm
zr	nm	nm	ns	zr	ps	pm	pm
ps	nm	ns	zr	ps	pm	pm	pb
pm	ns	zr	ps	pm	pm	pb	pb
pb	zr	ps	pm	pm	pb	pb	pb

provides fuzzy associative memory for the suggested system.

Table 4. Voltage magnitude algorithm expressing “m” as a function of “k”.

FLC Algorithm	Voltage Source Magnitude	Vmax	‘m’
Algorithm 1	${\mathrm{V}}_{1,\mathrm{o}}={\mathrm{V}}_{1,1}={\mathrm{V}}_{1,2}={\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\mathrm{j},0}={\mathrm{V}}_{\mathrm{j},1}={\mathrm{V}}_{\mathrm{j},2}=6^{k-1}{\mathrm{V}}_{\mathrm{dc}}$ j = 2, 3, …, k	$\left(3+3{\displaystyle \sum _{j=2}^k{6}^{j-1}}\right)\mathrm{Vdc}$	$2\left(3+3{\displaystyle \sum _{j=2}^k{6}^{j-1}}\right)+1$
Algorithm 2	${\mathrm{V}}_{1,\mathrm{o}}={\mathrm{V}}_{1,1}={\mathrm{V}}_{1,2}={\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\mathrm{j},0}={\mathrm{V}}_{\mathrm{j},1}={\mathrm{V}}_{\mathrm{j},2}=7^{k-1}{\mathrm{V}}_{\mathrm{dc}}$ j = 2, 3, …, k	$\left(3+3{\displaystyle \sum _{j=2}^k{7}^{j-1}}\right)\mathrm{Vdc}$	$2\left(3+3{\displaystyle \sum _{j=2}^k{7}^{j-1}}\right)+1$
Algorithm 3	${\mathrm{V}}_{1,\mathrm{o}}={\mathrm{V}}_{1,1}={\mathrm{V}}_{1,2}=7^{k-1}{\mathrm{V}}_{\mathrm{dc}}$ ${\mathrm{V}}_{\mathrm{j},0}={\mathrm{V}}_{\mathrm{j},1}={\mathrm{V}}_{\mathrm{j},2}=2\times 7^{k-1}{\mathrm{V}}_{\mathrm{dc}}$ j = 2, 3, …, k	$\left(5+5{\displaystyle \sum _{j=2}^k{7}^{j-1}}\right)\mathrm{Vdc}$	$2\left(5+5{\displaystyle \sum _{j=2}^k{7}^{j-1}}\right)+1$

explores the voltage magnitude of the proposed topology, expressing “m” as a function of “k”.

The FLC starts with the fuzzification, fuzzy inference and defuzzification. Initially the input parameter values are applied to fuzzification, the result obtained from the fuzzy vectors as membership functions, such as error, change of error, and output, are shown in Figure 13, Figure 14 and Figure 15. The fuzzy structures are analyzed with the help of 3D figure with respect to error, and change in error, and output, as shown in Figure 16, and the fuzzy rule is shown in Figure 17.

4. Simulation and Experimental Investigations

This section presents the simulation study, followed by experimental investigations which are clearly presented to validate the proposed CCAL multilevel inverter. Matlab R2017a is used for the simulation tool, and hardware proof of concept is implemented on Xilinx Spartan XC3SD1800A-FG676-4 Spartan 3A flat form. The proposed CCAL multilevel inverter utilizes four voltage sources and thirteen switches, although only four switches will be conducting in all modes of operation. This is the original contribution of research. A clear worth full comparison is made, with MCPWM scheme and FL controller scheme presented in Table 4 and

Table 5. Simulated result comparison with and without fuzzy logic controller.

Operating Mode		Simulated Result					Voltage Levels
		Voltage	Current	Fundamental RMS	Voltage THD	Current THD
Symmetric voltage ratio (1:1:1:1)	Without FLC	295.7	3.14	209.09	12.85%	3.45%	9
	With FLC	298.5	2.98	211.07	9.28%	3.15%
Asymmetric voltage ratio Binary (1:2:2:2)	Without FLC	296.4	2.94	209.58	8.34%	3.03%	15
	With FLC	298.5	2.98	211.07	7.14%	2.58%
Asymmetric voltage ratio Ternary (1:3:3:3)	Without FLC	297.7	3.04	210.05	5.85%	3.35%	21
	With FLC	299.5	2.86	211.77	3.28%	2.35%

. The simulation parameters for symmetric voltage ratio of 1:1:1:1 are as follows: keeping all SDCs the same, Va1,1, Va1,2, Vdc,1 and Vb1,1 = 75 Volts, with load resistance of R = 180 Ω and L = 120 mH, and switching frequency of 2 kHz, results in ((2 × n) + 1), i.e., 9 level. The simulated result is presented in Figure 18, with total harmonic distortion and laboratory proof of concept presented in Figure 19. The system undergoes asymmetric voltage ratio with binary values 1:2:2:2,Va1,1 = 43 Volts, Va1,2, Vdc,1, Vb1,1 = 86 Volts produces ((4 × n) − 1), 15 levels. The simulated result is presented in Figure 20, with total harmonic distortion and laboratory proof of concept presented in Figure 21. When the system undergoes ternary voltage ratio 1:3:3:3, Va1,1 = 30 Volts, Va1,2, Vdc,1, Vb1,1 = 90 Volts produces ((6 × n) − 3), 21 levels. The simulated result is presented in Figure 22, with total harmonic distortion and laboratory proof of concept presented in Figure 23. It is evident that the presented topology passes a lower number of conduction paths, compared in

Table 6. Hardware result comparison with and without fuzzy logic controller.

Operating Mode		Hardware Result					Voltage Levels
		Voltage	Current	Fundamental RMS	Voltage THD	Current THD
Symmetric voltage ratio (1:1:1:1)	Without FLC	284.2	3.14	200.95	14.38%	3.05%	9
	With FLC	292.5	2.98	206.92	12.58%	2.95%
Asymmetric voltage ratio Binary (1:2:2:2)	Without FLC	289.3	2.94	204.59	9.64%	3.13%	15
	With FLC	294.5	2.98	208.24	8.14%	3.08%
Asymmetric voltage ratio Ternary (1:3:3:3)	Without FLC	291.7	3.04	206.26	5.95%	3.05%	21
	With FLC	296.5	2.86	209.65	3.44%	2.25%

.

Table 5 shows the simulation results for the symmetric voltage ratio 1:1:1:1 keeping all the SDCs same as 75 V, secondly the asymmetric voltage ratio with binary ration of 1:2:2:2 as first SDCs 43 V and other SDCs as 86 V, and thirdly with ternary voltage ration 1:3:3:3 as first SDC 30 V and other SDCs 90 V. A clear comparison is made with and without fuzzy logic controller. The next Table 6 is the hardware result for the same voltage ratio.

Table 7. Comparison of the conduction path in the prevailing multilevel inverter topology and the proposed CCAL multilevel inverter.

Voltage Levels	Cascaded H Bridge MLI	Diode Clamped MLI	Flying Capacitor MLI	CHB-MLDCLI	DC- MLDCLI	CC- MLDCLI	Proposed CCAL MLI
9	8	8	8	6	6	6	4
15	14	14	14	9	9	9	4
21	20	20	20	12	12	12	4

compares the conduction path for the proposed and prevailing topologies.

In this work, the proposed MLI has been suggested, with a view to decreasing the number of power components and conduction path when creating different staircase waveform. The proposed MLI has been tested in both symmetric/asymmetric modes, has been constituted for the CCAL MLI topology, and analyzed in simulation and experimental studies. The device count in CCAL MLI symmetric topology reduces, whereas the level increases during this way of operating. The requirement of a power device blocking voltage is the same as the compared CHBMLI topology, as shown in the comparison with similar topologies. The comparison in Table 7 suggests that the proposed topology uses less conduction path. The Hardware proof of concept is designed with Xilinx Spartan XC3SD1800A-FG676-4 Spartan 3A processor is portrayed in Figure 24.

5. Conclusions

A novel MLI topology is suggested (CCAL) which has the ability to work in symmetrical as well as asymmetrical modes. The presented structure has several benefits that include low switching stress, lower switching loss, and less dv/dt stress. Additionally, the planned methodology is compared with other topologies in terms of active power switches, passing diodes, coupling diodes, capacitors and a number of sources in Table 2. The reduction in THD is attained by employing the MCPWM technique with fuzzy logic controller in Table 5 and Table 6. Experimental investigations were performed to validate the results with simulation study. The result obtained was promising and fuzzy logic controller is found to be a good candidate to produce 21 levels of output, with low THD output and less conduction path, as reported in Table 7. For the three different voltage levels, only a small number of switches is utilized in the CCAL asymmetric topology without any increase in the blocking voltage. The CCAL topology with modularity in nature can be suggested for low and medium power application; ideally, it can be extended to electric vehicle applications.