Design of All-Optical Ternary Inverter and Clocked SR Flip-Flop Based on Polarization Conversion and Rotation in Micro-Ring Resonator

Abstract

In the present study, a polarization rotation switch (PRS)-based all-optical ternary inverter circuit and ternary clocked SR flip-flop (TCSR) are proposed and discussed. The present scheme is designed by the polarization rotation of light in a waveguide coupled with a micro-ring resonator (MRR). The proposed scheme uses linear polarization-encoded light. Here, the ternary (radix = 3) logical states are expressed by the different polarized light. PRS-MRR explores the polarization-encoded methodology, which depends on polarization conversion from one state to another. All-optical ultrafast switching technology is employed to design the ternary NAND gate. We develop the ternary clocked SR flip-flop by employing the NAND gate; it produces a greater number of possible outputs as compared to the binary logic clocked SR flip-flop circuit. The performance of the proposed design is measured by the Jones parameter and Stokes parameter. The results of the polarization rotation-based ternary inverter and clocked SR flip-flop are realized using a pump–probe structure in the MRR. The numerical simulation results are confirmed by the well-known Jones vector (azimuth angle and ellipticity angle) and Stokes parameter (S₁, S₂, S₃) using Ansys Lumerical Interconnect simulation software.

1. Introduction

The requirements for faster all-optical signal processing in an optical communication network have been increased in recent times. To fulfill these requirements, the advancement of optical communication networks shifted towards a higher bandwidth in the terahertz (THz) range. A polarization rotation-based switch can transmit data in the optical domain without using an electro-optics interface. Therefore, it is capable of achieving ultrafast switching at higher data rates. The approach has been proposed in the domain of all-optical switches and a parallel processing system [1,2]. An all-optical switch (AOS)-based conventional logic circuit can be used in the high-speed signal processing system. It can fulfill the convenient performance required due to its compact size, low power characteristic, high transmittance, and ultra-high switching speed [3,4,5]. Micro-ring resonators provide a very versatile platform for optical switching and computing, offering the advantages of ultrafast and low-power switching. The switching operation of an AOS depends on the birefringence of the material/waveguide and nonlinear refractive index change [6,7].

Many researchers have endorsed different kinds of AOSs for ultrafast operative speed using many approaches such as a micro-ring resonator (MRR), a Sagnac switch, a Mach–Zender interferometer (MZI), a terahertz optical asymmetrical demultiplexer (TOAD), an optical nonlinear material (OPNLM) and AI-based logic circuits, etc. [8,9,10,11,12,13,14]. In this study, we used a polarization-encoded light signal. The polarization-dependent phenomena in AOSs are very significant, and these can function in the “terahertz” range and require very narrow power with less circuitry [15,16].

In the last decade, the multi-valued logic (MVL) technique has been considered a potential and promising domain of research. MVL systems have some major benefits over the binary logic system, such as increased data handling capacity in the field of optical computing, increased computational processing, and reduced dynamic power dissipation. Larger numbers of logic function can be derived with MVL circuits. A large diversity of optical data can be managed in the MVL domain, which is used as a promising alternative in different practical solutions [17,18,19,20,21]. The optical MVL operation is an impressive and visionary research direction for future optical data communication [22,23,24]. But most MVL circuits constructed in the past have been complicated and faced an analogue noise dilemma. A quaternary inverter and universal quaternary inverter have been implemented by TOAD-based switches [25]. A TOAD-based switch suffers from an asymmetric switching; it could produce high crosstalk and impair the Bit Error Rate (BER). The major drawback in MZI design is that it requires a large interaction length, which leads to high insertion loss, phase instability, and large power consumption. Few other MVL circuits have been constructed using an SOA-based MZI facing phase-handling obstacles.

A performance comparison of existing all-optical MVL technologies is shown in

Table 1. Performance comparison of existing all-optical MVL technologies.

Sl. No.	References	Mechanism	Structures/No. of Switches Used	Performance Analysis	Advantages	Drawbacks
1	T. Chattopadhyay and J. N. Roy [22]	SOA-assisted Sagnac switch-based all-optical quaternary universal inverter.	2 TOAD-based switches are used for inverters.	Power, 0.2 mW; switching time, not mentioned.	High-speed, simple optical control structure.	The main drawback of SOA-based AOSs is that it has speed limitations due to the relatively slow recovery of the carrier density in the amplifier’s active region. It has some problems with temperature variations and might have trouble keeping the signals polarized.
2	A. Raja, et al. [26]	Dual SOA-based all-optical quaternary inverter and clocked SR flip-flop.	2 SOA-based switches are used for inverter. 24 SOA-based switches are used for flip-flop. Relatively complex in nature.	Power, 0.2 mW for single SOA; data rate, 333 Gbps.	High-speed, simple optical control structure.	The main drawback of SOA-based AOSs is that it has speed limitations due to the relatively slow recovery of the carrier density in the amplifier’s active region. It has some problems with temperature variations and might have trouble keeping the signals polarized.
3	T. Chattopadhyay [27]	TOAD-based ternary logic gates.	2 TOAD-based interferometric switches for ternary MIN/MAX gate.	Power not mentioned; switching time not mentioned.	Normally high operational speed and low level of switching energy.	Normally, power consumption is high, wavelength selectivity is poor, and cascadability is difficult.
4	M. P. singh [28]	Ring resonator-based ternary multiplexer and demultiplexer circuit.	3-micro-ring resonator-based ternary AND gate.	Power, 80 µW to 1.35 mW; switching time, 0.714 ps.	Ultra-compact, very high operational speed, high wavelength selectivity, low power consumption, and high integration capacity.	Fabrication-sensitive, and narrow bandwidth.

.

In the present study, we propose a polarization rotation switch (PRS)-based ternary (radix, R = 3) clocked SR flip-flop using ternary NAND logic gate. The PRS using MRR-based ternary AND/NAND logic gate has already been designed and discussed in [29].

The article is organized in five sections. The ternary logic, an all-optical switch (AOS) and MVL circuits are discussed in Part 1, and the theories of the polarization rotation-based switch (PRS), ternary NAND logic gate using the MRR are discussed in Part 2. The ternary inverter using single micro-ring resonator and T-clocked SR flip-flop are discussed in Part 3. The simulation results using Ansys Lumerical Interconnect software conforming to the described design and discussion are given in Part 4. The conclusion of this study is given in Part 5.

2. Theory of Ternary Inverter Circuit and Clocked SR Flip-Flop Circuit

The polarization rotation-based ternary inverter can be designed using single MRR and applying the ternary input via the input port of the MRR to obtain the results at the through port of MRR. A ternary clocked SR flip-flop circuit can be designed using two inputs (S, R) and four ternary NAND gates. In the binary inverter, binary states are described by 0 (low logic) and 1 (high logic) according to the amplitude of the output signal. The ternary inverter includes the logic low, logic high and one intermediate state. According to the ternary inverter circuit, a large number of logic operations can be obtained for higher radix. Recently, the ternary inverter (radix, R = 3) has been used for ultrafast communication. For radix 3, a total number of possible inverter states is 27. In this proposed design, we used three different states of the polarized light to represent the ternary states (0, 1 and 2) for the logical operations, which are given below:

(a)

0: Horizontally polarized light or HPL (•);

(b)

1: Linearly polarized light at 45° or L45P;

(c)

2: Vertically polarized light or VPL (↑).

In this study, three different logic states are used to represent the polarized light, namely the ‘Logic-0’, ‘Logic-1’, and ‘Logic-2’. The ‘Logic-0’ is used to represent the linear horizontally polarized light or HPL (•). The ‘Logic-1’ is used to represent the linearly polarized light at 45° or (L45P). The ‘Logic-2’ is used to represent the linear vertically polarized light or VPL (↑).

2.1. Modeling of MRR-Based Ternary Polarization Rotation Switch (PRS)

In this section, we designed a new method to obtain all-optical multi-valued ternary inverter using polarization rotation switching in the MRR. We investigated and evaluated the performance from the simulated result using Ansys Lumerical Interconnect software.

Ansys Lumerical Interconnect is a powerful photonic integrated circuit simulator in which time and frequency domain analysis are performed using a dynamic data flow simulator, allowing for more flexibility than using traditional discrete time or time-driven simulators [30]. Lumerical Interconnect simulation software primarily focuses on simulating and analyzing the behavior of optical interconnects, such as waveguides, optical fibers, photonic devices, etc. The circuits can be simulated in Lumerical Interconnect using component circuit blocks that describe the input–output behavior of the component.

The basic configuration of the racetrack MRR comprising double waveguide coupled structure is shown in Figure 1. At the resonance, maximum light is transmitted to the through port of the MRR due to the constructive interference. Accordingly, the resonance condition is expressed by mλ_res = 2π.R_0.n_eff, where m denotes the mode number, R₀ is the ring radius, n_eff is the effective refractive index (RI) of the ring, and λ_res is the resonance wavelength. According to the transmission curve, the through port (TP) represents the maximum transmission and the drop port (DP) represents the minimum transmittance. The pump signal of suitable power is responsible for changing the RI of the material and inducing 180° phase shift. The graph of the output transmission of this structure is shown in Figure 2.

The polarization rotation switch is used for the realization of the ternary inverter as well as the clocked SR flip-flop circuit. The ternary clocked SR flip-flop circuit is designed with the help of MRR-PRS-based ternary NAND logic gate. The flow of operation of the MRR-based PRS is shown in Figure 3. The control signal with sufficient power is used to realize all-optical switching phenomenon. If the control signal is not present, a particular polarization state is available at the TP. When the control signal with different pump power is applied from the add port, the polarization rotation occurs at λ_res. The proposed configuration of PRS using MRR, consisting of nonlinear polarization maintaining (PM) fiber and a polarization rotator (PR), rotates the light polarization to a certain angle. The input polarized light enters the ring and can enhance the nonlinear birefringence dramatically due to the accumulated phase shift and the amplified intensity at the resonance wavelength. The detailed mathematical relationship between the input and output fields in terms of Jones matrix have already been discussed in [31,32,33,34,35]. The various parameters of the MRR-like coupling coefficient, waveguide height and width, ring radius and control signal power are optimized through Ansys Lumerical Interconnect simulation tool to obtain desired polarization conversion. The optimized values of these parameters are listed in

Table 2. List of parameters used to design ternary MRR-PRS.

S. No.	Parameters	Description
I.	MRR waveguide material	GaAs
II.	Nature of coupling	Lateral coupling
III.	Coupling coefficient (k1, k2)	0.45, 0.45
IV.	Refractive index of GaAs	3.38
V.	Coupling length	3 μm
VI.	MRR radius	12 μm
VII.	Resonance wavelength	1548.42 nm
VIII.	Polarization rotation angle	60°

. In this manuscript, horizontal axis, i.e., MRR axis, is considered as the reference axis. So, polarization angle of the MRR is considered as 0°. However, the misalignment of the polarization angle of the input light in the polarization setting may cause variation in the output of the proposed model [36,37].

If the linearly vertical polarized light is fed to the input port (IP) and no control signal is fed to the add port (AP) of the optical MRR, we obtain the same polarization state, i.e., linearly vertical polarized light at λ_res at the TP output. When the control signal is applied with optimized power, the MRR-PRS converts the VPL to HPL or linear 45° polarized (L45P) light.

2.2. Ternary NAND Logic Gate Using MRR-PRS

An MRR-PRS-based ternary NAND (TNAND) gate is designed in Lumerical simulation software, which is shown in Figure 4. A ternary NAND gate is realized at the TP of the proposed model and the logic levels are shown in

Table 3. Truth table of ternary NAND gate.

Input Port (A)	Add Port (B)	“Through Port” (NAND Gate)
HPL(‘Logic-0’)	HPL(‘Logic-0’)	VPL(‘Logic-2’)
L45P (‘Logic-1’)	HPL(‘Logic-0’)	VPL(‘Logic-2’)
VPL(‘Logic-2’)	HPL(‘Logic-0’)	VPL(‘Logic-2’)
HPL(‘Logic-0’)	L45P (‘Logic-1’)	VPL(‘Logic-2’)
L45P (‘Logic-1’)	L45P (‘Logic-1’)	L45P (‘Logic-1’)
VPL(‘Logic-2’)	L45P (‘Logic-1’)	L45P (‘Logic-1’)
HPL(‘Logic-0’)	VPL(‘Logic-2’)	VPL(‘Logic-2’)
L45P (‘Logic-1’)	VPL(‘Logic-2’)	L45P (‘Logic-1’)
VPL(‘Logic-2’)	VPL(‘Logic-2’)	HPL(‘Logic-0’)

. The polarized states of the input and control signal are used to obtain the desired output by applying the suitable pump power. Here, both the inputs A (probe signal) and B (control signal) can select any one of the three possible states (‘Logic-0’, ‘Logic-1’ and ’Logic 2’). The combinations of both the signals provide adequate phase-shift required for converting the polarization states at the output. Wavelength range and bandwidth of input signal are considered as 1547–1559 nm and 1.6 THz, respectively.

For example, if input ‘A’ = L45P or (‘Logic-1’), and ‘B’ = HPL (•) or (‘Logic-0’), VPL (↑) comes out from the TP at λ_res of 1548.42 nm. The obtained results are analyzed in terms of Jones parameters and Stokes parameters. For example, simulation results for inputs A and B in terms of Jones and Stokes parameters for ‘Logic-1’ and ‘Logic-0’, respectively, are shown in Figure 5. Figure 5a shows that the ellipticity angle is 0° and the azimuth angle is 90°. Figure 5b shows that Stokes parameters are [S₁, S₂, S₃] = [−1, 0, 0] at the TP of MRR, which indicates that the TP output is VPL (‘Logic-2’). The simulation results of the different combinations are given in

Table 4. Truth table and polarization states of ternary NAND gate.

Input Port (A)	Pump Source (B)		“Through Port” Output (NAND Gate)
	Logic State	Pump Power	Azimuth Angle (E = 0°)	Output Polarization State
HPL ‘Logic-0’	HPL	240 μW	90°	VPL(‘Logic-2’)
	L45P	400 μW	90°	VPL(‘Logic-2’)
	VPL	915 μW	90°	VPL(‘Logic-2’)
L45P ‘Logic-1’	HPL	185 μW	90°	VPL(‘Logic-2’)
	L45P	10 μW	45°	L45P (‘Logic-1’)
	VPL	18 μW	45°	L45P (‘Logic-1’)
VPL ‘Logic-2’	HPL	8 μW	90°	VPL(‘Logic-2’)
	L45P	200 μW	45°	L45P (‘Logic-1’)
	VPL	380 μW	0°	HPL(‘Logic-0’)

.

3. Design of the Ternary Inverter and Clocked SR Flip-Flop Circuit

Many researchers have explained the binary coded ternary logic to implement different kinds of ternary arithmetic and logical functions. In the study, intensity-encoded light signal is also investigated to represent the different types of logic states for the implementation of Boolean logic functions, which require apparent specific intensity level of light for individual state [16,20] and the intensity-encoded signal may also be altered due to many reasons. This problem can be avoided in the polarization-based encoding and decoding method.

The binary inverter is expressed by [0 1] $\to$ [x y], which indicates the transmission of the incoming signal of state 0 (low) into an outgoing signal x and the transmission of an incoming signal of state 1 into an outgoing signal y accordingly. For multi-valued, the total numbers of possible logical operations are ${\mathrm{R}}^{{\mathrm{R}}^{\mathrm{n}}}$ for a system of radix = R, and the number of input variables is n. According to binary logic system (n = 1, R = 2), we obtain four possible numbers of inverter states [0 1] $\to$ [0 0], [0 1] $\to$ [1 0], [0 1] $\to$ [0 1] and [0 1] $\to$ [1 1], respectively. Similarly, we can explain the ternary logic inverter in ternary logic system (radix, R = 3). We can obtain the total of $3^{3^1}=$27 inverter states [0 0 0], [1 0 0], [2 0 0], [0 1 0], … and [2 2 2], which are shown in

Table 5. Truth table and polarization properties of Ternary inverter.

Input Polarization States	Control Signal	Output Polarization States (Y)
HPL	HPL	HPL
		L45P
		VPL
	L45P	HPL
		L45P
		VPL
	VPL	HPL
		L45P
		VPL
L45P	HPL	HPL
		L45P
		VPL
	L45P	HPL
		L45P
		VPL
	VPL	HPL
		L45P
		VPL
VPL	HPL	HPL
		L45P
		VPL
	L45P	HPL
		L45P
		VPL
	VPL	HPL
		L45P
		VPL

.

A polarization-encoded all-optical ternary inverter uses polarization states of the light to represent and manipulate three-logic levels (ternary logic: 0, 1, 2). The polarization inversion operation is performed using polarization-selective elements that transform the polarization state to its logical inverse.

The PRS-based ternary logic circuit is implemented using double waveguide coupled MRR in Ansys Lumerical Interconnect simulation software, which is shown in Figure 6. It consists of symmetrical couplers, i.e., k₁ = k₂ = k = 0.45, and the refractive index of the waveguide is nearly 3.38. The polarization-based all-optical switching depends on the pump power of the optical signal.

The design of clocked S-R ternary flip-flop is described by ternary NAND gate. NAND gate-based clocked S-R flip-flop is shown in Figure 7. The corresponding Interconnect simulation model is shown in Figure 8 and its truth table is shown in

Table 6. Truth table of ternary clocked SR flip-flop circuit.

Ternary Clock	Input-S	Input-R	Previous State		Next State		Remark
			Qn	$\overline{{\mathbf{Q}}_{\mathbf{n}}}$	Qn+1	$\overline{{\mathbf{Q}}_{\mathbf{n}+1}}$
‘Logic-0’ (HPL)	‘Logic-0’	‘Logic-0’	‘Logic-0’	‘Logic-2’	0	2	Unchanged
			‘Logic-2’	‘Logic-0’	2	0	Unchanged
			‘Logic-1’	‘Logic-1’	1	1	Unchanged
	‘Logic-0’	‘Logic-1’	‘Logic-0’	‘Logic-2’	0	2	Reset
			‘Logic-2’	‘Logic-0’	2	0	Set
			‘Logic-1’	‘Logic-1’	1	1	Intermediate
	‘Logic-0’	‘Logic-2’	‘Logic-0’	‘Logic-2’	0	2	Reset
			‘Logic-2’	‘Logic-0’	2	0	Set
			‘Logic-1’	‘Logic-1’	1	1	Intermediate
‘Logic-1’ (L45P)	‘Logic-1’	‘Logic-0’	‘Logic-0’	‘Logic-2’	1	2	Forbidden
			‘Logic-2’	‘Logic-0’	2	1	Forbidden
			‘Logic-1’	‘Logic-1’	1	1	Intermediate
	‘Logic-1’	‘Logic-1’	‘Logic-0’	‘Logic-2’	1	2	Forbidden
			‘Logic-2’	‘Logic-0’	2	1	Forbidden
			‘Logic-1’	‘Logic-1’	1	1	Intermediate
	‘Logic-1’	‘Logic-2’	‘Logic-0’	‘Logic-2’	1	2	Forbidden
			‘Logic-2’	‘Logic-0’	2	1	Forbidden
			‘Logic-1’	‘Logic-1’	1	1	Intermediate
‘Logic-2’ (VPL)	‘Logic-2’	‘Logic-0’	‘Logic-0’	‘Logic-2’	0	2	Reset
			‘Logic-2’	‘Logic-0’	2	0	Set
			‘Logic-1’	‘Logic-1’	1	1	Intermediate
	‘Logic-2’	‘Logic-1’	‘Logic-0’	‘Logic-2’	2	2	Forbidden
			‘Logic-2’	‘Logic-0’	2	1	Forbidden
			‘Logic-1’	‘Logic-1’	1	1	Intermediate
	‘Logic-2’	‘Logic-2’	‘Logic-0’	‘Logic-2’	2	2	Forbidden
			‘Logic-2’	‘Logic-0’	2	2	Forbidden
			‘Logic-1’	‘Logic-1’	2	2	Forbidden

.

As per the definition of the ternary inverter, output is 2, when 0 is input and vice versa. But the output remains 1, when input is 1, i.e., 1’s complement is 1. Now for the SR flip-flop, states are referred to as “Set” when ${\mathrm{Q}}_{\mathrm{n}+1}$ = 2 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ = 0 for any combination of S and R. Inversely, states are referred to as “Reset” when ${\mathrm{Q}}_{\mathrm{n}+1}$ = 0 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$= 2 for any combination of S and R. But when ${\mathrm{Q}}_{\mathrm{n}+1}$ = 1, then $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ is also 1. So ${\mathrm{Q}}_{\mathrm{n}+1}$ = 1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ = 1 is also valid output state in ternary flip-flop unlike binary flip-flops and is called ‘intermediate state’. All other output combinations are not valid as per flip-flop definition. So, these states are called ‘forbidden state’.

The signal flow graph (SFG) diagram for a particular case of Table 6 of the proposed SR flip-flop is shown in Figure 9. In the diagram, for an instant, let us consider Clock = HPL (‘Logic-0’), S = HPL (‘Logic-0’), R = L45P (‘Logic-1’) and previous output ($Q_n$) = VPL (‘Logic-2’). So, as per truth Table 6, the output, ${\mathrm{Q}}_{\mathrm{n}+1}$ = 2, then $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ = 0, i.e., ‘Set’ condition is achieved.

4. Simulation Results and Discussion

The simulation results of ternary states are analyzed by the Jones matrix, which defines azimuth angle and ellipticity angle of the polarized light. The pump signal is injected from the AP and the polarization rotation-based ternary inverter operation is observed at the TP of the MRR at the resonance wavelength of 1548.428 nm. The simulation results of the Jones matrix method are also verified by Stokes parameters. The Stokes parameters, in general, are often combined into a vector, and are discussed below:

$$\mathrm{S}=\left[\begin{array}{c}{\mathrm{S}}_0\\ {\mathrm{S}}_1\\ {\mathrm{S}}_2\\ {\mathrm{S}}_3\end{array}\right], \mathrm{where} {\mathrm{S}}_0={\left|{\mathrm{E}}_{\mathrm{H}}\right|}^2+{\left|{\mathrm{E}}_{\mathrm{V}}\right|}^2, {\mathrm{S}}_1={\left|{\mathrm{E}}_{\mathrm{H}}\right|}^2-{\left|{\mathrm{E}}_{\mathrm{V}}\right|}^2, {\mathrm{S}}_2=2\left|{\mathrm{E}}_{\mathrm{H}}\right|\left|{\mathrm{E}}_{\mathrm{V}}\right|\cos \mathsf{\varphi },$$

$${\mathrm{S}}_3=2\left|{\mathrm{E}}_{\mathrm{H}}\right|·\left|{\mathrm{E}}_{\mathrm{V}}\right|\sin \mathsf{\varphi }$$

where $\mathsf{\varphi }$ = ${\mathsf{\varphi }}_{\mathrm{x}}-{\mathsf{\varphi }}_{\mathrm{y}}$ is the phase difference between x and y components of the polarized light.

$${\mathrm{S}}_{\mathrm{H}\mathrm{P}\mathrm{L}}=\left[\begin{array}{c}\begin{array}{c}1\\ 1\end{array}\\ 0\\ 0\end{array}\right], {\mathrm{S}}_{\mathrm{L}45\mathrm{P}}=\left[\begin{array}{c}\begin{array}{c}1\\ 0\end{array}\\ 1\\ 0\end{array}\right]\mathrm{and} {\mathrm{S}}_{\mathrm{V}\mathrm{P}\mathrm{L}}=\left[\begin{array}{c}\begin{array}{c}1\\ -1\end{array}\\ 0\\ 0\end{array}\right]$$

4.1. Inverter

MVL system (radix, R = 3) is represented as non-binary logic and performs the polarization switching between the three polarization states. In the ternary logic, a particular logic state is changed to the desired states at the resonant wavelength of 1548.42 nm. The polarization rotation of the signal depends upon the nature of the polarization and the power level of the control signal. In the design of Figure 6, the light source (LS) of the ternary input ‘A’ with any one of the polarization states (HPL/L45P/VPL) is applied at the IP of the MRR. An optical control signal (B) is applied to the AP of the MRR that changes the polarization state of the output. We realized the ternary inverter at the TP of the MRR.

Case 1: When input ‘A’ = HPL (•) or Logic-0’ and control signal B = HPL (•) or ‘Logic-0”, depending on the power of the control signal, we can deduce the ternary output as follows:

(i) The azimuth angle is 0°, the ellipticity angle is 0° and the Stokes parameters are S₁ = 1, S₂ = 0, and S₃ = 0 and we get the ‘Logic-0’ (HPL) at the output when control signal is 10 µW.

(ii) The azimuth angle is 45°, the ellipticity angle is 0° and Stokes parameters are S₁ = 0, S₂ = 1, and S₃ = 0 and we get the ‘Logic-1’ (L45P) at the output when control signal is 90 µW.

(iii) The azimuth angle is 90°, the ellipticity angle is 0° and Stokes parameters are S₁ = −1, S₂ = 0, and S₃ = 0 and we get the ‘Logic-2’ (VPL) at the output when control signal is 180 µW.

The simulation results of one of the above combinations (case 1(i)) are depicted in Figure 10. The output of the ternary inverter for the above-specified combination is shown in the first row of

Table 7. Truth table of ternary Inverter with control power.

Input Port Polarization State	Add-Port Polarization State	Control Signal Power	Output		Through Port “Polarization State”
			(Az, E),	(S1, S2, S3)
Logic-0 (HPL)	Logic-0 (HPL)	10 μW	(0°, 0°)	(1, 0, 0)	Logic-0 (HPL)
		90 μW	(45°, 0°)	(−1, 0, 0)	Logic-1 (L45P)
		180 μW	(90°, 0°)	(0, 1, 0)	Logic-2 (VPL)
Logic-0 (HPL)	Logic-1 (L45P)	20 μW	(0°, 0°)	(1, 0, 0)	Logic-0 (HPL)
		950 μW	(45°, 0°)	(−1, 0, 0)	Logic-1 (L45P)
		880 μW	(90°, 0°)	(0, 1, 0)	Logic-2 (VPL)
Logic-0 (HPL)	Logic-2 (VPL)	10 μW	(0°, 0°)	(1, 0, 0)	Logic-0 (HPL)
		740 μW	(45°, 0°)	(−1, 0, 0)	Logic-1 (L45P)
		965 μW	(90°, 0°)	(0, 1, 0)	Logic-2 (VPL)
Logic-1 (L45P)	Logic-0 (HPL)	165 μW	(0°, 0°)	(1, 0, 0)	Logic-0 (HPL)
		15 μW	(45°, 0°)	(−1, 0, 0)	Logic-1 (L45P)
		922 μW	(90°, 0°)	(0, 1, 0)	Logic-2 (VPL)
Logic-1 (L45P)	Logic-1 (L45P)	10 μW	(0°, 0°)	(1, 0, 0)	Logic-0 (HPL)
		650 μW	(45°, 0°)	(−1, 0, 0)	Logic-1 (L45P)
		867 μW	(90°, 0°)	(0, 1, 0)	Logic-2 (VPL)
Logic-1 (L45P)	Logic-2 (VPL)	114 μW	(0°, 0°)	(1, 0, 0)	Logic-0 (HPL)
		990 μW	(45°, 0°)	(−1, 0, 0)	Logic-1 (L45P)
		10 μW	(90°, 0°)	(0, 1, 0)	Logic-2 (VPL)
Logic-2 (VPL)	Logic-0 (HPL)	915 μW	(0°, 0°)	(1, 0, 0)	Logic-0 (HPL)
		650 μW	(45°, 0°)	(−1, 0, 0)	Logic-1 (L45P)
		14 μW	(90°, 0°)	(0, 1, 0)	Logic-2 (VPL)
Logic-2 (VPL)	Logic-1 (L45P)	450 μW	(0°, 0°)	(1, 0, 0)	Logic-0 (HPL)
		910 μW	(45°, 0°)	(−1, 0, 0)	Logic-1 (L45P)
		10 μW	(90°, 0°)	(0, 1, 0)	Logic-2 (VPL)
Logic-2 (VPL)	Logic-2 (VPL)	480 μW	(0°, 0°)	(1, 0, 0)	Logic-0 (HPL)
		910 μW	(45°, 0°)	(−1, 0, 0)	Logic-1 (L45P)
		10 μW	(90°, 0°)	(0, 1, 0)	Logic-2 (VPL)

.

Case 2: When input A = L45P or “Logic-1” and control signal B = HPL (•) or ‘Logic-0’, depending on the power of the control signal, we can deduce the ternary output at a resonant wavelength of 1548.42 nm as follows:

(i) The azimuth angle = 0°, the ellipticity angle is 0° and the Stokes parameters are S₁ = 1, S₂ = 0, and S₃ = 0 and we get the ‘Logic-0’ (HPL) at the output when control signal is 165 µW.

(ii) The azimuth angle is 45°, the ellipticity angle is 0° and the Stokes parameters are S₁ = 0, S₂ = 1, and S₃ = 0 and we get the ‘Logic-1’ (L45P) at the output when control signal is 15 µW.

(iii) The azimuth angle is 90°, the ellipticity angle is 0° and the Stokes parameters are S₁ = −1, S₂ = 0, and S₃ = 0 and we get the VPL (↑) or ‘Logic-2’ at the output when control signal is 922 μW, which is shown in Figure 11. The output of the ternary inverter for the above-specified combination is shown in the twelfth row of Table 7.

Case 3: When input A is VPL (↑) or “Logic-2” and control signal B is also HPL (•) or ‘Logic-0’, depending on the power of the control signal, we can conclude the ternary output at the resonant wavelength of 1548.42 nm as the following:

(i) The azimuth angle is 0°, the ellipticity angle is 0° and the Stokes parameters are S₁ = 1, S₂ = 0, and S₃ = 0 and we get the ‘Logic-0’ (HPL) at the output when control signal is 915 µW.

(ii) The azimuth angle is 90°, the ellipticity angle is 0° and the Stokes parameters are S₁ = −1, S₂ = 0, and S₃ = 0 and we get the ‘Logic-2’ (VPL) at the output when control signal is 14 µW.

(iii) The azimuth angle is 45°, the ellipticity angle is 0° and the Stokes parameters are S₁ = 0, S₂ = 1, and S₃ = 0 and we get the ‘Logic-1’ (L45P) at the output when control signal is 650 µW. This combination is shown in Figure 12. The output of the ternary inverter for the above-specified combination is shown in the twelfth row of Table 7. Similarly, all the remaining possible logic combinations are mentioned in Table 7.

4.2. Clocked SR Flip-Flop Circuit

The clocked SR ternary flip-flop comprises of four identical MRRs (MRR-1, MRR-2, MRR-3 and MRR-4), as shown in Figure 7. The output TP-3 of MRR-3 represents Q_n+1 and TP-4 of MRR-4 represents $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$. It fulfills all the conditions similarly to the conventional clocked binary flip-flop. In the binary SR flip-flop, only four possible conditions occur. Like binary, all four conditions (SET, RESET, Unchanged and Forbidden) of the SR flip-flop have been taken into consideration in our proposed design along with intermediate states, as shown in Table 6. The simulation model of the proposed ternary clocked SR flip-flop circuit is shown in Figure 8. The simulation results are validated by the Jones matrix (azimuth and ellipticity angle) and Stokes parameters (S₁ S₂ S₃). According to the truth table of the ternary clocked SR flip flop, the first three rows of Table 6 show unchanged condition, when T-Clock is ‘Logic-0’ and inputs, S = 0, R = 0.

Case 1: The clock is ‘Logic-0’, input S is ‘Logic-0’ or HPL (•) and R is ‘Logic-0’ or HPL (•). According to the simulation model, the ternary clocked SR flip-flop is realized using MRR-based ternary NAND gates. The polarization rotation switching occurs at the resonant wavelength of 1548.42 nm due to the MRR-PRS property. Three different outputs are obtained for different combinations of the previous output states. When the previous outputs are Q_n = 0 and $\overline{{\mathrm{Q}}_{\mathrm{n}}}$ = 2, the next output Q_n+1 is obtained at the TP-3 of MRR-3, which receives the ‘Logic-0’ or HPL. The output $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ is obtained at the TP-4 of MRR-4, which receives the ‘Logic-2’ or VPL. The Jones parameters’ representation of Q_n+1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ is shown in Figure 13a and Figure 14a, respectively. According to Figure 13a, it is observed that both the azimuth and ellipticity angles are almost 0°, which signifies that the output is ‘Logic-0’ or HPL (•). From Figure 14a, it is observed that the azimuth angle is 90° and the ellipticity angle is almost 0°, which signifies that the output is “Logic-2 or VPL (↑).

The Stokes parameters for Q_n+1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ are illustrated in Figure 13b and Figure 14b, respectively. From Figure 13b and Figure 14b it is observed that the Stokes parameters are [S₁ = 1, S₂ = 0, S3 = 0] and [S₁ = −1, S₂ = 0, S3 = 0], respectively. It is shown that Q_n+1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ outputs are ‘Logic-0’ or HPL (•) and ‘Logic-2’ or VPL (↑), respectively. The outputs of the TP-3 and TP-4 for the above-mentioned combination are (0, 2), which implies the RESET condition. Like this case, the present state remains the same in the other two cases when S = R = ‘Logic-0’. All the three cases are shown in the first three rows of

Table 8. Truth table of ternary clocked SR flip-flop circuit with control power.

T-Clock	Input S	Input R	Control Signal Power, CS-1	Control Signal Power, CS-2	Qn	$\overline{{\mathbf{Q}}_{\mathbf{n}}}$	Qn+1	$\overline{{\mathbf{Q}}_{\mathbf{n}+1}}$	Remarks
Active State (HPL)	0	0	12 μW	160 μW	0	2	0	2	Unchanged
	0	0	75 μW	15 μW	2	0	2	0	Unchanged
	0	0	670 μW	670 μW	1	1	1	1	Unchanged
	0	1	340 μW	880 μW	0	2	0	2	Reset
	0	1	1.02 mW	1.10 mW	2	0	2	0	Set
	0	1	170 μW	170 μW	1	1	1	1	Intermediate
	0	2	85 μW	140 μW	0	2	0	2	Reset
	0	2	640 μW	1.40 mW	2	0	2	0	Set
	0	2	810 μW	320 μW	1	1	1	1	Forbidden
Active State (L45L)	1	0	1.02 mW	140 μW	0	2	1	2	Forbidden
	1	0	850 μW	955 μW	2	0	2	1	Forbidden
	1	0	170 μW	170 μW	1	1	1	1	Intermediate
	1	1	140 μW	140 μW	0	2	1	2	Forbidden
	1	1	35 μW	155 μW	2	0	2	1	Forbidden
	1	1	170 μW	270 μW	1	1	1	1	Intermediate
	1	2	385 μW	1.15 mW	0	2	1	2	Forbidden
	1	2	140 μW	140 μW	2	0	2	1	Forbidden
	1	2	560 μW	440 μW	1	1	1	1	Intermediate
Active State (VPL)	2	0	1.50 mW	1.02 mW	0	2	0	2	Reset
	2	0	850 μW	850 μW	2	0	2	0	Set
	2	0	170 μW	240 μW	1	1	1	1	Forbidden
	2	1	140 μW	180 μW	0	2	2	2	Forbidden
	2	1	155 μW	120 μW	2	0	2	1	Forbidden
	2	1	670 μW	445 μW	1	1	1	1	Intermediate
	2	2	385 µW	140 μW	0	2	2	2	Forbidden
	2	2	470 μW	810 μW	2	0	2	2	Forbidden
	2	2	540 μW	1.24 mW	1	1	2	2	Forbidden

.

Case 2: The clock is “Logic-1”, Input S is ‘Logic-1’ or L45P and R is ‘Logic-1’ or L45P. The polarization rotation switching occurs at the resonant wavelength of 1548.42 nm due to the MRR-PRS property. Three different outputs are obtained for different combinations of the previous output states. When the previous outputs Q_n = 1 and $\overline{{\mathrm{Q}}_{\mathrm{n}}}$ = 1, the next output Q_n+1 is obtained as ‘Logic-1’ or L45P at the TP-3 of the MRR-3. The output $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ is also obtained as ‘Logic-1’ or L45P at the TP-4 of the MRR-4. The Jones parameter representations of Q_n+1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ are shown in Figure 15a and Figure 16a, respectively. According to the simulation results in Figure 15a and Figure 16a, it is observed that the azimuth angle is 45° and the ellipticity angle is almost 0°, which implies that the output is ‘Logic-1’ or L45P.

The Stokes parameters for Q_n+1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ are illustrated in Figure 15b and Figure 16b, respectively. From Figure 15b and Figure 16b, the Stokes parameters are [S₁ = 0, S2 = 1, S3 = 0]. It is shown that the Q_n+1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ outputs are ‘Logic-1’ or L45P. The outputs of the TP-3 and TP-4 for the above-mentioned combinations are (1, 1), which implies the intermediate condition. All three cases are shown in the thirteenth to fifteenth rows of Table 8.

Case 3: The clock is “Logic -2”, input S is ‘Logic-2’ or VPL (↑) and R is ‘Logic-0’ or HPL (•). Three different outputs are obtained for the different combinations of the previous output states. When the previous outputs are Q_n = 2 and $\overline{{\mathrm{Q}}_{\mathrm{n}}}$ = 0, the next output Q_n+1 is obtained at the TP-3 of the MRR-3, which receives the ‘Logic-2’ or VPL (↑). The output $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ is obtained at the TP-4 of the MRR-4, which receives the ‘Logic-0’ or HPL (•). The Jones parameters’ representation of Q_n+1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ is shown in Figure 17a and Figure 18a, respectively. According to the simulation results in Figure 17a, it is observed that the azimuth angle is 90° and the ellipticity angle is almost 0°, which implies that the output is ‘Logic-2’ or VPL (↑). Similarly, from the simulation results in Figure 18a, it is observed that both the azimuth angle and the ellipticity angle are almost 0°, which implies that the output is ‘Logic-0’ or HPL (•).

The Stokes parameters for Q_n+1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ are depicted in Figure 17b and Figure 18b, respectively. From Figure 17b and Figure 18b, the Stokes parameters are [S₁ = −1, S₂ = 0, S3 = 0] and [S₁ = 1, S₂ = 0, S3 = 0], respectively. It is validated that outputs Q_n+1 and $\overline{{\mathrm{Q}}_{\mathrm{n}+1}}$ are ‘Logic-2’ or VPL (↑) and ‘Logic-0’ or HPL (•), respectively. The outputs of the TP-3 and TP-4 for the above-mentioned combinations are (2, 0), which satisfies the SET condition. All three cases are shown in the nineteenth to twenty-first rows of Table 8.

4.3. Discussion

The performance improvement of all optical ternary flip-flop in MRR is reflected through several key metrics, such as on-off ratio, free spectral range (FSR), switching speed, compactness, power efficiency, and attenuation loss.

We calculated the on-off ratio and free spectral range (FSR) from the transmission curve as shown in Figure 19. The on-off ratio is an important parameter of the micro-ring resonator-based ternary inverter and T-clock SR flip-flop. It can be quantified by calculating the ration of the “ON resonance” signal to the “OFF resonance” signal:

$$\mathrm{ON}\text{-}\mathrm{OFF} \mathrm{ratio} = {\displaystyle \frac{{\mathrm{T}}_{\mathrm{MAX}\left(\mathrm{ThroughPort}\right)}}{{\mathrm{T}}_{\mathrm{MIN}\left(\mathrm{DropPort}\right)}}}$$

(1)

For high performance, the value of the on-off ratio of micro-ring resonator-based devices should be greater than 20 dB [38] and the obtained value from the simulation of our proposed design is 19.12 dB, which is slightly less than the desired value. There is a scope to improve on-off ratio by optimizing more preciously the ring parameters, like ring radius, coupling coefficient. The output FSR is defined as the wavelength range between two successive resonance peaks and the calculated value from the simulation is nearly 9.35 nm. The other performance parameters of the model are switching speed and attenuation loss. The simulation results for switching speed and overall attenuation loss of the proposed model are shown in Figure 20. The switching speed and overall attenuation loss of the proposed circuit are 0.14 ps, 0.52 dB, respectively. The proposed ternary circuit reduces the total number of logic elements, which translates to lower overall power consumption. In the proposed model the required power varies from µW to a few mW only. The ternary flip-flops store three discrete logic levels (0, 1, 2) unlike binary flip-flops. This reduces the required number of components and interconnect complexity in multi-valued logic (MVL) systems, which leads to higher integration density in photonic circuits, which is another important improvement of the proposed design.

The device performance is affected by fabrication tolerances, such as variations in ring radius, and coupling coefficient. So, the proposed model is analyzed by considering variation of coupling coefficient (k). The variations of azimuth angle with k₁ = 0.45(±0.05), i.e., 0.4 and 0.5 with constant k₂ = 0.45 and constant ring radius R₀ = 12 µm are observed and shown in Figure 21a and Figure 21b, respectively. From Figure 21 it is observed that the azimuth angle varies less than 10% for the above variation of coupling coefficient.

Similarly, variation of the MRR radius is analyzed. In the proposed model radius of the MRR is considered as 12 µm. The variations of azimuth angle with radius, R₀ = (12 ± 1) µm with constant k₁ = k₂ = 0.45 are observed and shown in Figure 22a and Figure 22b, respectively. From Figure 22 it is observed that the tolerance level of the radius may be considered as 10%.

5. Conclusions

In this study, we have designed ternary inverter and SR flip-flop by exploiting PRS-MRR-based ternary NAND logic gates using Interconnect simulation software. The obtained simulation results for the ternary inverter and the clocked SR flip-flop are confirmed by both the Stokes parameters and the Jones matrix. The PRS-MRR-based design is compact, simple and requires very small power with very high switching speed of 0.141 ps. The control signal power is very low and it is in the range of micro-watts to a few milli-watts. The parameters are optimized in such a way that proper polarization conversion occurs. So, these methods can be successfully implemented for higher-order MVL logic and counter circuits. Furthermore, AI-based modeling might be a future option for studying more complex, cascaded systems, demonstrating a forward-looking perspective and broader awareness of the field.