Search Results (138)

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

This work investigates the effects of radiation on FinFET-based full adders, which are crucial components of arithmetic units, particularly in aerospace and space applications. While FinFETs offer significant advantages, they remain susceptible to single-event transients (SETs) induced by radiation, which can cause computational errors. We assess three circuit-level mitigation techniques against SETs in FinFET adders: decoupling cells (DCELLs), transistor sizing (TS), and a combined approach incorporating both methods. Our results demonstrate that the most sensitive nodes and critical vectors in the adders vary depending on the mitigation strategy, underscoring their impact on overall radiation resilience. By analyzing these techniques alongside critical node evaluation, we identify their advantages and limitations, providing insights to enhance the robustness of FinFET-based processors in radiation-prone environments. Full article

As semiconductor devices approach the sub-10 nm technology node, the self-heating effect (SHE) induced by confined geometries (e.g., FinFETs and nanosheet FETs) has emerged as a critical bottleneck affecting both performance and reliability. This challenge has prompted extensive research efforts to develop advanced characterization methodologies to investigate this effect and its corresponding influence on the device’s reliability issues. In this paper, we propose reflection-based ultra-fast measurement techniques for the continuous monitoring of the self-heating effect in advanced MOSFETs. With this approach, the self-heating effect-induced degradation of transistor drain current and the real-time temperature change can be continuously captured using a digital phosphor oscilloscope on a nanosecond scale. The thermal time constant of 17 ns and the thermal resistance of 34,000 K/W have been extracted for the short channel transistors used in this study with the help of this new characterization method. This reflection-based method is useful for the fast extraction of the thermal time constant and thermal resistance and for the continuous monitoring of current degradation as well as the real-time temperature. Therefore, this new characterization method is beneficial for the evaluation of the self-heating effect in advanced ultra-scaled MOSFETs. Full article

With the continuous scaling of CMOS technology, stress engineering has become increasingly critical at advanced technology nodes, especially in tall and narrow FinFET structures. Asymmetric layout environments (such as dual-Fin structures or poly cuts) can introduce stress imbalance originating from shallow trench isolation (STI), which in turn affects device performance. In this study, TCAD simulations were performed on n-type FinFETs representative of the 10 nm technology node, with a physical gate length of 20 nm, to investigate the correlation between asymmetric stress and device drive current. As the Fin width decreases, the asymmetric stress from STI induces noticeable performance fluctuations, with the mobility enhancement under saturation bias reaching a maximum of 8.42% at W = 6 nm. Similarly, as the Fin body angle deviates from 90° and the Fin top narrows, with W_top = 6 nm and W_bottom = 8 nm, the mobility enhancement peaks at 7.65%. The simulation results confirm that STI-induced asymmetric stress has a significant impact on the Fin sidewall channel, while its effect on the top channel is minimal. To mitigate these effects, CESL stress engineering is proposed as an effective solution to amplify the top channel current, thereby reducing the influence of asymmetric stress on device performance. A CESL stress of 2.0 GPa is shown to improve device stability by approximately 20%. Full article

Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources ⁵⁸$Ni$ and ²⁸$Si$, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs. Full article

In this paper, a novel approach to symbolic regression using Kolmogorov–Arnold Networks (KAN) for developing gray-box Simulation Program with Integrated Circuit Emphasis models of generic transistors is proposed. Unlike traditional black-box models, such as artificial neural networks, (ANN), the developed KAN-based model enhances interpretability by generating explicit mathematical expressions while maintaining high accuracy in device modeling. By combining the computational efficiency of neural network approaches with the transparency of formula-based modeling, the SPICE model generation is significantly accelerated, thereby improving the efficiency of the design technology co-optimization (DTCO) process. The experimental results demonstrate that the expressions derived from the KAN model accurately represent the current–voltage (I–V) characteristics of the BSIM–CMG compact model and provide nearly symmetric results. To further validate the effectiveness and versatility of the approach, we embedded the trained I–V KAN model into a 12 nm FinFET SPICE model and performed 11-stage ring oscillator (RO) simulations. The results indicate that the KAN-based SPICE model achieves accuracy comparable to the original 12 nm FinFET SPICE model, demonstrating its potential to streamline device modeling for advanced technology nodes. Full article

As semiconductor technology and process nodes advance, three-dimensional devices like FinFET and NSFET are increasingly becoming the primary choice, replacing planar MOSFETs. However, the complex manufacturing processes and high process sensitivity of three-dimensional devices at advanced process nodes inevitably cause significant deviations from the ideal structure during actual fabrication, leading to notable changes in their electrical characteristics. This paper investigates the impact of source/drain region height fluctuations caused by etching and epitaxial growth variations on the electrical characteristics of FinFET and NSFET devices, as well as their related circuits. The electrical characteristics when height variations occur in single and multiple electrodes indicate that, although NSFET and FinFET generally exhibit similar properties such as a decrease in the ON-state current when the source/drain height is reduced, the independent nature of the nanosheets in NSFET and the unidirectional conduction of Schottky contact resistance cause significant differences in their electrical characteristics. Additionally, the related circuit-level simulations show that height fluctuations in the source/drain regions of devices can significantly impact circuit characteristics, including voltage and delay, and in severe cases, they may even lead to circuit failure. Full article

Decoders are among the most fundamental components in digital circuit design. They are widely used in combinational logic to convert and route binary data, as well as in memory array logic, for decoding binary addresses that point to the memory locations to be accessed. Due to their extensive utilization, optimizing decoder cells can potentially yield perceivable improvements in a digital system. This paper introduces 3-Transistor Logic (3TL), a new design approach for the optimization of CMOS decoder circuits, which combines static CMOS, Transmission-Gate Logic, and Dual-Value Logic. A complete transistor-level design methodology is demonstrated for decoder sizes from $2\times 4$ up to $8\times 256$, using 15 nm FinFET technology. Furthermore, an extensive comparative analysis is conducted with transistor-level simulations, evaluating the new circuits against conventional static CMOS and other previously proposed designs. The results show that 3TL circuits offer the best overall performance in terms of active power consumption, standby power consumption, and delay, owing largely to the fact that they are designed with logic efficiency and the minimum possible number of transistors. Full article

The HCI effect has been the focus of research as a common reliability consideration under advanced nodes in semiconductors. In this paper, a new compact model that takes into account the self-heating effect, width dependence, and substrate voltage dependence is proposed in the framework of a self-saturated power–law model containing oxide defects. The compact model employs different parameters in different carrier energy regions to improve the accuracy of the model. The predictions of the model fit well with experimental data extracted from the literature and the TCAD data, proving the validity of the model. Meanwhile, the model is used in this paper to predict and analyze the HCI’s degradation as well as lifetime under different conditions. Full article

Despite the advantages of fin field-effect transistors (FinFETs), there are hidden issues such as electric field enhancement and exacerbated self-heating effects, which will intensify device aging effects. Due to the escalating costs associated with aging protection at the device process level, there is an urgent need to reduce the impact of aging on circuit performance from the circuit design perspective. This study focuses on the specific structure of the strong-arm latch comparator and conducts a detailed aging analysis. Based on the quasi-static approximation (QSA) model, the threshold voltage shift under operational stress is simulated. It is concluded that both the hot carrier injection (HCI) effect and negative bias temperature instability (NBTI) effect play equally non-negligible roles. Furthermore, aging tests were conducted based on 14 nm FinFET devices, validating the substantial HCI effects induced by short-duration pulses. Simultaneously, the test results suggest that the aging effect becomes more remarkable with increasing current. An improved circuit is proposed to reduce the HCI effect by reducing the current pulse by the way of pre-charging, which effectively reduces the threshold voltage shift of the latch comparator input transistors. Full article

Frequency divider circuits divide the frequency of an input signal by a specified ratio. They are critical components in analog, digital, and mixed-signal microelectronics. In power-constrained environments, such as cryogenic electronics or implanted biomedical devices, minimizing power consumption is crucial. This paper reviews operational principles, benefits, trade-offs, and circuit solutions of three main typologies of frequency divider: Current Mode Logic (CML), Injection-Locking (IL), and True Single-Phase Clock (TSPC). Distinct trade-offs between operation speed, power efficiency, complexity, and integration make each of them suitable for specific applications. Nevertheless, hybrid circuit solutions combining different typologies could potentially balance performance and energy efficiency. This paper thus also reports and discusses examples of hybrid frequency dividers. Examples of frequency dividers implemented in emerging technologies, such as the FinFETs CMOS, are addressed, as well. The purpose of this paper is to guide designers in selecting frequency divider solutions that best meet the design-specific requirements. Full article

The SiC MOSFET with an integrated SBD (SBD-MOSFET) exhibits excellent performance in power electronics. However, the static and dynamic characteristics of this device are influenced by a multitude of parameters, and traditional TCAD simulation methods are often characterized by their complexity. Due to the increasing research on neural networks in recent years, such as the application of neural networks to the prediction of GaN JBS and Finfet devices, this paper considers the application of neural networks to the performance prediction of SiC MOSFET devices with an integrated SBD. This study introduces a novel approach utilizing neural network machine learning to predict the static and dynamic characteristics of the SBD-MOSFET. In this research, SBD-MOSFET devices are modeled and simulated using Sentaurus TCAD(2017) software, resulting in the generation of 625 sets of device structure and sample data, which serve as the sample set for the neural network. These input variables are then fed into the neural network for prediction. The findings indicate that the mean square error (MSE) values for the threshold voltage (Vth), breakdown voltage (BV), specific on-resistance (R_on), and total switching power dissipation (E) are 0.0051, 0.0031, 0.0065, and 0.0220, respectively, demonstrating a high degree of accuracy in the predicted values. Meanwhile, in the comparison of convolutional neural networks and machine learning, the CNN accuracy is much higher than the machine learning methods. This method of predicting device performance via neural networks offers a rapid means of designing SBD-MOSFETs with specified performance targets, thereby presenting significant advantages in accelerating research on SBD-MOSFET performance prediction. Full article

Based on the minimum conduction band edge caused by the minimum channel potential resulting from the quasi-3D scaling theory and the 3D density of state (DOS) accompanied by the Fermi–Dirac distribution function on the source and drain sides, a unified semiconductor-device-physics-based ballistic model is developed for the threshold voltage of modern multiple-gate (MG) transistors, including FinFET, Ω-gate MOSFET, and nanosheet (NS) MOSFET. It is shown that the thin silicon, thin gate oxide, and high work function will alleviate ballistic effects and resist threshold voltage degradation. In addition, as the device dimension is further reduced to give rise to the 2D/1D DOS, the lowest conduction band edge is increased to resist threshold voltage degradation. The nanosheet MOSFET exhibits the largest threshold voltage among the three transistors due to the smallest minimum conduction band edge caused by the quasi-3D minimum channel potential. When the n-type MOSFET (N-FET) is compared to the P-type MOSFET (P-FET), the P-FET shows more threshold voltage because the hole has a more effective mass than the electron. Full article

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications, such as speech recognition, facial recognition, and object detection, has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to memory access times and power consumption challenges. To address these challenges, we propose the application of computing-in-memory (CIM) within FinFET-based 8T SRAM structures, specifically utilizing P-latch N-access (PLNA) and single-ended (SE) configurations. Our design significantly reduces power consumption by up to 56% in the PLNA configuration and 60% in the SEconfiguration compared to traditional FinFET SRAM designs. These reductions are achieved while maintaining competitive delay performance, making our approach a promising solution for implementing efficient and low-power AI hardware. Detailed simulations in 7 nm FinFET technology underscore the potential of these CIM-based SRAM structures in overcoming the computational bottlenecks associated with DNNs and CNNs. Full article

The continuous scaling down of MOSFETs is one of the present trends in semiconductor devices to increase device performance. Nevertheless, with scaling down beyond 22 nm technology, the performance of even the newer nanodevices with multi-gate architecture declines with an increase in short channel effects (SCEs). Consequently, to facilitate further increases in the drain current, the use of strained silicon technology provides a better solution. Thus, the development of a novel Gate-All-Around Field-Effect Transistor (GAAFET) incorporating a strained silicon channel with a 10 nm gate length is initiated and discussed. In this device, strain is incorporated in the channel, where a strained silicon germanium layer is wedged between two strained silicon layers. The GAAFET device has four gates that surround the channel to provide improved control of the gate over the strained channel region and also reduce the short channel effects in the devices. The electrical properties, such as the on current, off current, threshold voltage (V_TH), subthreshold slope, drain-induced barrier lowering (DIBL), and I_on/I_off current ratio, of the 10 nm channel length GAAFET are compared with the 22 nm strained silicon channel GAAFET, the existing SOI FinFET device on 10 nm gate length, and IRDS 2022 specifications device. The developed 10 nm channel length GAAFET, having an ultrathin strained silicon channel, delivers enriched device performance, being augmented in contrast to the IRDS 2022 specifications device, showing improved characteristics along with amended SCEs. Full article