Search Results (59)

Thermoelectric generator (TEG)-based energy harvesting (EH) has emerged as a promising solution for powering ultra-low-power electronic systems. However, the inherently low output voltage of miniature TEGs is often below a range of 40–100 mV under small temperature gradients, presenting a fundamental cold-start challenge for DC-DC boost converters, preventing fully autonomous operation without dedicated start-up circuitry. Although numerous start-up techniques have been reported, the existing literature lacks a focused, design-oriented review of circuit architecture specifically optimized for ultra-low-voltage TEG applications. This paper addresses this gap by introducing a unified classification framework and providing a structured, topology-oriented analysis of state-of-the-art start-up strategies for TEG-based EH systems. Reported techniques are organized into five categories: external energy assistance, mechanical switch-assisted techniques, multi-source EH, transformer-based architectures, and oscillator-driven DC-AC-DC conversion. Each category is comparatively evaluated in terms of start-up voltage, integration level, efficiency, and system autonomy. Among these, oscillator-based approaches, particularly ring oscillator (RO) architectures, emerge as the most viable pathway toward fully integrated and scalable implementations, owing to their CMOS compatibility and architectural flexibility. The review further discusses key design trade-offs, handover stability challenges, and practical limitations, and provides architectural insights to guide the development of next-generation autonomous TEG-powered platforms. Full article

This paper presents a 2-GS/s voltage–time hybrid pipelined analog-to-digital converter (ADC) with a 14-bit digital output, implemented in a 28-nm CMOS process. To alleviate the gain–bandwidth–power trade-off in deeply scaled technologies, the proposed architecture employs a SHA-less front-end and a low-gain inverter-based push–pull RA for energy-efficient coarse quantization. The residue is then transferred to the time domain via a highly linear constant-current voltage-to-time converter (CC-VTC) and digitized by a four-channel time-interleaved gated-ring-oscillator (GRO) TDC. To recover dynamic linearity degraded by low-gain amplification and interleaving mismatches, a multiplier-less digital background calibration engine is implemented. Leveraging mean absolute value (MAV) statistics and dither-injected least-mean-squares (LMS) algorithms, it effectively compensates for inter-channel and interstage errors with minimal hardware overhead. The prototype occupies an active area of 0.16 mm². At 2 GS/s, the ADC achieves a Nyquist SNDR of 63.42 dB and an SFDR of 73.71 dB, corresponding to an ENOB of 10.24 bits. Consuming 86.9 mW from a 1-V supply, it achieves a Walden FoM of 35.9 fJ/conv.-step. Measurement results from multiple chips under a wide range of operating conditions verify the robustness of the proposed ADC. Full article

This paper presents a novel dual-mode memristor-based ring oscillator designed for energy-efficient, wireless biomedical signal conditioning systems. The proposed architecture leverages a compact DTMOS memristor emulator, consisting of only two transistors and one capacitor, to replace the conventional NMOS pull-down devices in a three-stage PMOS ring oscillator. This integration enables two distinct operating modes within a single compact core: a fixed-frequency mode for stable clock generation and carrier synthesis, and a programmable chirp mode for frequency-modulated signal generation. The fixed-frequency mode achieves continuous tuning from 3.142 GHz to 4.017 GHz via varactor control, with an ultra-low power consumption of only 111 µW at 4.017 GHz. The chirp mode generates linear frequency sweeps starting from 0.8 GHz, with the sweep range independently controllable through the state capacitor value and the pulse width of the control signal (SW_Chirp). Designed in a standard 0.18 µm CMOS process, the oscillator exhibits a low phase noise of −87.82 dBc/Hz at a 1 MHz offset for the three-stage configuration, improving to −94.3 dBc/Hz for the five-stage design. The overall frequency coverage spans 0.8–4.017 GHz, representing a 133.6% fractional range. The calculated figure of merit (FoM) is −169.45 dBc/Hz. Experimental validation using a discrete CD4007 prototype confirms the oscillation principle, while comprehensive simulations demonstrate robust performance across process corners and temperature variations. With its zero-static-power memristor core, wide tunability, and dual-mode reconfigurability, the proposed oscillator is ideally suited for multi-standard wireless biomedical applications, including implantable telemetry, neural stimulation, ultra-wideband (UWB) transmitters, and non-contact vital sign monitoring. Full article

As the mainstream technology solution for deep imaging LiDAR, dToF measurement has been widely applied in emerging fields such as environmental perception and obstacle recognition, 3D terrain reconstruction, real-time motion capture, and drone obstacle avoidance navigation due to its advantages of high resolution, long-range detection capability, and high sensitivity. In order to adapt to functional applications in different scenarios, the resolution of TDC needs to be adjustable and can work normally in different environments. In view of this, this article studies the pixel array and TDC circuit in the chip and locks a voltage-controlled ring oscillator (VCRO) with the same structure as the pixel to a fixed frequency through a PLL structure. Then copy the control voltage of the locked VCRO to the control terminal of the TDC in each pixel. In an ideal situation, this control voltage can make the oscillation frequency of VCRO within the pixel consistent with the locking frequency of VCRO within the PLL, and insensitive to changes in PVT. This study developed a module expandable 16 × 16-pixel array dToF sensor chip based on TDC architecture using CMOS technology. Finally, six configurable 16 × 16-pixel subarrays were integrated and constructed into a 32 × 48 large-scale dToF sensor chip through modular splicing. The top-level layout design was completed using SMIC 180 nm technology, with a layout area of 5285 µm × 3669 µm. Post-simulation verification showed that, under the testing conditions of a 400 MHz system clock and a 33.3 kHz frame rate, the dToF chip system performance indicators were: time measurement resolution of 156 ps, DNL < 1 LSB, INL < 0.85 LSB, and absolute ranging accuracy better than 2.5 cm. Full article

A ring-oscillator based voltage-controlled oscillator (VCO) architecture with reduced frequency drift across temperature and process variations is presented in this paper. The frequency stability is achieved through two dedicated compensation techniques: a temperature compensation circuit that generates a proportional-to-absolute-temperature (PTAT) current to mitigate frequency shifts due to temperature changes, and a process compensation circuit that dynamically adjusts the frequency based on detected process corners. The proposed design is implemented in a 22 nm CMOS technology with a 0.8 V supply voltage and targets a nominal oscillation frequency of 2.5 GHz. The post-layout simulation results demonstrate a significant improvement in frequency stability, reducing temperature-induced frequency drift from 23.9% to a range of 5.4% over the −40 °C to 125 °C temperature range for the typical corner. Combining temperature and process compensation, the frequency drift is improved from 47.3% to better than 7.2%. The VCO also achieves a phase noise value about −80 dBc/Hz at a 1 MHz offset with an average power consumption of 380 µW, including the tuning mechanism and the compensation circuits. Full article

This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (I_BIAS) modulation from 30–130 nA, while a four-stage configuration spans 388–587 MHz. At 70 nA I_BIAS, the three-stage design delivers a nominal frequency of 666.8 MHz with just 10.23 µW power dissipation, underscoring its suitability for ultra-low-power IoT and biomedical applications. The oscillator’s linear frequency sensitivity (2.63 MHz/nA) allows precise, dynamic control over performance–power tradeoffs. To address diverse application needs, the design integrates three tunability mechanisms: programmable capacitor arrays for coarse frequency adjustments, configurable stage counts (three- or four-stage topologies), and supply voltage scaling. This multi-modal approach extends the operational range to 1 MHz–1 GHz, ensuring compatibility with low-speed sensor interfaces and high-speed edge-computing tasks. The CCRO’s subthreshold operation at 0.4 V—coupled with nanoampere-level current consumption—makes it uniquely suited for battery-less systems, wearable health monitors, and implantable medical devices where energy efficiency and adaptive clocking are paramount. By eliminating traditional voltage-controlled oscillators’ complexity, this topology offers a compact, scalable solution for emerging ultra-low-power technologies. Full article

This paper presents a novel passive floating memristor emulator that operates without an external DC bias, leveraging the DTMOS technique. The design comprises only four MOSFETs and eliminates the need for external capacitors. The emulator achieves a high operating frequency of around 250 MHz and consumes zero static power. A comprehensive analysis and simulation, conducted using 180 nm CMOS technology, validates the circuit’s performance. The versatility and effectiveness of the proposed emulator are demonstrated through its application in various circuits, including logic gates, a ring oscillator, and analog filters, highlighting its potential for diverse low-power, high-frequency applications. The proposed emulator provides a compact, efficient, and integrable solution for nanoelectronic circuit designs. Full article

This work presents a nano-watt digital output temperature sensor featuring a supply-insensitive, self-biased current source. Second-order temperature dependencies of the MOS diode are canceled to produce a stable reference and a linear temperature-sensitive voltage. The sensor integrates a sensing unit, voltage-controlled differential ring oscillators, and a low-power frequency-to-digital converter, utilizing a resistor-less design to minimize power and area. The delay element in the ring oscillator reduces stage count, improving noise performance and compactness. Fabricated in 65 nm CMOS, the sensor occupies 0.02 mm² and consumes 60 nW at 25 °C and 0.8 V. Measurements show an inaccuracy of +1.5/−1.6 °C from −20 °C to 120 °C after two-point calibration, with a resolution of 0.2 °C (rms) and a resolution FoM of 0.022 nJ·K⁻². Consuming 0.55 nJ per conversion with a 9.2 ms conversion time, the sensor was tested in a battery-less wireless sensor node, demonstrating its suitability for wireless sensing systems. Full article

The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm²), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to test whether the ECC function operates normally in the MTP IP with a built-in ECC function, and it is confirmed through a test using logic tester equipment that the output data DOUT[7:0] and the error flag ERROR_FLAG[1:0] are exactly the same in the cases of no error, a single-bit error, and a double-bit error. In addition, by sharing a current-controlled ring oscillator circuit that uses a current-starved inverter in the VPP, VNN, and VNNL charge pumping circuits that share a single ring oscillator in the erase and program operation modes of the MTP IP and using the regulated VPVR as power, the pumping capacitor size is reduced, and a new technology to reduce ripple voltage variation is proposed. Meanwhile, in the VNN level detector circuit that detects whether the VNN has reached the target voltage, a folded-cascode CMOS OP-AMP whose output swing voltage is almost VDD is used instead of a differential amplifier circuit with a PMOS differential input pair to ensure that normal VNN level detection operation occurs. Full article

This paper introduces a novel TRNG architecture that employs a wave converter to generate random outputs from the jitter noise in a customized ring oscillator (RO). Using a current-starved inverter, the proposed RO offers the option of operating three different oscillation frequencies from a single oscillator. To assess its performance, the core TRNG proposed in this work was designed with multiple samples, employing various transistor sizes for 28 nm CMOS processes. The measurements show that only a small number of measured TRNG samples passed the randomness NIST SP 800-22 tests, which is a common problem, not only with the proposed TRNG but also with other TRNG structures. To solve this issue, a lightweight post-processing algorithm using the Photon hash function was newly applied to the proposed TRNGs topology. The lightweight Photon hash function-based post-processing was implemented with the proposed TRNG topology in a 28 nm CMOS process. The design occupies 16,498 µm², with a throughput of 0.0142 Mbps and power consumption of 31.12 mW. Measurements showed significant improvement, with a 50% increase in chips passing the NIST SP 800-22 tests. Compared with the conventional DRBG post-processing method, the proposed lightweight Photon post-processing reduces area occupation by five times and power consumption by 65%. Full article

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs. Full article

PLLs with small areas, low power consumption, and low jitter are crucial for mobile applications. Hence, achieving a balance between the area, power consumption, and noise of a PLL is a significant issue. In this work, a compact, low-power, and low-jitter fractional-N PLL using Ring-VCO is introduced. In order to reduce area and power consumption, a single-ended Ring-VCO is implemented. Additionally, novel resistance matrixes are proposed to decrease phase noise. The resistor matrix creates 13 frequency tuning curves with close VCO gain and different initial frequencies, reducing the VCO gain and thus the overall noise while maintaining high tuning linearity. The proposed PLL is fabricated based on 12 nm FinFET technology with a 0.078 mm² area. It achieves a 2.702 ps RMS jitter at 5.76 GHz while consuming 6.4 mW. Moreover, it maintains a low power consumption and a low RMS jitter across the entire frequency range. Full article

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support V_CM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s. Full article

A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Express protocols, with optimized performance in all of them, including the current consumption, the phase noise, and the frequency tuning in each case. Designed in a CMOS 22 nm technology node with a 0.8 V supply voltage, it can achieve, at 3 GHz frequency, a phase noise better than −90 dBc/Hz at 1 MHz offset and an average power consumption equal to 3.84 mW. Extended digital control can set optimized configurations for phase noise, current consumption, and VCO gain vs. process variations. Extensive post-layout simulation results verify the superior performance. Full article

This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce jitter variations, minimize oscillator spurious signals, and eliminate periodical phase error, a double edge-injection (window injection) scheme with synchronized edge directions is proposed. A combinational edge generator is utilized to substitute the sequential edge generators for injection timing requirements relaxation. By biasing devices in deep triode, digitally controlled delay cells currents are adopted for frequency tuning. This helps reducing the devices flicker (1/f) noise and minimize the DCRO overall phase noise. At 1 MHz offset of frequency, the proposed oscillator has a measured phase noise of −125.95 dBc/Hz and −115.6 dBc/Hz at oscillation frequencies of 913.4 MHz and 432.6 MHz, respectively. Fabricated in 350 nm CMOS process, with a maximum power consumption of 3.3 mW, and oscillating at 913.4 MHz, this DCRO achieves a tuned oscillator figure of merit (FoM) of −197.35 dBc/Hz. The core area of this edge-injection-based DRCO is only 0.08 mm². Full article