A Compact, Low-Power, and Low-Jitter Fractional-N Phase-Locked Loop with a Single-Ended Ring Voltage-Controlled Oscillator in a 12 nm CMOS FinFET

Abstract

PLLs with small areas, low power consumption, and low jitter are crucial for mobile applications. Hence, achieving a balance between the area, power consumption, and noise of a PLL is a significant issue. In this work, a compact, low-power, and low-jitter fractional-N PLL using Ring-VCO is introduced. In order to reduce area and power consumption, a single-ended Ring-VCO is implemented. Additionally, novel resistance matrixes are proposed to decrease phase noise. The resistor matrix creates 13 frequency tuning curves with close VCO gain and different initial frequencies, reducing the VCO gain and thus the overall noise while maintaining high tuning linearity. The proposed PLL is fabricated based on 12 nm FinFET technology with a 0.078 mm² area. It achieves a 2.702 ps RMS jitter at 5.76 GHz while consuming 6.4 mW. Moreover, it maintains a low power consumption and a low RMS jitter across the entire frequency range.

1. Introduction

Phase-locked loops (PLLs) are essential components in wireless communication systems for generating high-performance clock signals [1,2,3,4]. With the explosive development of mobile applications, there is an increasing demand for highly integrated and low-power-consuming PLLs [5,6,7]. To achieve a smaller area and lower power, digital PLLs have been developed, which offer advantages such as compactness, low power consumption, and high programmability [8,9,10]. However, digital PLLs have longer lock-in time and inferior noise performance compared to analog PLLs [11,12]. In conventional analog PLLs, the low-pass filter (LPF) and the voltage-controlled oscillator (VCO) are the primary contributors to the overall area. On the one hand, the structure of LPFs is simple and closely related to the bandwidth, leading to difficulty in modification. On the other hand, due to the diverse implementation methods of the VCO [13], there is potential to reduce its area.

The LC-VCO shown in Figure 1a is commonly used in conventional analog PLLs, featuring a simple structure and low jitter [14,15,16,17]. In comparison, the Ring-VCO is formed by connecting an odd number of delay units in series, eliminating the need for capacitors and inductors. This results in a smaller area [18,19,20]. Many studies have proposed PLLs based on differential Ring-VCOs, which achieve a compact area and wide tuning range at the expense of increased noise [21,22,23]. Moreover, the area and power of the VCO can be further reduced.

Here, for the first time, we propose a single-ended Ring-VCO-based PLL based on the FinFET process. Compared to the delay units of the differential Ring-VCO shown in Figure 1b, the delay units of the single-ended Ring-VCO (Figure 1c) employ fewer devices and require no tail current circuit. In addition, it requires a smaller voltage supply. This enables a smaller area and lower power consumption. In addition, novel resistor matrixes are proposed to construct 13 frequency tuning curves with close VCO gain ($K_{VCO}$) and different initial frequencies, which reduces $K_{VCO}$ and thus phase noise. The proposed PLL exhibits low complexity, minimal space requirements, and low power consumption, making it highly suitable for mobile RF transceivers. It achieves a small area of 0.078 mm² and low power of 6.4 mW. Additionally, it attains a maximum output frequency of 6.72 GHz and an RMS jitter of only 2.702 ps.

2. The Design Scheme of the Proposed Ring-VCO

There are three common issues associated with single-ended Ring-VCOs when compared to other types of VCOs: low maximum frequency, poor stability, and low phase noise. In this study, we propose the following solutions.

The single-ended delay unit has low speed and therefore low maximum frequency. And since the current driving capability of FinFETs is much better than MOSFETs, high frequencies can also be achieved using FinFET inverters [24]. Although the use of single-ended delay units reduces the maximum frequency, this problem is compensated by using the FinFET process, which increases the maximum frequency.

The single-ended delay unit is not stable, mainly because it is more susceptible to power supply fluctuations and spatial coupling than the differential delay unit. The solution is to use a stable power supply and protect it with guard rings in the layout.

The single-ended Ring-VCOs have poor phase noise, especially compared to LC-VCOs. So novel variable resistor matrixes are proposed to improve the noise performance by reducing the $K_{VCO}$. A total of 13 frequency tuning curves are created with close $K_{VCO}$ and different initial frequencies. Therefore, it is possible to reduce the $K_{VCO}$ and hence the overall phase noise of the PLL to an acceptable range.

Since the maximum frequency problem can be solved by process selection, and the stability problem can be solved by stabilizing the power supply and guard rings in the layout, the focus of the following part is on phase noise reduction through circuit improvement.

The output frequency of the VCO can be expressed in the time domain as

$${\omega }_{out}=K_{VCO}{V}_{ctrl}\left(t\right)+{\omega }_{init},$$

(1)

where $K_{VCO}$ is the VCO gain, $V_{ctrl}$ is the control voltage of the VCO, and ${\omega }_{init}$ is the initial frequency of the VCO. Integrating both sides of Equation (1) yields the VCO output phase in the time domain, as shown in Equation (2):

$${\varphi }_{out}\left(t\right)=\int {\omega }_{out}\left(t\right)dt=K_{VCO}\int V_{ctrl}\left(t\right)dt.$$

(2)

Considering $K_{VCO}$ as a time-independent component, the transfer function of the VCO in the frequency domain can be expressed as Equation (3):

$${\varphi }_{out}\left(s\right)=\frac{K_{VCO}}{s}{V}_{ctrl}\left(s\right).$$

(3)

Therefore, the noise components of the PLL are highly dependent on $K_{VCO}$. Decreasing $K_{VCO}$ can reduce phase noise.

Figure 2a shows the conventional Ring-VCO, while Figure 2b presents the proposed Ring-VCO. The oscillator is composed of three delay units shown in Figure 1c. Core devices with a power supply of 0.8 V are used in the oscillator, while I/O devices with a power supply of 1.8 V are used in the VCO to enhance the frequency tuning range. The voltage in the oscillator is kept below 0.8 V due to the presence of a cascode current mirror to divide the voltage. The core devices in the oscillator with a standard voltage of 0.8 V will not break down. Besides the oscillator, all other transistors in the proposed VCO are I/O devices with a standard voltage of 1.8 V. Therefore, there is no risk of breakdown.

In the conventional VCO, the input voltage $V_{ctrl}$ is converted into $I_{ctrl}$ through the input transistor and the resistance $R_S$ at its source. $I_{ctrl}$ controls the output frequency $f_{OSC}$, represented as Equations (4) and (5):

$$I_{ctrl}=\frac{g_m}{1+g_m{R}_S}{V}_{ctrl},$$

(4)

$$f_{OSC}=\frac{I_{ctrl}}{2N{C}_L{V}_{OSC}}=\frac{1}{2N{C}_L{V}_{OSC}}·\frac{g_m}{1+g_m{R}_S}{V}_{ctrl}.$$

(5)

Here, $g_m$ denotes the transconductance of the input transistor. $R_S$ is much larger than $1/g_m$, enhancing the linearity of the voltage–current conversion. $K_{VCO}$ can be represented as $g_m/(2N{C}_L{V}_{OSC}·(1+g_m{R}_S))$, which is an approximately constant value.

In the proposed VCO, variable resistive matrixes $R_S$ and $R_D$ are introduced. The control current $I_{OSC}$ of the ring oscillator is the sum of $I_{ctrl}$ and $I_{offset}$. Here, $I_{OSC}$ and $f_{OSC}$ are represented as follows:

$$I_{OSC}=I_{ctrl}+I_{offset}=\frac{g_m{V}_{ctrl}}{1+g_m{R}_S}+\frac{V_{DD}-V_{OSC}}{R_D},$$

(6)

$$f_{OSC}=\frac{I_{OSC}}{2N{C}_L{V}_{OSC}}=\frac{1}{2N{C}_L{V}_{OSC}}\left(\frac{g_m{V}_{ctrl}}{1+g_m{R}_S}+\frac{V_{DD}-V_{OSC}}{R_D}\right).$$

(7)

Based on different coarse tuning results of automatic frequency control, denoted as AFC<3:0>, varying values of $R_S$ and $R_D$ are chosen, leading to corresponding changes in $V_{OSC}$ and $I_{offset}$, thus resulting in different $K_{VCO}$ and initial frequencies. By choosing suitable adjustable resistances for $R_S$ and $R_D$, 13 curves are produced with similar $K_{VCO}$ and different initial frequencies, allowing for a broader frequency tuning range with reduced $K_{VCO}$.

The simulation results of the proposed VCO are illustrated in Figure 3. In Figure 3a–c, the AFC code of the curves changes from “0000” to “1100” along the direction of the black arrow. The AFC codes for curves of the same color are also the same. When $R_S$ and $R_D$ differ, the variation in $I_{ctrl}$ with $V_{ctrl}$ is shown in Figure 3a, and the change in output frequency with $I_{ctrl}$ is depicted in Figure 3b. In the proposed VCO, $V_{OSC}$ is not a constant value but varies with $R_D$, which affects $K_{VCO}$ by adjusting $V_{OSC}$. When an upward adjustment of the frequency tuning range is required, a smaller $R_S$ is selected, resulting in a larger slope of $I_{ctrl}$ vs. $V_{ctrl}$ (Figure 3a). At the same time, a smaller $R_D$ is selected. Since the oscillator and $R_D$ are on the same branch, the oscillator divides the voltage more and $V_{OSC}$ increases. From Equation (7), the slope of the output frequency vs. $I_{ctrl}$ becomes smaller (Figure 3b). By choosing the appropriate $R_S$ and $R_D$, it is possible to make the slope of $I_{ctrl}$ vs. $V_{ctrl}$ larger to the same extent as the slope of output frequency vs. $I_{ctrl}$ is smaller, so that the slope of output frequency vs. $V_{ctrl}$ is almost constant. In other words, smaller $R_S$ and larger $V_{OSC}$ values keep $K_{VCO}=g_m/(2N{C}_L{V}_{OSC}·(1+g_m{R}_S))$ nearly constant.

As illustrated in Figure 3c, by selecting the resistance values of $R_S$ and $R_D$ appropriately, 13 curves are obtained with close $K_{VCO}$ and different initial frequencies. Compared to the conventional VCO with a larger $K_{VCO}$ shown in Figure 2a, the simulation demonstrates better noise characteristics, as shown in Figure 3d.

Due to the variable resistance matrixes and reduced $K_{VCO}$, the phase noise of the proposed VCO is significantly decreased. Furthermore, the $K_{VCO}$ is consistent across different curves while maintaining high linearity. Only three additional resistor matrixes are required in this method, which enables minimal increase in area and power consumption.

The results across the PVTs (processes, voltages, temperatures) of the proposed VCO in post-layout simulation are shown in

Table 1. The results across PVTs of the proposed VCO in post-layout simulation.

	25 °C, 1.8 V, TPTN	MIN	MAX
Default frequency range (GHz)	4.5–7.9	3.6–7.2	5.4–8.2
Maximum frequency range (GHz)	9.5–12.5	8.2–11.7	9.9–12.3
Minimum frequency range (GHz)	0.7–4.4	0.4–3.8	1.5–4.9
Kvco variation	18.1%	12.9%	23.8%
Phase noise @ 1 MHz(dBc/Hz)	−81.45	−83.12	−78.77
power consumption(mW)	1.08	0.826	1.38

. The temperature variation range is from −40 °C to 125 °C, and the supply voltage variation range is from 1.65 V to 1.9 V. The process corners considered include S_PS_N, F_PF_N, S_PF_N, F_PS_N, and T_PT_N.

The PVT results show that the frequency tuning range exhibits minor variations with changes in temperature, supply voltage, and process corners. Moreover, in each corner, by selecting different tuning curves, a wide frequency range from low frequencies up to over 10 GHz can be covered. The variation rate of $K_{VCO}$ is maintained below 23.8% in all cases, achieving extremely high tuning linearity. The phase noise shows small variations, indicating that the proposed VCO can maintain similar phase noise performance across different corners. The power consumption has slightly larger variations but is still within an acceptable range. These results reflect the high stability of the proposed VCO under different temperatures, supply voltages, and process corners, showcasing its robustness and reliability in various operating conditions.

3. The Structure of the Proposed PLL

The block diagram of the proposed PLL is depicted in Figure 4. It comprises various components including a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a Ring-VCO, a divide-by-two circuit (DIV2), a multi-modulus divider (MMD), a delta-sigma modulator (DSM) with automatic frequency control (AFC), and a post divider.

The PFD compares the phase and frequency of the reference clock signal $R_{CK}$ and the feedback clock signal $f_{CK}$. The result of this comparison is sent to the CP as a current $I_{CP}$. CP then converts $I_{CP}$ into a voltage $V_{CP}$, which is subsequently filtered by the LPF. The output voltage $V_{ctrl}$ of the LPF regulates the frequency of the Ring-VCO. The output frequency $f_{out}$ of the Ring-VCO serves as the output of the PLL. It is divided by a high-speed divider-by-two and then further divided by an MMD that can divide by 16 to 255, allowing for capture of different feedback signals. The fractional division function is achieved by using a DSM, which includes AFC. Before PLL lock-in, the frequency is adjusted by utilizing the AFC, which selects a frequency curve that includes the desired target frequency by sending a four-bit code $V_{afc}$ to the VCO. A post divider is employed to divide the high-frequency signal by 16, 32, or 64 to facilitate testing purposes.

The noise from each aforementioned component can be represented by different types of noise signals injected at various nodes in the loop. These injected noises propagate through different feedforward and feedback paths to the output, resulting in corresponding phase noise components.

The simulation results of the overall noise of the PLL in integer-N mode are demonstrated in Figure 5. The results are obtained by post-layout simulation of phase noise for each module and then synthesized through MATLAB R2021a. The overall phase noise of the proposed PLL shown in Figure 5b is lower than that of the conventional PLL shown in Figure 5a. At low frequencies, the phase noise of the VCO is reduced, making the total phase noise lower. At high frequencies, since the noise transmission of the LPF is positively correlated with $K_{VCO}$, the noise reduction in the LPF at high frequencies makes the total phase noise lower.

4. Test Results and Discussions

The proposed fractional-N PLL with a small area and low power consumption was implemented using 12 nm FinFET technology. Figure 6 shows a micrograph of the chip, with the PLL occupying an area of 0.078 mm². The PLL layout is shown in the right part of the figure. The LPF, which utilizes a large number of capacitors and resistors, occupies the largest area. Considering the requirements for bandwidth and stability, it is difficult to reduce its area. The oscillator in the VCO only occupies a small area, protected by guard rings to enhance its stability.

The waveform was observed and captured by an oscilloscope (Tektronix MSO64B, Beaverton, OR, USA) and the spectrum and phase noise were measured by a spectrometer (Keysight 9030B, Santa Clara, CA, USA). Figure 7a displays the output of the VCO measured at the divide-by-two output, while Figure 7b shows the spectrum after dividing this output by 16. When the reference clock is 80 MHz and the PLL is divided by 16, the VCO output frequency should be 1.28 GHz. At this time, the output frequency of DIV2 is 640.6 MHz and the output swing is 2.153 V, which is marked in the red rectangle of Figure 7a. In order to measure the phase noise and jitter performance more accurately, the results of DIV2 were tested in the spectrometer after 16 divisions, and its peak was located at 40.04 MHz, which is demonstrated in the red rectangle in Figure 7b. These results show that the proposed PLL can work properly.

The main target applications of the proposed PLL are mobile RF transceivers for 2.4 GHz/5 GHz wireless communications. The 2.4 GHz band has a small range of 2.4–2.4835 GHz, and 14 sub-channels in a bandwidth of only 83.5 MHz, which requires more accurate fractional frequency division. The 5 GHz band has a larger range of 5.15–5.855 GHz, so integer frequency division can meet the demand. Therefore, we tested the performance of integer-N mode at 5.76 GHz and the performance of fractional-N mode at 3.19 GHz to conform to the respective applications. The test frequency of fractional-N mode was slightly larger than 2.4 GHz to demonstrate that it not only covers the 2.4 GHz application but also adapts to other potential applications.

The RMS jitter was tested using a reference input clock of 60 MHz. And the output signal of PLL is tested after dividing the frequency, which shows no impact on the size of the RMS jitter. In integer-N mode, the feedback frequency of the PLL is equal to the 60 MHz input frequency by dividing the frequency by 96 in the PLL. Therefore, the output frequency of the PLL is 60 MHz × 96 = 5.76 GHz. This frequency was tested after 32 divisions, so the integer division test frequency is 180 MHz. In the test of fractional-N mode, the division ratio is 53.25. Here, the output frequency of the PLL is 60 MHz × 53.25 = 3.195 GHz. This frequency was tested after 32 divisions and therefore the integer divided frequency was tested at 99.84375 MHz.

The phase noise performance of the PLL output in integer-N mode is shown in Figure 8. The orange curve represents the measured values, while the green curve represents the fitted values. The start and stop frequencies for the test are marked in the lower red rectangle of Figure 8, and the carrier frequency and RMS jitter are marked in the upper red rectangle. The actual output frequency of the PLL is 5.76 GHz, and the tested frequency is 180 MHz after 32 divisions. The RMS jitter integrated from 0.1 kHz to 10 MHz is 2.702 ps. The measured phase noise is −113.11 dBc/Hz at 1 MHz offset frequency.

Figure 9 shows the phase noise performance of the PLL output in fractional-N mode. The orange curve is composed of the actual measured values, which are then fitted to obtain the green curve. The start and stop frequencies, carrier frequency, and RMS jitter are likewise marked in the red rectangle. The actual output frequency of the PLL is 3.19 GHz and the test frequency is 99.84 MHz after 32 divisions. The RMS jitter integrated from 0.1 kHz to 10 MHz is 5.068 ps and the measured phase noise is −123.09 dBc/Hz at 1 MHz offset frequency.

The RMS jitter and power consumption in integer-N mode across the complete output frequency range are plotted in Figure 10. Within the operational range, the RMS jitter is consistently maintained below 4.5 ps, while power consumption remains below 7.5 mW. Performance comparison between the proposed PLL and other PLLs in recently reported work is summarized in

Table 2. Performance summary and comparison with analog PLL.

	This		[25] RFIC’18	[26] IEICE’20	[27] ISSCC’16	[28] Electronics’22	[29] TCAS-Ι’24
	Integ.-N	Frac.-N
Technology (nm)	12		14	180	65	28	14
Synth. Type	Frac.-N		Frac.-N	Integ.-N	Frac.-N	Integ.-N	Integ.-N
VCO Type	Single-ended ring		Ring	Ring	Ring	Ring	Ring
Freq. (GHz)	6.72		7	1.92	1.4	3	2.13
Area (mm2)	0.078		0.1	N/A	0.054	0.028	0.019
Power (mW)	6.4@5.76 GHz	3.4@3.19 GHz	36.3	17.4	8	4.6	1.19
RMS Jitter (ps)	2.702	5.068	0.982	2.61	2.8	N/A	5.67
FoM * (dB)	−223.3	−220.6	−224.6	−219.3	−222	N/A	−224.2

* $FoM=20\log \left(\frac{\sigma }{1\mathrm{s}}\right)+10\log \left(\frac{P}{1\mathrm{m}\mathrm{W}}\right)\sigma :\mathrm{r}\mathrm{m}\mathrm{s}\mathrm{j}\mathrm{i}\mathrm{t}\mathrm{t}\mathrm{e}\mathrm{r}, P:\mathrm{p}\mathrm{o}\mathrm{w}\mathrm{e}\mathrm{r}.$

. The proposed PLL demonstrates advantages in power consumption and area while maintaining low RMS jitter and high output frequency.

5. Conclusions

This work presents a compact, low-power, and low-jitter fractional-N PLL using single-ended Ring-VCO with novel resistive matrixes. A novel frequency control method in VCO with high-linearity $K_{VCO}$ is proposed, and the great application potential of single-ended Ring-VCOs in FinFETs is demonstrated. Implemented in a 12 nm FinFET process, the proposed PLL occupies only 0.078 mm². It achieves a 2.702 ps RMS jitter at 5.76 GHz, integrated from 0.1 kHz to 10 MHz, at a power consumption of 6.4 mW. Additionally, it maintains a power consumption below 7.5 mW and an RMS jitter below 4.5 ps over the entire output frequency range of 2.24–6.72 GHz. It can be further applied in mobile applications such as RF transceivers.