Search Results (28)

This work presents a fully integrated, two-stage, deep class-AB power amplifier (PA) operating at a center frequency of 60 GHz. High efficiency and suppression of third-order intermodulation products are targeted, achieving improved linearity compared to reported state-of-the-art designs. A current combining architecture is also employed to enhance the output power capability. The PA is designed in a 22 nm FD-SOI CMOS technology and is optimized through a complete schematic-to-layout design flow. Post-layout simulations indicate that the PA achieves a peak power-added efficiency (PAE) of 28%, a saturated output power ($P_{sat}$) of 20.2 dBm, and a maximum large-signal gain ($G_{max}$) of 19.6 dB at 60 GHz, evaluated at an operating temperature of 60 °C. The design maintains high linearity across the targeted output power range, exhibiting effective suppression of third-order intermodulation distortion (IMD3), which enhances its suitability for spectrally efficient modulation schemes. Full article

This paper presents a 0–360° phase shifter in 28 nm FD-SOI CMOS technology, suitable for radar applications and mm-wave wireless communication systems, which adopt high-efficiency transmitter architectures. It exploits a novel switching vector modulator based on a double-balanced Gilbert cell, which guarantees high-resolution phase control while exhibiting inherently high robustness against process and temperature variations. The phase control is performed by merely changing the currents in the Gilbert cells using digitally controlled current generators. The proposed phase shifter operates at 39 GHz and provides RMS phase and gain errors of 2.7–4.7° and 0.3–0.5 dB, respectively, while drawing 13 mA from a 1 V supply voltage. Full article

Low-pass filters with bandwidths larger than several GHz are required in many applications, such as anti-aliasing filters in high-speed ADCs and pulse-shaping filters in high-speed DACs. In highly integrated applications, low area occupation and power consumption are key specifications, so inductor-less implementations are to be preferred. Furthermore, full CMOS implementations provide an advantage in terms of technology availability and cost. In this paper, we present an inductor-less CMOS biquad stage based on the super source follower topology that provides an 8 GHz cutoff frequency and a low power consumption of 0.42 mW per pole, showing remarkable performance also in terms of bandwidth and dynamic range. The availability of two separate current sources allows independent tuning of natural frequency and quality factor. The stage can be implemented in two complementary ways, exploiting NMOS and PMOS input devices, respectively, thus simplifying cascadability. The two complementary biquads have been implemented in the STMicroelectronics FDSOI 28 nm CMOS process and extensively simulated and provide stable performance under PVT variations and mismatches. The area occupation is about 387.5 μm² per biquad, one of the lowest in the literature. The figures-of-merit are remarkable, as the filters achieve excellent power efficiency, very low area occupation, and good dynamic range. Full article

The non-ideality aspects of phase change memory (PCM) such as drift and resistance variability can pose significant obstacles in neuromorphic hardware implementations. A unique drift and variability compensation strategy is demonstrated and implemented in an FD-SOI SNN hardware unit composed of embedded phase change memories (ePCMs), current attenuators, and spiking neurons. The effect of drift and variability compensation on inference accuracy is tested on the MNIST dataset to show that our drift and variability mitigation strategy is effective in sustaining its accuracy over time. The variability is reduced by up to 5% while the drift coefficient is reduced by up to 57.8%. The drift is compensated and the SNN classification accuracy is sustained for up to 2 years with intrinsic control-free hardware that tracks the ePCM current over time and consumes less than 30 µW. The results are based on ePCM chip experimental data and pos-layout simulation of a test chip comprising the proposed circuit solution. Full article

Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in BNN accuracy. Our Monte Carlo simulations demonstrate that in an SRAM-based analog CIM implementing the VGG-9 BNN model, the classification accuracy on the CIFAR-10 image dataset is degraded to below 50% under process variations in a 28 nm FD-SOI technology. To overcome this problem, we present a variation-aware BNN framework. The proposed framework is developed for SRAM-based BNN CIMs since SRAM is most widely used as on-chip memory; however, it is easily extensible to BNN CIMs based on other memories. Our extensive experimental results demonstrate that under process variation of 28 nm FD-SOI, with an SRAM array size of $128\times 128$, our framework significantly enhances classification accuracies on both the MNIST hand-written digit dataset and the CIFAR-10 image dataset. Specifically, for the CONVNET BNN model on MNIST, accuracy improves from 60.24% to 92.33%, while for the VGG-9 BNN model on CIFAR-10, accuracy increases from 45.23% to 78.22%. Full article

Some applications, such as satellites, require ultralow power and high-radiation resilience. We developed a12Tsoft error-resilient SRAM cell, TA-Quatro, to deliver in-memory computing (IMC) for those applications. Based on our TA-Quatro cell, we implemented an IMC circuit to support binary weights and ternary activations in a single SRAM cell. Our simulation under 28 nm FD-SOI technology demonstrates that the TA-Quatro IMC circuit maintains good IMC stability at a scaled supply of 0.7Vand achieves ternary activation without needing analog-to-digital converters. These advancements significantly enhance the power efficiency of the proposed IMC circuit compared to state-of-the-art works. Full article

In this paper, we propose a cost-effective way to tune RF process technology to achieve well-optimized RF and mmWave performances/power/area by tweaking back-end-of-line (BEOL) configurations. This paper suggests that the most favorable altitude is that of an ultra-thick-metal (UTM) layer from the silicon substrate, and the effort also focuses on the calibration of the via height/pitch underneath the UTM to satisfy the least ohmic loss in the interface between the active and passive device components. We implemented a process optimization in a 28 nm fully depleted silicon-on-insulator (FD-SOI) process technology, and the results show performance enhancements on the inductor, achieving a 14.8% quality factor improvement and a 13.1% self-resonance frequency improvement. This paper also showcases how the process optimization boosts 29 GHz LNA performances, with a 31.8% gain in boosting and a 9.1% reduction in noise-figure. Full article

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm². Full article

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (P_DC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S₂₁-3 dB-BW [GHz])/(P_DC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature. Full article

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability. Full article

This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologies is introduced. Then, a set of simulation testbenches are defined in order to simulate and compare the considered topologies implemented in both a 130 nm technology and a 28 nm FDSOI CMOS process. Propagation delay, power consumption and power–delay product are evaluated for different values of the input common mode voltage, as a function of input differential amplitude, and in different supply voltage and temperature conditions. Monte Carlo simulations to evaluate the input offset voltage under mismatch variations are also provided. Simulation results show that the performances of the different comparator topologies are strongly dependent on the input common mode voltage, and that the best values for all the performance figures of merit are achieved by the comparator based on three-input NAND gates, with the only limitation being its non-rail-to-rail input common mode range (ICMR). The performances of the considered comparator topologies have also been simulated for different values of the supply voltage, ranging from 0.3 V to 1.2 V, showing that, even if standard-cell-based comparators can be operated at higher supply voltages by scaling their performances accordingly, the best values of the FoMs are achieved for $V_{DD}$ = 0.3 V. Full article

This paper presents the design and implementation of a 28 GHz phased array transceiver for 5G applications using 22 nm FD-SOI CMOS technology. The transceiver consists of a four-channel phased array receiver and transmitter, which employs phase shifting based on coarse and fine controls. The transceiver employs a zero-IF architecture, which is suitable for small footprints and low power requirements. The receiver achieves a 3.5 dB NF with a 1 dB compression point of −21 dBm and a gain of 13 dB. Full article

This paper presents a novel analog front-end for EMG sensor signal processing powered by 1 V. Such a low supply voltage requires specific design steps enabled using the 28 nm fully depleted silicon on insulator (FDSOI) technology from STMicroelectronics. An active ground circuit is implemented to keep the input common-mode voltage close to the analog ground and to minimize external interference. The amplifier circuit comprises an input instrumentation amplifier (INA) and a programmable-gain amplifier (PGA). Both are implemented in a fully differential topology. The actual performance of the circuit is analyzed using the corner and Monte Carlo analyses that comprise fifth-hundred samples for the global and local process variations. The proposed circuit achieves a high common-mode rejection ratio (CMRR) of 105.5 dB and a high input impedance of 11 G$\mathrm{\Omega }$ with a chip area of 0.09 mm${}^2$. Full article

Single-event transient (SET)-induced soft errors are becoming a more significant threat to the reliability of electronic systems in space, especially for advanced technologies. The SET pulse width, which is vulnerable to SET propagation, is a critical parameter for developing SET mitigation techniques. This paper investigates the pulse-broadening effect in the process of SET propagation in logic circuits and the SET-sensitive region distribution in the layout using the pulsed-laser mapping technique in logic circuits implemented with 28 nm Ultra-Thin Body and BOX (UTBB) FDSOI technology. The experiments were carried out at the Naval Research Laboratory (NRL) to measure the SET-induced errors and map the SET-sensitive region distribution at various clock frequencies and laser energy levels. The results illustrate that the number of errors increases with the clock frequency and energy for combinational logic circuits and that the flip-flop SEU rate is less sensitive to clock frequency. The SET pulse-broadening effect was also observed using SET mapping for an OR gate chain at different laser energy levels. In addition, the simulation results revealed the mechanism of the SET pulse-broadening effect in an OR gate chain. Full article

In Message Passing (MP) decoding of Low-Density Parity Check (LDPC) codes, extrinsic information is exchanged between Check Nodes (CNs) and Variable Nodes (VNs). In a practical implementation, this information exchange is limited by quantization using only a small number of bits. In recent investigations, a novel class of Finite Alphabet Message Passing (FA-MP) decoders are designed to maximize the Mutual Information (MI) using only a small number of bits per message (e.g., 3 or 4 bits) with a communication performance close to high-precision Belief Propagation (BP) decoding. In contrast to the conventional BP decoder, operations are given as discrete-input discrete-output mappings which can be described by multidimensional LUTs (mLUTs). A common approach to avoid exponential increases in the size of mLUTs with the node degree is given by the sequential LUT (sLUT) design approach, i.e., by using a sequence of two-dimensional Lookup-Tables (LUTs) for the design, leading to a slight performance degradation. Recently, approaches such as Reconstruction-Computation-Quantization (RCQ) and Mutual Information-Maximizing Quantized Belief Propagation (MIM-QBP) have been proposed to avoid the complexity drawback of using mLUTs by using pre-designed functions that require calculations over a computational domain. It has been shown that these calculations are able to represent the mLUT mapping exactly by executing computations with infinite precision over real numbers. Based on the framework of MIM-QBP and RCQ, the Minimum-Integer Computation (MIC) decoder design generates low-bit integer computations that are derived from the Log-Likelihood Ratio (LLR) separation property of the information maximizing quantizer to replace the mLUT mappings either exactly or approximately. We derive a novel criterion for the bit resolution that is required to represent the mLUT mappings exactly. Furthermore, we show that our MIC decoder has exactly the communication performance of the corresponding mLUT decoder, but with much lower implementation complexity. We also perform an objective comparison between the state-of-the-art Min-Sum (MS) and the FA-MP decoder implementations for throughput towards 1 Tb/s in a state-of-the-art 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology. Furthermore, we demonstrate that our new MIC decoder implementation outperforms previous FA-MP decoders and MS decoders in terms of reduced routing complexity, area efficiency and energy efficiency. Full article