Research on Key Technologies for Hardware Acceleration

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 June 2024) | Viewed by 275

Special Issue Editor

Institute for Artificial Intelligence, School of Integrated Circuits, Peking University, Beijing 100871, China
Interests: FPGA hardware system; deep learning acceleration; energy-efficient VLSI design
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

With increasingly demand for more computing power, data storage, and memory bandwidth by artificial intelligence (AI), current general-purpose processors are suffering from low latency and low energy efficiency for AI applications due to the unsuitable architecture or limited memory access bandwidth (e.g., memory wall bottleneck). To meet the requirements of modern intelligent systems, customized hardware accelerators are emerging for different tasks by integrating cross-level optimizations and innovations of algorithm, compilation, architecture, and circuit designs. The aim of this Special Issue is to focus on the key technologies including reconfigurable FPGAs, 2.5D/3D chiplets, and in-/near-memory computing for hardware acceleration.

Submissions for this Special Issue on “Research on Key Technologies for Hardware Acceleration” are welcome on any scope related, but not limited, to the following areas:

  • Co-optimization of hardware-friendly emerging AI algorithms, including pruning, quantization, etc.
  • Reconfigurable hardware accelerators on FPGA for intelligent vision tasks.
  • The ultra-low power ASIC accelerator for voice applications.
  • The methodologies of compilation and mapping to AI hardware accelerators.
  • The hardware accelerators based on in-/near-memory computing architecture.
  • The interconnection and parallel structure of 2.5D chiplets or 3D stacked chips.

Dr. Yufei Ma
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • hardware accelerators
  • reconfigurable FPGA acceleration
  • in-/near-memory computing
  • 2.5D/3D integrated chiplets

Published Papers

There is no accepted submissions to this special issue at this moment.
Back to TopTop