Search Results (636)

A monolithic digital Silicon Photomultiplier (SiPM) featuring 1024 microcells with a 30-micrometer pitch and a 50% fill factor has been designed in a 110-nanometer CMOS image sensor technology. The device under consideration integrates both SPAD sensors and front-end electronics in the same substrate. It can count up to 1024 photons in less than 22 ns, while assigning timestamps to the first and last detected photons with a time resolution of less than 100 ps. A parallel counter structure combined with a fast adder tree provides photon counting in digital form with low latency, whereas a carefully balanced fast NAND tree ensures a fixed-pattern time uncertainty not exceeding 26 ps. The architecture incorporates in-pixel memory for individual cell disabling and configurable thresholding on the timing signal for noise mitigation. In order to optimize the fill factor, a part of the electronics is placed outside the array, while the most sensitive elements of the timing and counting circuits are laid out close to the sensor, in the SPAD array. A serial readout is employed to provide a single output connection per SiPM, thereby simplifying system integration. Full article

Artificial intelligence (AI) is propelling space exploration into a new era. Synergistic breakthroughs in chip design and high-speed communications have facilitated the large-scale deployment of on-board satellite computing. Assessing the reliability of these systems via fault injection (FI) remains difficult due to the massive computational demands of Convolutional Neural Networks (CNNs) and the complex architectures of Neural Processing Units (NPUs). This research presents a high-precision, efficient FI methodology specifically tailored for NPU architectures to optimize both evaluation accuracy and execution efficiency. Implementing a hierarchical injection strategy to identify fault-sensitive layers minimizes computational overhead while ensuring statistical validity. Experimental results on the ResNet-50 network demonstrate that the proposed methodology constrains accuracy degradation to less than 0.1% while achieving a 60.80% reduction in total execution time. Full article

As emerging nonvolatile memory devices, ferroelectric field-effect transistors (FeFETs) have attracted significant attention for memory applications. However, due to the stochastic nature of fabrication processes and material properties, FeFETs exhibit pronounced device-to-device (DTD) variations, leading to threshold voltage dispersion and inconsistency in memory window (MW), which severely constrain array-level performance and reliability. In this study, a compact model-based variability analysis methodology for FeFETs has been proposed. Specifically, the Preisach ferroelectric (FE) hysteresis model was combined with the MIT Virtual Source (MVS) physical compact model to establish a macro-model for FeFETs, and statistical simulations were performed to evaluate device-level variations. Using the proposed framework, how fluctuations in two key FE parameters, film thickness (t_FE) and coercive field (E_C), affect FeFET transfer characteristics, threshold voltage (V_TH), and MW was systematically investigated. Monte Carlo (MC) simulations were further conducted to quantify the distribution width and statistical features of V_TH under different variability scenarios. The results indicate that random fluctuations in process-related parameters broaden the FeFET I_d-V_g characteristics, induce shifts in high/low threshold voltages, and cause MW variations. Moreover, when t_FE and E_C fluctuate simultaneously, the dispersions of V_TH and MW become significantly larger than those induced by a single-parameter fluctuation. The proposed compact-modeling framework and variability analysis approach enables the efficient evaluation of parameter tolerance and performance margin in FeFET arrays, providing guidance for storage-array design. Full article

In this study, an ultra-low-voltage operational transconductance amplifier (OTA) operating from a 0.3 V supply, designed in a 45 nm CMOS process, is presented. To overcome the severe headroom constraints, the design employs a bulk-driven differential input stage combined with a current-reuse strategy, effectively enhancing transconductance while operating all transistors in the subthreshold region. This approach enables a rail-to-rail input common-mode range. A multipath Miller zero cancellation compensation technique ensures stability. The resulting OTA achieves an open-loop gain of 44.2 dB and a remarkable common-mode rejection ratio (CMRR) of 87.5 dB, all while consuming 23.3 nW of power. With a gain–bandwidth product of 9.9 kHz, a power supply rejection ratio (PSRR) of 41.1 dB, and an input noise of 1.0 μV/√Hz, this design is highly suitable for energy-constrained, low-frequency applications such as biomedical sensor interfaces and IoT nodes. Full article

Practical development of terahertz technology requires higher power radiation sources. The sheet electron beam vacuum device is an effective solution of increasing the output power of terahertz radiation sources, but faces the difficulty of stable transmission of the beam. In this paper, a compact quadrupole permanent magnet (QPM) focusing system for terahertz sheet beam devices is designed, and a practical focusing system is constructed into a prototype for beam transmission verification. In the experiment, 16 pieces of high-performance NdFeB permanent magnets were adopted with a total weight of about 10 kg. The magnetic field test of the system was carried out and the results show that the system can provide a uniform high-intensity magnetic field of over 0.95 T within an axial length of 20 mm. With the tested QPM magnetic field configuration, PIC simulation of the sheet beam transmission was implemented, indicating that a sheet electron beam with a 20 kV voltage and 15 mA current can travel through a beam tunnel of a cross-section 0.1 mm × 0.05 mm, with a transmission ratio of 98.5%. Full article

This paper presents a compact floating memtranstor (MT) emulator, a memory element characterized by a direct φ–q relationship, realized without analog multipliers or complex circuitry. The proposed design employs only two active blocks—a voltage differential transconductance amplifier (VDTA) and a voltage differential current conveyor (VDCC)—along with three grounded capacitors and a single grounded electronically tunable resistor. The emulator accurately reproduces the fundamental φ–q dynamics, exhibiting origin-crossing pinched hysteresis loops under sinusoidal excitation, and operates at a low supply voltage of ±0.9 V. Electronic tunability is achieved via bias-controlled transconductance modulation, enabling flexible adaptation across excitation frequencies and operating conditions. Validation is performed through analytical modeling, Monte Carlo simulations, temperature sensitivity analysis, and full LTspice post-layout simulations using a 180 nm CMOS process. The full-custom layout occupies 2529.49 μm², with robust performance confirmed under parasitic and process variations. Adaptive learning simulations demonstrate the emulator’s artificial synaptic plasticity, highlighting its suitability for neuromorphic computing, chaos-based circuits, and nonlinear dynamical systems. The compact, low-power, and multiplier-free architecture establishes the proposed MT emulator as a practical platform for emerging analog memory-centric applications. To validate the feasibility of the proposed solution, experimental tests are performed using commercially available components. Full article

Electromagnetic compatibility (EMC) diagnostics for high-density through-silicon via (TSV)-based chips face significant challenges due to complex three-dimensional electromagnetic coupling and inefficient source reconstruction workflows. This paper proposes a universal contribution-driven dipole preprocessing technique tailored for dipole array-based source reconstruction methods, addressing the critical efficiency-accuracy trade-off inherent in traditional approaches. The core innovation is an influence factor-based evaluation-elimination mechanism that extracts effective dipole components aligned with the structural characteristics of TSV-based chips and multilayer printed circuit boards, while eliminating redundant dipoles independently of the downstream source reconstruction algorithm. Validation on a multilayer PCB (1 GHz) and a TSV-based chip (4 GHz) demonstrates that the technique maintains high reconstruction accuracy, with error increase limited to ≤0.2% for the simulated PCB and ≤0.05% for the physically measured TSV-based chip. Computational time is reduced by 28–61% for the PCB and 20–28% for the TSV chip compared to traditional source reconstruction without preprocessing. For TSV-based chips exhibiting complex electromagnetic behavior, the technique delivers consistent performance across different dipole configurations, providing a fast, robust, and universal EMC diagnostic tool for high-density electronic devices. Full article

Based on the electron cyclotron maser instability, gyrotrons are capable of generating high-power electromagnetic vortex waves. In conventional axisymmetric configurations, the electron beam typically lifts the azimuthal degeneracy between co-rotating and counter-rotating modes, leading to a state of intense mutual suppression. This study elucidates a fundamental transition from such competitive dynamics to a stable cooperative coexistence, driven by symmetry-breaking perturbations. Using a time-dependent self-consistent interaction theory, we investigate the intermodal dynamics of the counter-rotating ${\mathrm{T}\mathrm{E}}_{6,2}$ mode pair in a terahertz gyrotron. Our results reveal that the azimuthal intermodal phase beating dictates a reciprocal energy exchange that ensures single-mode dominance. However, electron beam misalignment introduces a significant azimuthal non-uniformity in the coupling strength. This non-uniformity effectively neutralizes the competitive disparity between the two modes. At a critical offset, the system undergoes a “territorial division,” where the orthogonal vortex modes spatially segregate by dominating distinct azimuthal segments of the annular beam. This spatial segregation eliminates nonlinear cross-suppression, allowing for the stable coexistence of both rotational states. These findings offer a new perspective on multi-mode interactions in non-ideal systems and establish a robust theoretical framework for the active manipulation of vortex waves in high-performance THz radiation sources. Full article

An enhanced dynamic bias comparator with a reference-compensated offset calibration technique is implemented in a 180 nm CMOS process. In order to reduce the delay time of the comparator, an enhanced structure is used. To reduce the power consumption, a dynamic bias technique is applied to the comparator. A novel reference-compensated offset calibration technique is introduced to achieve offset calibration. Spectre simulation results indicate that the proposed comparator achieves a delay time of 190.3 ps and an energy consumption of 324.2 fJ/comparison under operating conditions of 150 MHz and an input differential amplitude of 0.1 V, compared to a delay time of 235.5 ps and an energy consumption of 636.6 fJ/comparison for the conventional comparator. Furthermore, the application of a reference-compensated offset calibration technique facilitates a reduction in the offset voltage of the comparator from 18.1 mV to 6.3 mV. Full article

This paper proposes a novel solution to suppress backward wave oscillation (BWO) in high-order mode (HOM) sheet beam (SB) slow-wave structures (SWSs) and designs an isolator between cavities based on a Bragg resonator. This method can cut-off the backward wave signal path without interrupting the operating signal path, thereby eliminating BWO while maintaining high circuit gain. Simulation results show that the S21 parameter of the isolator is less than −20 dB from 175 GHz to 228 GHz. To verify the method’s performance, particle-in-cell (PIC) simulation was conducted based on a HOM SB SWS—a T-slot coupled-cavity (TSCC) SWS. Results indicate that this method can effectively suppress BWO and shows significant improvement in gain and output power compared to traditional methods such as sever or lossy loading. Under operating conditions of 34.4 kV and 0.35 A, the circuit achieves a maximum output power of 527 W at 216 GHz, a maximum gain of 36.39 dB at 214.4 GHz, and a bandwidth of 3 GHz where the output power exceeds 300 W. Full article

The growing demand for electric vehicles, renewable energy systems, and portable electronics has led to the widespread adoption of power conversion systems. Although advanced structures like the superjunction MOSFET have prolonged the viability of silicon in power applications, maintaining its dominance through cost efficiency, Si-based technology is ultimately constrained by its intrinsic limitations in critical electric fields. To address these constraints, research into wide bandgap semiconductors aims to minimize system footprint while maximizing efficiency. This study reviews the semiconductor landscape, demonstrating why Gallium Nitride (GaN) has emerged as the most promising technology for next-generation power applications. With a critical electric field of $3.75\mathrm{MV}/\mathrm{cm}$ ($12.5\times$ higher than Si), GaN facilitates power devices with lower conduction loss and higher frequency capability when compared to their Si counterpart. Furthermore, this paper surveys the GaN ecosystem, ranging from device modeling and packaging to monolithic ICs and switching converter implementations based on discrete transistors. While existing literature primarily focuses on discrete devices, this work addresses the critical gap regarding GaN monolithic integration. It synthesizes key challenges and achievements in the design of GaN integrated circuits, providing a comprehensive review that spans semiconductor technology, monolithic circuit architectures, and system-level applications. Reported data demonstrate monolithic stages reaching $30\mathrm{m}\Omega$ and $25\mathrm{MHz}$, exceeding Si performance limits. Additionally, the study reports on high-density hybrid implementations, such as a space-grade POL converter achieving $123.3\mathrm{kW}/\mathrm{L}$ with $90.9\%$ efficiency. Full article

Laser pulses are essential in various scientific fields, yet existing laser diode drivers offer limited adjustability. This paper presents a digitally adjustable subnanosecond gain-switched laser diode driver, a first one with step sizes of the control being in the single-digit picosecond range. The proposed circuit differentially drives the laser diode (LD) using two high-current gate drivers whose relative delay is digitally adjusted by a dual programmable delay line. Pulse width is defined by the delay difference between the two channels, enabling fine control without the need for high-speed semiconductor switching. Experimental results demonstrate stable optical pulse generation with widths tunable from $350ps$ to $2.8ns$ in $9ps$ increments and repetition rates exceeding $150MHz$. Timing jitter remains below $15ps$, and amplitude variation is below 1% across the tested operating conditions. The proposed solution provides a compact, low-cost, and highly adjustable platform for applications that require precise timing and pulse-width control, such as time-resolved measurements, range finding, and nonlinear optical excitation. Full article

Division remains one of the most computationally demanding operations in digital arithmetic. Traditional algorithms, such as restoring, non-restoring, and SRT (Sweeney–Robertson–Tocher) division, are limited by sequential dependencies that reduce throughput in hardware implementations. To overcome these constraints, this work proposes a pipelined integer divider architecture that employs precomputed divisor multiples and comparator-based logic to eliminate the need for full binary adders in the quotient selection stages. The proposed design consists of a three-stage pipeline, where each stage compares the shifted partial remainder with stored multiples of the divisor (B, 2B, 3B) to generate two quotient bits per clock cycle. This approach achieves a 2× reduction in the number of computation stages compared with conventional radix-2 dividers and ensures continuous operation after an initial pipeline latency. The architecture was described in Verilog hardware description language (HDL) and implemented on a Xilinx Artix-7 (XC7A100T-1CSG324C) field-programmable gate array (FPGA) using the Xilinx ISE Design Suite 14.4. Post-synthesis simulation confirmed correct quotient and remainder generation with a maximum operating frequency of 208 MHz. The implementation occupied less than 0.3% the look-up table (LUT) resources, achieving over a twofold performance improvement compared with a non-pipelined baseline. These results demonstrate that the proposed divider provides an efficient trade-off between speed and hardware cost, making it suitable for digital signal processing and embedded computation systems. Full article

The rapid evolution of modern vehicles into intelligent and interconnected systems presents new complexities in both functional safety and cybersecurity. In this context, ensuring the reliability and integrity of critical sensor data, such as wheel speed inputs for anti-lock brake systems (ABS), is essential. Effective detection of wheel speed sensor faults not only improves functional safety, but also plays a vital role in keeping system resilience against potential cyber–physical threats. Although data-driven approaches have gained popularity for system development due to their ability to extract meaningful patterns from historical data, a major limitation is the lack of diverse and representative faulty datasets. This study proposes a novel dual learning model, based on Temporal Convolutional Networks (TCN), designed to accurately distinguish between normal and faulty wheel speed sensor behavior within a hardware-in-the-loop (HIL) simulation platform implemented on an FPGA. To address dataset limitations, a TruckSim–MATLAB/Simulink co-simulation environment is used to generate realistic datasets under normal operation and eight representative fault scenarios, yielding up to 5000 labeled sequences (balanced between normal and faulty behaviors) at a sampling rate of 60 Hz. Two TCN models are trained independently to learn normal and faulty dynamics, and fault decisions are made by comparing the reconstruction errors (MSE and MAE) of both models, thus avoiding manually tuned thresholds. On a test set of 1000 sequences (500 normal and 500 faulty) from the 5000 sample configuration, the proposed dual TCN framework achieves a detection accuracy of 97.8%, a precision of 96.5%, a recall of 98.2%, and an F1-score of 97.3%, outperforming a single TCN baseline, which achieves 91.4% accuracy and an 88.9% F1-score. The complete dual TCN architecture is implemented on a Xilinx ZCU102 FPGA evaluation kit (AMD, Santa Clara, CA, USA), while supporting real-time inference in the HIL loop. These results demonstrate that the proposed approach provides accurate, low-latency fault detection suitable for safety-critical ABS applications and contributes to improving both functional safety and cyber-resilience of braking systems. Full article

With continued transistor scaling and increasing interconnect density in very large-scale integration (VLSI) circuits, the parasitic capacitance of interconnect has become a major contributor to circuit delay and signal integrity degradation. Fast and accurate parasitic capacitance extraction is therefore essential in the back-end-of-line (BEOL) stage. Currently, 2.5D parasitic capacitance extraction flow based on the pattern matching method is widely used by commercial tools, which still suffer from lengthy pattern library construction, cross-section preprocessing, pattern mismatch, and poor accuracy for small capacitance extraction. To overcome these limitations, this work proposes an end-to-end parasitic capacitance extraction workflow, named residual multilayer perceptron interconnect parasitic capacitance extraction (RMLP-Cap), which leverages a residual multilayer perceptron (ResMLP) to enhance traditional workflow. RMLP-Cap integrates parasitic extraction (PEX) window acquisition, pattern definition, feature extraction, dataset generation, ResMLP model training, and capacitance aggregation into a unified flow. Experimental results show that RMLP-Cap can automatically define and model complex 2D patterns with 100% matching accuracy. Compared with a field solver based on the boundary element method (BEM), the ResMLP model achieves an average relative error below 0.9%, a standard deviation under 0.2%, and less than 0.5% error for small capacitances, while providing a 900% speed improvement for extraction speed. Full article