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Micromachines
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Advances in Resistive Switching Memory Devices
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Advances in Resistive Switching Memory Devices

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A：Physics".

Deadline for manuscript submissions: closed (30 July 2021) | Viewed by 11327

Special Issue Editor

Prof. Dr. Hee-Dong Kim

E-Mail Website
Guest Editor
Innovative nanoTechnology Laboratory, Department of Electrical Engineering, Sejong University, Seoul, Republic of Korea
Interests: semiconductor memory; semiconductor sensor; LED device; electronic materials
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear colleagues,

Next-generation memory devices have recently become an active area of research, prompted by the physical limitations of charge trap-based non-volatile memory (NVM) devices. Among them, resistive switching memory (RRAM) devices have been considered as the most promising NVM device since the fourth fundamental passive circuit element was postulated in 1971, and can store two distinctive resistance states, namely a high-resistance state (HRS) and low-resistance state (LRS). Ever since, a variety of resistive switching devices have been demonstrated with the hope of finding the next-generation NVM devices offering the advantage of being highly scalable: 4F2 in a single layer, which could be further reduced to 4F2/n, where F is a half of the pitch in a crossbar arrangement and n is the number of stacks of physical layers of resistive switching devices. However, these devices incur several severe issues for commercialization that result in frequent read/write errors and unnecessary power consumption. To fix the issues that affect the performance of RRAM devices, researchers are proposing various approaches regarding new materials, designs, and properties. Hence, this Special Issue will be considering all RRAM device-related outcomes in the form of both original research papers and review papers and contribute to advancements in this research area by serving as a useful resource for researchers.

Prof. Dr. Hee-Dong Kim
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • resistive switching memory
  • RRAM
  • selector device
  • array circuit
  • RRAM-based application devices

Published Papers (3 papers)

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Research

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24 pages, 5480 KiB  
Article
Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)
by Furqan Zahoor, Fawnizu Azmadi Hussin, Farooq Ahmad Khanday, Mohamad Radzi Ahmad and Illani Mohd Nawi
Micromachines 2021, 12(11), 1288; https://doi.org/10.3390/mi12111288 - 21 Oct 2021
Cited by 12 | Viewed by 2836
Abstract
Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible [...] Read more.
Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder–subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility. Full article
(This article belongs to the Special Issue Advances in Resistive Switching Memory Devices)
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18 pages, 11487 KiB  
Article
Memristor-CMOS Hybrid Neuron Circuit with Nonideal-Effect Correction Related to Parasitic Resistance for Binary-Memristor-Crossbar Neural Networks
by Tien Van Nguyen, Jiyong An and Kyeong-Sik Min
Micromachines 2021, 12(7), 791; https://doi.org/10.3390/mi12070791 - 1 Jul 2021
Cited by 16 | Viewed by 3263
Abstract
Voltages and currents in a memristor crossbar can be significantly affected due to nonideal effects such as parasitic source, line, and neuron resistance. These nonideal effects related to the parasitic resistance can cause the degradation of the neural network’s performance realized with the [...] Read more.
Voltages and currents in a memristor crossbar can be significantly affected due to nonideal effects such as parasitic source, line, and neuron resistance. These nonideal effects related to the parasitic resistance can cause the degradation of the neural network’s performance realized with the nonideal memristor crossbar. To avoid performance degradation due to the parasitic-resistance-related nonideal effects, adaptive training methods were proposed previously. However, the complicated training algorithm could add a heavy computational burden to the neural network hardware. Especially, the hardware and algorithmic burden can be more serious for edge intelligence applications such as Internet of Things (IoT) sensors. In this paper, a memristor-CMOS hybrid neuron circuit is proposed for compensating the parasitic-resistance-related nonideal effects during not the training phase but the inference one, where the complicated adaptive training is not needed. Moreover, unlike the previous linear correction method performed by the external hardware, the proposed correction circuit can be included in the memristor crossbar to minimize the power and hardware overheads for compensating the nonideal effects. The proposed correction circuit has been verified to be able to restore the degradation of source and output voltages in the nonideal crossbar. For the source voltage, the average percentage error of the uncompensated crossbar is as large as 36.7%. If the correction circuit is used, the percentage error in the source voltage can be reduced from 36.7% to 7.5%. For the output voltage, the average percentage error of the uncompensated crossbar is as large as 65.2%. The correction circuit can improve the percentage error in the output voltage from 65.2% to 8.6%. Almost the percentage error can be reduced to ~1/7 if the correction circuit is used. The nonideal memristor crossbar with the correction circuit has been tested for MNIST and CIFAR-10 datasets in this paper. For MNIST, the uncompensated and compensated crossbars indicate the recognition rate of 90.4% and 95.1%, respectively, compared to 95.5% of the ideal crossbar. For CIFAR-10, the nonideal crossbars without and with the nonideal-effect correction show the rate of 85.3% and 88.1%, respectively, compared to the ideal crossbar achieving the rate as large as 88.9%. Full article
(This article belongs to the Special Issue Advances in Resistive Switching Memory Devices)
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Review

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24 pages, 8838 KiB  
Review
Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes
by Donglin Zhang, Bo Peng, Yulin Zhao, Zhongze Han, Qiao Hu, Xuanzhi Liu, Yongkang Han, Honghu Yang, Jinhui Cheng, Qingting Ding, Haijun Jiang, Jianguo Yang and Hangbing Lv
Micromachines 2021, 12(8), 913; https://doi.org/10.3390/mi12080913 - 30 Jul 2021
Cited by 6 | Viewed by 4149
Abstract
Resistive random access memory (RRAM) is one of the most promising new nonvolatile memories because of its excellent properties. Moreover, due to fast read speed and low work voltage, it is suitable for seldom-write frequent-read applications. However, as technology nodes shrink, RRAM faces [...] Read more.
Resistive random access memory (RRAM) is one of the most promising new nonvolatile memories because of its excellent properties. Moreover, due to fast read speed and low work voltage, it is suitable for seldom-write frequent-read applications. However, as technology nodes shrink, RRAM faces many issues, which can significantly degrade RRAM performance. Therefore, it is necessary to optimize the sensing schemes to improve the application range of RRAM. In this paper, the issues faced by RRAM in advanced technology nodes are summarized. Then, the advantages and weaknesses in the novel design and optimization methodologies of sensing schemes are introduced in detail from three aspects, the reference schemes, sensing amplifier schemes, and bit line (BL)-enhancing schemes, according to the development of technology in especially recent years, which can be the reference for designing the sensing schemes. Moreover, the waveforms and results of each method are illustrated to make the design easy to understand. With the development of technology, the sensing schemes of RRAM become higher speed and resolution, low power consumption, and are applied at advanced technology nodes and low working voltage. Now, the most advanced nodes the RRAM applied is 14 nm node, the lowest working voltage can reach 0.32 V, and the shortest access time can be only a few nanoseconds. Full article
(This article belongs to the Special Issue Advances in Resistive Switching Memory Devices)
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