Network-on-Chip and Application
A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".
Deadline for manuscript submissions: closed (15 November 2021) | Viewed by 709
Special Issue Editors
Interests: system-on-a-chip; network-on-a-chip; CPU–GPU-based SoCs; tools and applications
Special Issue Information
Dear Colleagues,
Advancement in computing system architectures, coupled with the Moore’s Law and Dennard scaling, has enabled system-on-a-chip (SoC) architects to accommodate hundreds of processing, memory, and other cores on a single chip. This complex integration has introduced many challenges in the form of low-power SoC implementations, and the spread of applications and computational paradigms including multi- and many-core SoCs, chip multi-processors (CMPs), and heterogeneous computing. The network-on-a-chip (NoC) paradigm is based on packet-switched routing mechanism. It can address most of the on-chip communication problems, including performance limitations of long interconnects and the integration of many heterogeneous cores on a chip. NoC has become the most common interconnection structure to integrate FPGAs, many-core SoCs, and hybrid single-chip systems. However, NoC performance, hardware cost, and power consumption depend on its various parameters, such as topology, the number and depth of virtual channels, routing, and flow control mechanisms.
The goal of this Special Issue is to assemble and put forward innovative ideas and solutions related to NoC architecture, design, implementation, and applications. Moreover, the NoCs for FPGAs, multi/many-core SoCs, and heterogeneous systems will also be explored. Researchers and developers are invited to submit their unpublished network-on-a-chip-related work. The extended versions of published papers in conferences, symposiums or workshops are also welcomed as long as they have substantial (> 40%) additional material.
Prof. Dr. Gul N. Khan
Dr. Anita Tino
Guest Editors
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Keywords
- Network-on-a-chip architecture and Implementation
- NoC topologies, routing, and flow control
- Modeling, simulation, and synthesis of NoCs
- Fault tolerance and reliability of networks-on-chip
- NoCs for FPGAs, CMP, MPSoC, and heterogeneous systems
- Mapping of applications to NoCs and real NoC case-studies
- Emerging applications (deep learning) and NoC technologies (optical, wireless)
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