Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
3.6
1.6
Journals
JLPEA
Special Issues
Ultra-Low Power VLSI Design for Emerging Applications
share announcement

Ultra-Low Power VLSI Design for Emerging Applications

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (31 August 2016) | Viewed by 42300

Special Issue Editors

Dr. Tony Tae-Hyoung Kim

E-Mail Website
Guest Editor
VIRTUS IC Design Center of Excellence, School of EEE, Nanyang Technological University, Singapore
Interests: ultra-low power; ultra-low voltage integrated circuits; low power memory circuits; low power circuits for 3D ICs; energy-efficient circuits and systems
Dr. Xin Liu

E-Mail Website
Guest Editor
Institute of Microelectronics, A*STAR, Singapore
Interests: energy-efficient digital signal processor architecture; hardware-oriented algorithm development for on-chip signal processing; cognitive wireless radio baseband; advanced 2.5D/3D TSV/TSI design
Dr. Jun Zhou

E-Mail Website
Guest Editor
Institute of Microelectronics, A*STAR, Singapore
Interests: ultra-low power digital circuits; energy efficient digital signal processors; variation-resilient digital circuits; circuit design for emerging technologies (e.g. spintronic devices, TSI/TSV)

Special Issue Information

Dear Colleagues,

Power consumption is a top-most design parameter in numerous circuits and systems. It is particularly significant in nanoscale CMOS technology where scaling of power is extremely challenging. Low voltage operation has been widely explored to reduce power consumption. However, supply voltage scaling alone cannot meet the power consumption requirement of many emerging applications. Therefore, various innovative design techniques for ultra-low power consumption need to be developed.

This Special Issue will present the most recent advancements in ultra-low power VLSI design for emerging applications such as Internet of Things, biomedical applications, and mobile electronics.

Dr. Tony Tae-Hyoung Kim
Dr. Jun Zhou
Dr. Xin Liu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Low power VLSI
  • Low power memory circuits
  • Low power digital circuits
  • Low power VLSI for emerging applications
  • Ultra-low voltage VLSI

Benefits of Publishing in a Special Issue

  • Ease of navigation: Grouping papers by topic helps scholars navigate broad scope journals more efficiently.
  • Greater discoverability: Special Issues support the reach and impact of scientific research. Articles in Special Issues are more discoverable and cited more frequently.
  • Expansion of research network: Special Issues facilitate connections among authors, fostering scientific collaborations.
  • External promotion: Articles in Special Issues are often promoted through the journal's social media, increasing their visibility.
  • e-Book format: Special Issues with more than 10 articles can be published as dedicated e-books, ensuring wide and rapid dissemination.

Further information on MDPI's Special Issue polices can be found here.

Published Papers (5 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

2210 KiB  
Article
The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology
by Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass and Chia Yee Ooi
J. Low Power Electron. Appl. 2017, 7(2), 7; https://doi.org/10.3390/jlpea7020007 - 28 Apr 2017
Cited by 3 | Viewed by 8451
Abstract
Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused by test patterns [...] Read more.
Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption in the scan chain but also introduce spurious switching activities in the combinational logic. In this work, a new low power gating scan cell for scan based designs has been proposed in order to reduce power consumption in the scan chain as well as the combinational part during shifting. We have modified the conventional scan cell and augmented it with state preserving and gating logic that enables an average power reduction in combinational logic during shift mode. The new scan cell mitigates the number of transitions during shift and capture cycles. Thus, it reduces the average power consumption inside the scan cell and as a result the scan chain during scan shifting with a low impact on peak power during the capture cycle. Furthermore, due to introducing a new shorter shift path, improvements are observed in terms of propagation delay and power consumption in the scan chain during shifting. This leads to higher feasible shift frequency whereby the shift frequency is limited by the maximum power budget and hence results in reducing the test application time. The post-layout spice simulation results show a 7.21% reduction in total power consumption, an average 12.25% reduction of shift power consumption, and a 50.7% improvement in the clock (CLK)-to-shift propagation delay over the conventional scan cell in Synopsys 32/28 nm standard CMOS technology. Full article
(This article belongs to the Special Issue Ultra-Low Power VLSI Design for Emerging Applications)
►▼ Show Figures

Figure 1

2342 KiB  
Article
A 4.1 W/mm2 Hybrid Inductive/Capacitive Converter for 2–140 mA-DVS Load under Inductor
by Sudhir Kudva, Saurabh Chaubey and Ramesh Harjani
J. Low Power Electron. Appl. 2016, 6(3), 18; https://doi.org/10.3390/jlpea6030018 - 9 Sep 2016
Cited by 1 | Viewed by 7658
Abstract
This work presents a fully integrated hybrid inductive/capacitive converter maintaining high efficiency for a load range of 2 mA to 140 mA (70×) suitable for the dynamic voltage scaling (DVS) based loads. This high efficiency is achieved by using an inductive converter for [...] Read more.
This work presents a fully integrated hybrid inductive/capacitive converter maintaining high efficiency for a load range of 2 mA to 140 mA (70×) suitable for the dynamic voltage scaling (DVS) based loads. This high efficiency is achieved by using an inductive converter for higher loads (15–140 mA, 0.50–0.9 V) and a capacitive converter for lighter loads (2–5 mA, 0.40–0.55 V) with a 50 mV hysteresis margin. A digital state machine activates the appropriate converter based on the power efficiency and enables the converter hand-over. The functional feasibility of implementing digital circuits as representative loads under the inductor is shown thereby increasing the peak converter power density from 0.387 W/mm2 to 4.1 W/mm2 with only a minor hit on the efficiency. The maximum measured efficiency is achieved in inductive mode of operation and decreases from 76.4% to 71% when digital circuits are present under the inductor. The design was fabricated in IBM’s 32 nm SOI technology. Full article
(This article belongs to the Special Issue Ultra-Low Power VLSI Design for Emerging Applications)
►▼ Show Figures

Figure 1

5229 KiB  
Article
A Fully Integrated 2:1 Self-Oscillating Switched-Capacitor DC–DC Converter in 28 nm UTBB FD-SOI
by Matthew Turnquist, Markus Hiienkari, Jani Mäkipää and Lauri Koskinen
J. Low Power Electron. Appl. 2016, 6(3), 17; https://doi.org/10.3390/jlpea6030017 - 8 Sep 2016
Cited by 2 | Viewed by 8885
Abstract
The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC–DC converter that supplies [...] Read more.
The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC–DC converter that supplies these processors is critical since energy consumption of the DC–DC/processor system is proportional to the DC–DC converter efficiency. The DC–DC converter must maintain high efficiency over a large load range generated from the multiple power modes of the processor. This paper presents a fully integrated step-down self-oscillating switched-capacitor DC–DC converter that is capable of meeting these challenges. The area of the converter is 0.0104 mm2 and is designed in 28 nm ultra-thin body and buried oxide fully-depleted SOI (UTBB FD-SOI). Back-gate biasing within FD-SOI is utilized to increase the load power range of the converter. With an input of 1 V and output of 460 mV, measurements of the converter show a minimum efficiency of 75% for 79 nW to 200 µW loads. Measurements with an off-chip NT processor load show efficiency up to 86%. The converter’s large load power range and high efficiency make it an excellent fit for energy-constrained processors. Full article
(This article belongs to the Special Issue Ultra-Low Power VLSI Design for Emerging Applications)
►▼ Show Figures

Graphical abstract

968 KiB  
Article
Remote System Setup Using Large-Scale Field Programmable Analog Arrays (FPAA) to Enabling Wide Accessibility of Configurable Devices
by Jennifer Hasler, Sahil Shah, Sihwan Kim, Ishan Kumal Lal and Michelle Collins
J. Low Power Electron. Appl. 2016, 6(3), 14; https://doi.org/10.3390/jlpea6030014 - 28 Jul 2016
Cited by 10 | Viewed by 7664
Abstract
We present a novel remote test system, an integrated remote testing system requiring minimal technology support overhead, enabled by configurable analog–digital Integrated Circuits (IC) to create a simple interface for a wide range of experiments. Our remote test system requires no additional setup, [...] Read more.
We present a novel remote test system, an integrated remote testing system requiring minimal technology support overhead, enabled by configurable analog–digital Integrated Circuits (IC) to create a simple interface for a wide range of experiments. Our remote test system requires no additional setup, resulting both from using highly configurable devices, as well as from the advancement of straight-forward digital interfaces (i.e., USB) for the resulting experimental system. The system overhead requirements require simple email handling, available over almost all network systems with no additional requirements. The system is empowered through large-scale Field Programmable Analog Array (FPAA) devices and Baseline Tool Framework (BTF), where we present a range of experimentally measured examples illustrating the range of user interfacing available for the remote user. Full article
(This article belongs to the Special Issue Ultra-Low Power VLSI Design for Emerging Applications)
►▼ Show Figures

Figure 1

683 KiB  
Article
Scaling Floating-Gate Devices Predicting Behavior for Programmable and Configurable Circuits and Systems
by Jennifer Hasler, Sihwan Kim and Farhan Adil
J. Low Power Electron. Appl. 2016, 6(3), 13; https://doi.org/10.3390/jlpea6030013 - 27 Jul 2016
Cited by 29 | Viewed by 7867
Abstract
This paper presents scaling of Floating-Gate (FG) devices, and the resulting implication to large-scale Field Programmable Analog Arrays (FPAA) systems. The properties of FG circuits and systems in one technology (e.g., 350 nm CMOS) are experimentally shown to roughly translate to FG circuits [...] Read more.
This paper presents scaling of Floating-Gate (FG) devices, and the resulting implication to large-scale Field Programmable Analog Arrays (FPAA) systems. The properties of FG circuits and systems in one technology (e.g., 350 nm CMOS) are experimentally shown to roughly translate to FG circuits in scaled down processes in a way predictable through MOSFET physics concepts. Scaling FG devices results in higher frequency response, (e.g., FPAA fabric) as well as lower parasitic capacitance and lower power consumption. FPAA architectures, limited to 50–100 MHz frequency ranges could be envisioned to operate at 500 MHz–1 GHz for 130 nm line widths, and operate around 4 GHz for 40 nm line widths. Full article
(This article belongs to the Special Issue Ultra-Low Power VLSI Design for Emerging Applications)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-5
Back to TopTop