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J. Low Power Electron. Appl. 2017, 7(2), 7;

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Department of Electronic Systems Engineering, Malaysia-Japan International Institute of Technology Universiti Teknologi Malaysia, Jalan Sultan Yahya Petra, 54100 Kuala Lumpur, Malaysia
Integrated Circuit Engineering, 14387, Taman Paik Siong, Batu 71/2, Jalan Puchong, 47180 Puchong, Selangor Darul Ehsan, Malaysia
Author to whom correspondence should be addressed.
Academic Editor: Tony Tae-Hyoung Kim
Received: 22 November 2016 / Revised: 17 March 2017 / Accepted: 27 March 2017 / Published: 28 April 2017
(This article belongs to the Special Issue Ultra-Low Power VLSI Design for Emerging Applications)
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Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption in the scan chain but also introduce spurious switching activities in the combinational logic. In this work, a new low power gating scan cell for scan based designs has been proposed in order to reduce power consumption in the scan chain as well as the combinational part during shifting. We have modified the conventional scan cell and augmented it with state preserving and gating logic that enables an average power reduction in combinational logic during shift mode. The new scan cell mitigates the number of transitions during shift and capture cycles. Thus, it reduces the average power consumption inside the scan cell and as a result the scan chain during scan shifting with a low impact on peak power during the capture cycle. Furthermore, due to introducing a new shorter shift path, improvements are observed in terms of propagation delay and power consumption in the scan chain during shifting. This leads to higher feasible shift frequency whereby the shift frequency is limited by the maximum power budget and hence results in reducing the test application time. The post-layout spice simulation results show a 7.21% reduction in total power consumption, an average 12.25% reduction of shift power consumption, and a 50.7% improvement in the clock (CLK)-to-shift propagation delay over the conventional scan cell in Synopsys 32/28 nm standard CMOS technology. View Full-Text
Keywords: switching activity; scan cell; gating logic; shift power; peak power; design for testability switching activity; scan cell; gating logic; shift power; peak power; design for testability

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Naeini, M.M.; Dass, S.B.; Ooi, C.Y. The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology. J. Low Power Electron. Appl. 2017, 7, 7.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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