Special Issue "Design Space Exploration and Resource Management of Multi/Many-Core Systems"

Special Issue Editors

Dr. Amit Kumar Singh
Website
Guest Editor
School of Computer Science and Electronic Engineering, University of Essex, Colchester CO4 3SQ, UK
Interests: embedded systems; MPSoC; NoC; design space exploration; run-time mapping
Special Issues and Collections in MDPI journals
Dr. Amlan Ganguly
Website
Guest Editor
Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY 14623, USA
Interests: interconnection network; Network-on-Chip (NoC); multi-chip system integration; wireless interconnects; data center networks
Special Issues and Collections in MDPI journals

Special Issue Information

Dear Colleagues,

The reliance of computing systems of various scales, e.g., emebbeded to cloud computing, is increasing on multi/many-core chips mainly to satisfy the high performance requirement of complex software applications. These systems are typically referred to as multi/many-core systems. At the same time, depending upon the application domain, these systems also demand energy efficiency, reliabilty and/or security. These demands can be fulfilled by exploring the design space by considering the software applications and the multi/many-core chips to find the design points leading to efficiency in all the required metrics depending upon the application domain.

Further, considering varying workloads in the systems over time, efficient resource management methodologies need to be developed to meet the requirements of performance, energy efficiency, reliability and/or security. These methodologies can perform resource management decisions online without any prior analysis or can exploit offline explore design space to take efficient run-time decisions and, thus, management.

Authors are invited to submit regular papers following the JLPEA submission guidelines, within the remit of this Special Issue call. Topics include but are not limited to:

  • Design space exploration (DSE) techniques for multi/many-core systems;
  • DSE considering optimisation for one or more metrics, such as accuracy, performance, energy consumption, reliability and security;
  • Resource management considering various principles, e.g., machine learning and heuristics;
  • Adaptive and hieracrchical resource management;
  • Approximate computing to achieve trade-offs for various metrics.

Dr. Amit Kumar Singh
Dr. Amlan Ganguly
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Multicore and many-core
  • Design space exploration
  • Resource management
  • Security
  • Reliability
  • Energy efficiency
  • Machine learning
  • Approximate computing

Published Papers (4 papers)

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Research

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Open AccessArticle
PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications
J. Low Power Electron. Appl. 2020, 10(4), 31; https://doi.org/10.3390/jlpea10040031 (registering DOI) - 30 Sep 2020
Abstract
Multiple multi-threaded tasks constitute a modern many-core application. An accompanying generic Directed Acyclic Graph (DAG) represents the execution precedence relationship between the tasks. The application comes with a hard deadline and high peak power consumption. Parallel execution of multiple tasks on multiple cores [...] Read more.
Multiple multi-threaded tasks constitute a modern many-core application. An accompanying generic Directed Acyclic Graph (DAG) represents the execution precedence relationship between the tasks. The application comes with a hard deadline and high peak power consumption. Parallel execution of multiple tasks on multiple cores results in a quicker execution, but higher peak power. Peak power single-handedly determines the involved cooling costs in many-cores, while its violations could induce performance-crippling execution uncertainties. Less task parallelization, on the other hand, results in lower peak power, but a more prolonged deadline violating execution. The problem of peak power minimization in many-cores is to determine task-to-core mapping configuration in the spatio-temporal domain that minimizes the peak power consumption of an application, but ensures application still meets the deadline. All previous works on peak power minimization for many-core applications (with or without DAG) assume only single-threaded tasks. We are the first to propose a framework, called PkMin, which minimizes the peak power of many-core applications with DAG that have multi-threaded tasks. PkMin leverages the inherent convexity in the execution characteristics of multi-threaded tasks to find a configuration that satisfies the deadline, as well as minimizes peak power. Evaluation on hundreds of applications shows PkMin on average results in 49.2% lower peak power than a similar state-of-the-art framework. Full article
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Open AccessFeature PaperArticle
Low-Complexity Run-time Management of Concurrent Workloads for Energy-Efficient Multi-Core Systems
J. Low Power Electron. Appl. 2020, 10(3), 25; https://doi.org/10.3390/jlpea10030025 - 25 Aug 2020
Abstract
Contemporary embedded systems may execute multiple applications, potentially concurrently on heterogeneous platforms, with different system workloads (CPU- or memory-intensive or both) leading to different power signatures. This makes finding the most energy-efficient system configuration for each type of workload scenario extremely challenging. This [...] Read more.
Contemporary embedded systems may execute multiple applications, potentially concurrently on heterogeneous platforms, with different system workloads (CPU- or memory-intensive or both) leading to different power signatures. This makes finding the most energy-efficient system configuration for each type of workload scenario extremely challenging. This paper proposes a novel run-time optimization approach aiming for maximum power normalized performance under such circumstances. Based on experimenting with PARSEC applications on an Odroid XU-3 and Intel Core i7 platforms, we model power normalized performance (in terms of instruction per second (IPS)/Watt) through multivariate linear regression (MLR). We derive run-time control methods to exploit the models in different ways, trading off optimization results with control overheads. We demonstrate low-cost and low-complexity run-time algorithms that continuously adapt system configuration to improve the IPS/Watt by up to 139% compared to existing approaches. Full article
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Review

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Open AccessFeature PaperReview
A Survey of Resource Management for Processing-In-Memory and Near-Memory Processing Architectures
J. Low Power Electron. Appl. 2020, 10(4), 30; https://doi.org/10.3390/jlpea10040030 - 24 Sep 2020
Abstract
Due to the amount of data involved in emerging deep learning and big data applications, operations related to data movement have quickly become a bottleneck. Data-centric computing (DCC), as enabled by processing-in-memory (PIM) and near-memory processing (NMP) paradigms, aims to accelerate these types [...] Read more.
Due to the amount of data involved in emerging deep learning and big data applications, operations related to data movement have quickly become a bottleneck. Data-centric computing (DCC), as enabled by processing-in-memory (PIM) and near-memory processing (NMP) paradigms, aims to accelerate these types of applications by moving the computation closer to the data. Over the past few years, researchers have proposed various memory architectures that enable DCC systems, such as logic layers in 3D-stacked memories or charge-sharing-based bitwise operations in dynamic random-access memory (DRAM). However, application-specific memory access patterns, power and thermal concerns, memory technology limitations, and inconsistent performance gains complicate the offloading of computation in DCC systems. Therefore, designing intelligent resource management techniques for computation offloading is vital for leveraging the potential offered by this new paradigm. In this article, we survey the major trends in managing PIM and NMP-based DCC systems and provide a review of the landscape of resource management techniques employed by system designers for such systems. Additionally, we discuss the future challenges and opportunities in DCC management. Full article
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Other

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Open AccessOpinion
A Case for Security-Aware Design-Space Exploration of Embedded Systems
J. Low Power Electron. Appl. 2020, 10(3), 22; https://doi.org/10.3390/jlpea10030022 - 17 Jul 2020
Abstract
As modern embedded systems are becoming more and more ubiquitous and interconnected, they attract a world-wide attention of attackers and the security aspect is more important than ever during the design of those systems. Moreover, given the ever-increasing complexity of the applications that [...] Read more.
As modern embedded systems are becoming more and more ubiquitous and interconnected, they attract a world-wide attention of attackers and the security aspect is more important than ever during the design of those systems. Moreover, given the ever-increasing complexity of the applications that run on these systems, it becomes increasingly difficult to meet all security criteria. While extra-functional design objectives such as performance and power/energy consumption are typically taken into account already during the very early stages of embedded systems design, system security is still mostly considered as an afterthought. That is, security is usually not regarded in the process of (early) design-space exploration of embedded systems, which is the critical process of multi-objective optimization that aims at optimizing the extra-functional behavior of a design. This position paper argues for the development of techniques for quantifying the ’degree of secureness’ of embedded system design instances such that these can be incorporated in a multi-objective optimization process. Such technology would allow for the optimization of security aspects of embedded systems during the earliest design phases as well as for studying the trade-offs between security and the other design objectives such as performance, power consumption and cost. Full article
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