Special Issue "Emerging Interconnection Networks Across Scales"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 December 2018)

Special Issue Editor

Guest Editor
Dr. Amlan Ganguly

Director, Multicore Systems Laboratory, Department of Computer Engineering, Rochester Institute of Technology (RIT), New York, NY, USA
Website | E-Mail
Interests: interconnection network; Network-on-Chip (NoC); multi-chip system integration; wireless interconnects; data center networks

Special Issue Information

Dear Colleagues,

With the advent of multicore or manycore processors, the interconnection architecture on Multi-Processor System-on-Chips shifted from the bus-based methodology towards the Network-on-Chip paradigm. However, due to issues of unpredictable latencies and power consumption over multi-hop metal/dielectric paths, emerging interconnection architectures with monolithic 3D integration, photonic, RF and wireless interconnections are being investigated. On the other hand, multi-chip systems, such as blade servers and embedded systems, require efficient high bandwidth interconnections between processors and memory subsystems. Traditional I/O and packaging techniques suffer from non-scalable analog designs pin densities. Therefore, the performance gap between on-chip and off-chip interconnects is expected to widen. Moreover, in the era or cloud services and Internet-of-Things (IoTs), chip-to-chip interconnects will need to provide seamless integration of heterogeneous architectures on the same platform which may range from ASICs, FPGA, multi/manycore CPUs and GPUs. On the other side of the spectrum, data centers, which provide the storage and computational backbone of the modern digital world have extremely high power consumption. Data center networks, interconnecting thousands of servers, result in increasing power consumption with the increase in network performance. All these factors require interconnection networks, connecting either many cores within a die, processors within a server or servers within a data center, to extremely energy efficient while supporting the necessary performance. The issue of security and privacy in these interconnection fabrics also need to be specifically tailored for their operating environments. This would naturally need innovative solutions, encompassing physical layer, routing protocols, as well as architectures, and carefully establish design trade-offs.

To advance and capture the recent and future innovations in interconnection technology at multiple scales, such as on-chip networks, chip-to-chip interconnections and data center networks, the proposed Special Issue of JLPEA will be dedicated towards innovative ways of interconnecting electronic devices. The readers of this Special Issue will be able to familiarize themselves with the recent advances in these technology paradigms, while also discovering the common and disparate issues about these interconnections at these various scales. Original contributions from the following non-exhaustive list of topics are solicited:

  • Power efficiency in Network-on-Chip
  • Chip-to-chip interconnections
  • Interconnections for heterogeneous systems
  • Dynamic interconnection networks
  • Data center networks
  • 3D NoC
  • Photonic/optical interconnects
  • RF interconnections
  • Wireless interconnects
  • Millimeter-wave wireless communication for computing platforms
  • THz band communications for computing systems
  • Security and Privacy in NoC
  • Data center network security and privacy
  • Congruence of interconnection networks with IoT
Dr. Amlan Ganguly
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 350 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Network-on-Chip
  • Chip-to-Chip interconnection
  • Multi-chip integration
  • Data center Network
  • Emerging interconnection technologies
  • 3D integration
  • Interposers
  • Photonic/Optical interconnects
  • RF interconnects
  • Wireless interconnects

Published Papers (4 papers)

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Research

Open AccessArticle Improving the Performance of Turbo-Coded Systems under Suzuki Fading Channels
J. Low Power Electron. Appl. 2019, 9(2), 13; https://doi.org/10.3390/jlpea9020013
Received: 7 February 2019 / Revised: 10 March 2019 / Accepted: 25 March 2019 / Published: 29 March 2019
PDF Full-text (283 KB)
Abstract
In this paper, the performance of coded systems is considered in the presence of Suzuki fading channels, which is a combination of both short-fading and long-fading channels. The problem in manipulating a Suzuki fading model is the complicated integration involved in the evaluation [...] Read more.
In this paper, the performance of coded systems is considered in the presence of Suzuki fading channels, which is a combination of both short-fading and long-fading channels. The problem in manipulating a Suzuki fading model is the complicated integration involved in the evaluation of the Suzuki probability density function (PDF). In this paper, we calculated noise PDF after the zero-forcing equalizer (ZFE) at the receiver end with several approaches. In addition, we used the derived PDF to calculate the log-likelihood ratios (LLRs) for turbo-coded systems, and results were compared to Gaussian distribution-based LLRs. The results showed a 2 dB improvement in performance compared to traditional LLRs at 10 - 6 of the bit error rate (BER) with no added complexity. Simulations were obtained utilizing the Matlab program, and results showed good improvement in the performance of the turbo-coded system with the proposed LLRs compared to Gaussian-based LLRs. Full article
(This article belongs to the Special Issue Emerging Interconnection Networks Across Scales)
Open AccessArticle DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures
J. Low Power Electron. Appl. 2019, 9(1), 7; https://doi.org/10.3390/jlpea9010007
Received: 27 November 2018 / Revised: 31 January 2019 / Accepted: 1 February 2019 / Published: 5 February 2019
PDF Full-text (1229 KB) | HTML Full-text | XML Full-text
Abstract
Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used [...] Read more.
Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead. Full article
(This article belongs to the Special Issue Emerging Interconnection Networks Across Scales)
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Open AccessArticle Towards Energy-Efficient and Secure Computing Systems
J. Low Power Electron. Appl. 2018, 8(4), 48; https://doi.org/10.3390/jlpea8040048
Received: 30 October 2018 / Revised: 19 November 2018 / Accepted: 21 November 2018 / Published: 27 November 2018
PDF Full-text (1748 KB) | HTML Full-text | XML Full-text
Abstract
Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems. This work presents a summary of energy-efficiency techniques that have been applied in security primitives [...] Read more.
Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems. This work presents a summary of energy-efficiency techniques that have been applied in security primitives or mechanisms to ensure computing systems’ resilience against various security threats on hardware. This work also uses examples to discuss practical methods for securing the hardware for computing systems to achieve energy efficiency. Full article
(This article belongs to the Special Issue Emerging Interconnection Networks Across Scales)
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Open AccessArticle Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications
J. Low Power Electron. Appl. 2018, 8(4), 39; https://doi.org/10.3390/jlpea8040039
Received: 13 September 2018 / Revised: 11 October 2018 / Accepted: 12 October 2018 / Published: 17 October 2018
PDF Full-text (4190 KB) | HTML Full-text | XML Full-text
Abstract
Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered [...] Read more.
Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties. Full article
(This article belongs to the Special Issue Emerging Interconnection Networks Across Scales)
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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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