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Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

University Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France
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This paper is an extended version of our paper published inS. Chairat, E. Beigne, F. Berthier, I. Miro-Panades and M. Belleville, “Ultra low energy FDSOI asynchronous reconfiguration network for an IoT wireless sensor network node,” 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 2016, pp. 1–3.
Academic Editors: David Bol and Steven A. Vitale
J. Low Power Electron. Appl. 2017, 7(2), 11; https://doi.org/10.3390/jlpea7020011
Received: 2 March 2017 / Revised: 29 April 2017 / Accepted: 4 May 2017 / Published: 11 May 2017
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2016)
This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL) to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V and a 1.1 ns/bit latency per stage. View Full-Text
Keywords: on-chip communication network; adaptive blocks; asynchronous design on-chip communication network; adaptive blocks; asynchronous design
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Chairat, S.; Beigne, E.; Miro-Panades, I.; Belleville, M. Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits . J. Low Power Electron. Appl. 2017, 7, 11.

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