A 0.3 V Nanowatt Bulk-Driven CCII⁻ in 0.18-µm CMOS for Ultra-Low-Power Current-Mode Interfaces

Abstract

A 0.3 V nanowatt CCII⁻ is presented in 0.18 $\mathsf{\mu }$m TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 Hz are ${\beta }_0=0.9452$ (−0.48 dB) and ${\alpha }_0=0.9609$ (≈−0.35 dB), with $-3$ dB bandwidths of 22.95 kHz and 63.95 kHz for the voltage and current transfers, respectively. Small-signal extraction confirms the intended impedance profile, yielding $R_X=46.73$ M$\mathsf{\Omega }$, $R_Z=1.204$ G$\mathsf{\Omega }$, and a very high input resistance $R_Y=392$ G$\mathsf{\Omega }$. Robustness is verified through full PVT and mismatch analyses, showing stable functionality across process corners, a 0–80 °C temperature range, and 270–330 mV supply variations while maintaining nanowatt-level dissipation.

1. Introduction

The rapid growth of portable, wearable, and implantable electronic systems is driving the development of analog building blocks able to operate with ultra-low supply voltages and extremely limited energy budgets. In many biomedical and sensing front-ends, long lifetime and maintenance-free operation are key requirements, motivating battery-less solutions powered by energy harvesting and aggressive voltage scaling [1]. In this scenario, the supply voltage is often pushed into the few-hundred-millivolt range to suppress static and dynamic losses while still meeting constraints on signal integrity and robustness. At the system level, this trend is reflected in low-voltage signal-conditioning and stimulation circuits, where dedicated design techniques are adopted either to operate from reduced supply rails or to realize high-voltage functions in low-voltage CMOS technologies [2,3]. Similarly, ultra-low-power front-end blocks such as OTAs for biomedical-band signals are increasingly designed under low-voltage constraints, in order to match the bandwidth requirements of ECG, EEG, ERG, and related sensing modalities [4,5,6].

When the supply voltage is scaled below about $0.5\mathrm{V}$, conventional gate-driven MOS design becomes increasingly difficult because of the limited headroom imposed by threshold voltages and stacked devices. In this context, bulk-driven (BD) techniques are attractive, since they shift the signal path to the body terminal, thereby relaxing the threshold-voltage constraint and enabling wider signal swing and input common-mode range under very low supply conditions [7,8]. When combined with weak-inversion or subthreshold biasing, BD operation also allows a significant reduction in static power consumption, although at the cost of reduced transconductance, lower loop gain, and limited bandwidth [6,9,10]. Alternative low-voltage approaches based on quasi-floating-gate and related techniques have also been investigated, confirming that the choice of the signal-driving mechanism strongly affects the achievable trade-off between transconductance efficiency, dynamic behavior, and energy consumption [9].

Within the broader context of bulk-driven low-voltage analog design, it is worth remarking that the voltage-follower core adopted in the present work is related to the bulk-driven voltage follower/DC level shifter introduced by Kulej et al. [11]. This prior work is relevant because it establishes the bulk-driven follower as an effective low-voltage front-end solution and provides the proper background for the input stage adopted in the proposed conveyor.

Within this framework, the second-generation current conveyor (CCII) is a particularly relevant building block for low-voltage analog signal processing. Owing to its mixed voltage/current nature, the CCII combines voltage transfer between terminals Y and X with current transfer between terminals X and Z, while ideally exhibiting high input impedance at Y, low input impedance at X, and high output impedance at Z. Since its introduction as a current-mode alternative to classical voltage-mode structures [12], the CCII has been widely employed in the realization of filters, oscillators, impedance converters, instrumentation circuits, and sensor interfaces [13,14,15,16]. Its modularity has also made it attractive in application-driven architectures requiring compact front-ends and high input impedance, including biomedical interfaces and sensor readout circuits [15,17]. Further examples of conveyor-based design include non-conventional analog functions such as mem-element emulators and conveyor-based instrumentation blocks [18,19].

As CMOS implementations matured, research on current conveyors evolved along two complementary directions. On one side, several works focused on high-performance realizations aimed at improving transfer accuracy, bandwidth, and terminal impedance levels. For example, the CMOS CCII reported in [13] combines a high-performance voltage-follower section with a current-follower branch to achieve wideband operation and a clear impedance hierarchy. On the other side, application-oriented studies exploited the CCII as a modular current-mode primitive in complete analog front-ends. Examples include CCII⁻ based interfaces for capacitive and resistive sensors [15], high-input-impedance biomedical stages based on bootstrap techniques [17], universal filter realizations [14], and practical oscillator implementations using current conveyor variants [10]. Overall, these works established the CCII as a versatile and IC-friendly building block for both general-purpose analog design and specific interface applications.

More recently, the progressive reduction of supply voltage and available power budget has shifted the focus toward CCII architectures able to operate under ultra-low-voltage (ULV) and ultra-low-power (ULP) conditions. In such a regime, the implementation of the $Y\to X$ voltage buffering and $X\to Z$ current conveying functions become particularly challenging because of the reduced intrinsic gain and transconductance available at very low bias currents. To mitigate these limitations, bulk-driven and related low-voltage techniques have been increasingly adopted. Early contributions already explored the use of bulk-driven approaches to realize low-voltage current conveyors with improved input swing and current-mode applicability. In particular, Khateb et al. proposed a bulk-driven folded-cascode OTA-based CCII± operating at very low supply voltage and demonstrated its use in a multifunction current-mode filter [20]. In a related contribution, a bulk-driven class-AB CCII was introduced to improve dynamic behavior and output driving capability under low-voltage operation [21]. These works represent important steps in showing the feasibility of bulk-driven current conveyors for low-voltage and low-power analog signal processing.

In addition, the literature on bulk-driven voltage followers and ultra-low-voltage OTAs [11] is particularly relevant to the present work, because the $Y\to X$ voltage-buffer section of the proposed CCII⁻ is not introduced as a completely new cell but rather as the integration of a known low-voltage follower concept within a compact current-conveyor architecture. In this sense, the novelty of the proposed solution lies at the architectural level, namely in the realization of a complete CCII⁻ with a reduced number of active branches, ultra-low-voltage operation at $0.3$ V, nanowatt power consumption, and post-layout validated performance under PVT and mismatch conditions.

Subsequent studies further investigated bulk-driven, quasi-floating-gate, and combined BD–QFG conveyor solutions, showing how the adopted signal-driving technique affects the attainable trade-off among transconductance efficiency, bandwidth, and power consumption under sub-volt supplies [9]. A relevant milestone in this area is the experimentally validated $0.3$ V BD CCII reported in [7], where all transistors are biased in subthreshold and nanowatt-range power dissipation is achieved. Other contributions explored architecture-level solutions to improve the energy–speed trade-off. For instance, adaptive-biasing strategies were proposed to enhance transient performance while limiting average dissipation [22], whereas BD self-cascode approaches were introduced to improve dynamic behavior and terminal parasitics under low-voltage operation [23]. More recently, Shah et al. presented a $0.35$ V subthreshold BD CCII achieving MHz-range bandwidth by means of a higher-gain core and enhanced output stages, at the cost of microampere-level quiescent current [24].

This evolution clearly shows that the design of ULV current conveyors is governed by a strict trade-off among supply voltage, static power consumption, transfer accuracy, and dynamic performance, while the literature has demonstrated the feasibility of bulk-driven current conveyors below $0.5$ V, achieving operation at $0.3$ V with nanowatt-level dissipation and, at the same time, preserving useful conveying behavior under realistic integrated constraints, including post-layout parasitics and mismatch, remains a practically relevant challenge. This is particularly true for energy-harvesting and battery-less sensor-interface applications, where the power budget is extremely limited and the required signal bandwidth often lies in the low-kHz range.

In this context, this paper presents an ultra-compact bulk-driven CCII⁻ designed in $0.18\mathsf{\mu }\mathrm{m}$ CMOS and operating from a single $V_{DD}=0.3\mathrm{V}$ supply. Rather than introducing a radically new current conveyor topology, the proposed contribution lies in the combination of architectural simplicity, bulk-driven operation, ultra-low-voltage supply, and nanowatt-level power consumption, validated at the post-layout level. The adopted architecture simplifies the internal voltage-buffering section so as to reduce the number of active branches and the quiescent current while still preserving the negative-feedback mechanism required to enforce the Y–X voltage transfer. A compact current-repetition branch conveys the X-terminal current to the Z terminal. Post-layout simulations, including extracted parasitics, PVT analysis, and mismatch assessment, confirm correct CCII⁻ operation with nanowatt-level power dissipation, making the proposed solution suitable for ultra-low-power sensor-interface applications in the kHz range. At the same time, the proposed design explicitly accepts the trade-offs associated with this extreme operating point, including non-ideal tracking accuracy and limited bandwidth, in exchange for circuit compactness and minimum static power.

The remainder of the paper is organized as follows. Section 2 introduces the proposed CCII⁻ topology and discusses its operating principle. Section 3 presents a simplified small-signal analysis and derives the main performance relationships. Section 4 reports the post-layout simulation results and discusses the key performance trade-offs, including PVT and statistical variability. Section 5 presents an application example based on a reconfigurable filter to validate the proposed CCII⁻ under realistic operating conditions. Section 6 compares the proposed solution with representative current conveyor implementations from the literature. Finally, Section 7 concludes the paper.

2. Proposed Architecture

Figure 1a reports the proposed ultra-low-voltage (ULV) bulk-driven second-generation current conveyor (CCII⁻), together with its post-layout implementation in a 0.18-$\mathsf{\mu }$m TSMC CMOS process (Figure 1b). The circuit targets the classical CCII⁻ port relations, namely $I_Y\approx 0$, $V_X\approx V_Y$, and $I_Z\approx -I_X$, while operating from a single $V_{DD}=0.3$ V supply and subthreshold biasing to minimize static power dissipation.

As shown in Figure 1a, the architecture is composed of two compact functional blocks: (i) a bulk-driven voltage-buffer section that enforces $V_X\approx V_Y$ through local negative feedback, and (ii) a current repetition branch that mirrors the X-terminal current to the Z terminal. In the voltage-buffer section, transistors M1–M2 form the bulk-driven input pair: the input signal is applied to the body terminal of M1 (node Y) to avoid the threshold-voltage limitation in the signal path under a 0.3 V headroom. The unity-gain condition is obtained by closing a local feedback loop around the buffer (bulk/drain feedback as indicated in the schematic), which forces the internal operating point such that the X node tracks the Y node with high input impedance at Y and the lowest impedance at X. The quiescent currents of the buffer are set by the bias transistors (M3–M4), which operate in weak inversion to maximize transconductance efficiency at nanowatt power levels.

It is worth noting that the main contribution of the proposed solution does not lie in the introduction of a radically new current-conveyor topology but rather in the architectural simplification adopted to push operation toward the extreme ULV/ULP regime. In particular, with respect to previously reported bulk-driven CCII implementations operating at $0.3$ V, the proposed voltage-buffer section exploits one less current branch. This choice directly reduces the static current required by the $Y\to X$ path and contributes to the overall nanowatt power budget of the conveyor. In addition, the simplified buffer avoids the presence of internal high-impedance nodes directly involved in the voltage and current transfer functions. As a consequence, the dynamic behavior is less dependent on internal pole-splitting mechanisms and does not require Miller-type compensation to enforce stability. This aspect is particularly relevant in the ULV regime, where even small parasitic capacitances may strongly affect the pole locations and the available bandwidth.

The above point also helps clarify the practical meaning of the proposed trade-off. The goal of this work is not to maximize transfer accuracy in absolute terms but to demonstrate that a very compact CCII⁻ can still preserve useful conveying behavior at $V_{DD}=0.3$ V and nanowatt-level power dissipation, while remaining compatible with post-layout operation. In this sense, the reduction of one current branch is a design choice aimed at lowering current consumption and simplifying the internal dynamics of the conveyor. The tradeoff is a non-ideal voltage transfer ${\beta }_0<1$, which reflects the limited transconductance and loop gain available under subthreshold bulk-driven biasing. Therefore, the proposed architecture should be interpreted as a solution optimized for severely energy-constrained sensor interfaces, where minimum power budget is the dominant requirement and moderate deviations from ideal tracking can be tolerated.

The current conveying action ($I_Z\approx I_X$) is realized by the current repetition branch (M5–M6). In this block, M5 is driven to replicate the drain current associated with the X-node branch and deliver it to terminal Z, while M6 provides the required biasing in subthreshold. The full CCII core is biased by a single low reference current ($I_{bias}=2$ nA in Figure 1a); a diode-connected device (Mb) generates the bias voltage $V_{bn}$ that is distributed to the current-source devices, thereby setting all branches in weak inversion. Transistor dimensions are selected to meet the ULV gain/impedance trade-offs while keeping the device count minimal (as annotated in Figure 1, with $L=1\mathsf{\mu }$m and widths of 7 $\mathsf{\mu }$m or 12 $\mathsf{\mu }$m for the main devices).

The simplified architecture also has implications at the application level. Unlike more complex low-voltage conveyor cores relying on stronger internal compensation, the proposed solution is intended for low-frequency front-ends in which the useful signal band is in the kHz range and the main design priority is minimizing the quiescent power. Under these conditions, the proposed CCII⁻ offers an attractive compromise between implementation simplicity, energy efficiency, and conveying functionality. The post-layout results reported in the following sections confirm that this compact architecture remains operational under extracted parasitics, process corners, and mismatch, thereby supporting the practical relevance of the adopted design strategy.

The corresponding layout is also shown in Figure 1b. In the proposed implementation, the layout was primarily conceived to obtain a post-layout validation of the ultra-low-voltage, ultra-low-power CCII core while keeping parasitic effects under control and preserving the simplicity of the structure. For this reason, the adopted solution does not systematically exploit more advanced mismatch-oriented techniques, such as common-centroid arrangements or the extensive use of dummy devices. Nevertheless, care was taken to preserve a reasonable symmetry in the placement of paired devices (e.g., M1–M2 and M3–M4) and to keep local interconnects short, especially around critical internal nodes, so as to limit systematic offsets and parasitic degradation under post-layout conditions. Moreover, since bulk-driven operation requires independent well access, the PMOS devices that process the signal through the body terminal are placed in isolated wells with guard rings to mitigate substrate coupling and latch-up risks. Since mismatch sensitivity is particularly critical in weak inversion, a more symmetry-oriented and mismatch-aware layout strategy, including common-centroid and dummy-based solutions where applicable, could be adopted in future implementations to further improve robustness, especially when scaling the technology to nodes where mismatch and parasitic effects become more dominant. The reported post-layout view (Figure 1b) refers to the complete CCII core in 0.18-$\mathsf{\mu }$m TSMC technology, and its extracted parasitics are included in the validation reported in the following sections.

3. Analytical Results and Small-Signal Notation

This section summarizes the small-signal behavior of the proposed CCII⁻ in compact form. The Laplace variable is denoted by s. For each MOS transistor $M_i$, $g_{m_i}$ denotes the gate-driven transconductance, $g_{m{b}_i}$ the bulk-driven transconductance, and $g_{d{s}_i}$ the output conductance (with $r_{o_i}=1/g_{d{s}_i}$). Parasitic capacitances follow the usual notation $C_{gs}$, $C_{gd}$, $C_{bd}$, $C_{bs}$, and $C_{ds}$.

The analytical treatment reported in this section is intentionally kept at a first-order level. Its purpose is not to provide an exact prediction of the complete frequency response but rather to identify the main internal mechanisms that limit the voltage and current transfer paths, in line with the type of simplified small-signal discussion commonly adopted in the literature. In particular, the following derivation is meant to highlight the dominant nodes, parasitic capacitances, and conductance ratios that mainly determine the tracking accuracy and bandwidth of the proposed architecture.

To keep the expressions concise, the following dimensionless error factors are introduced:

$${\epsilon }_X={\displaystyle \frac{g_{ds2}+g_{ds4}}{g_{mb2}}},{\epsilon }_H={\displaystyle \frac{g_{ds1}+g_{ds3}}{g_{m1}}}$$

(1)

The quantities ${\epsilon }_H$ and ${\epsilon }_X$ provide a compact measure of the main static non-idealities affecting the two conveying paths. More specifically, ${\epsilon }_H$ accounts for the finite gain of the internal voltage-buffer loop associated with node H, whereas ${\epsilon }_X$ quantifies the degradation introduced at node X by the finite output conductances of the devices connected to the low-impedance terminal. Therefore, larger values of ${\epsilon }_H$ and ${\epsilon }_X$ directly correspond to a stronger departure from ideal voltage and current conveying behavior.

The dominant pole of the $Y\to X$ voltage-buffer loop is associated with the internal node H. From the highlighted derivation, the effective capacitance at node H is approximated as

$$C_H\approx C_{gd2}{\displaystyle \frac{g_{m2}}{g_{mb2}}},$$

(2)

leading to the dominant time constant

$${\tau }_H\approx {\displaystyle \frac{C_H}{g_{m1}}}={\displaystyle \frac{C_{gd2}}{g_{m1}}}{\displaystyle \frac{g_{m2}}{g_{mb2}}},p_H\approx -{\displaystyle \frac{1}{{\tau }_H}}.$$

(3)

Equation (3) shows that the bandwidth of the $Y\to X$ path is mainly limited by the internal node H, through the combined effect of the parasitic capacitance seen at that node and the reduced transconductance available under bulk-driven, weak-inversion operation. In particular, the term $g_{m2}/g_{mb2}$ emphasizes the penalty introduced by bulk-driven excitation, since the bulk transconductance is intrinsically lower than the corresponding gate-driven one. This explains why the voltage transfer is the most critical path in the proposed ULV architecture and why improving the effective loop gain of the buffer would be one of the most direct ways to enhance both accuracy and speed in future implementations.

The current transfer is limited by the pole at node X associated with $C_X$ and the output conductances of the Z-stage devices. Accordingly, the time constant at node X is defined as

$${\tau }_X\approx {\displaystyle \frac{C_X}{g_{ds5}+g_{ds6}}},p_X\approx -{\displaystyle \frac{1}{{\tau }_X}}=-{\displaystyle \frac{g_{ds5}+g_{ds6}}{C_X}}.$$

(4)

Similarly, (4) indicates that the $X\to Z$ current transfer is mainly governed by the parasitic capacitance accumulated at node X and by the finite small-signal conductance of the current-repetition branch. This expression clarifies that the current path is less affected by the internal voltage-buffer dynamics, while it remains sensitive to the sizing and biasing of the output transistors. Therefore, the simplified small-signal model points out that the main bandwidth bottlenecks of the voltage and current transfers originate from different internal mechanisms, consistent with the different trends observed in the simulated frequency responses.

The conveyor is described through the standard CCII⁻ hybrid matrix, where the ideal relations are $I_Y\approx 0$ (i.e., limited to junction leakage, with $R_Y\simeq r_j$), $V_X\approx V_Y$, and $I_Z\approx -I_X$:

$$\left[\begin{array}{c}{V}_X\\ I_Y\\ I_Z\end{array}\right]=\underset{\mathbf{T}\left(s\right)}{\underbrace{\left[\begin{array}{ccc}0& \beta \left(s\right)& 0\\ 0& 0& 0\\ -\alpha \left(s\right)& 0& 0\end{array}\right]}}\left[\begin{array}{c}{I}_X\\ V_Y\\ V_Z\end{array}\right].$$

(5)

The resulting non-ideal voltage and current tracking factors are summarized in

Table 1. Non-ideal CCII⁻ transfer relations (small-signal).

Transfer	Expression
$Y\to X$ voltage gain	${\displaystyle \beta \left(s\right)=\frac{V_X}{V_Y}\simeq \frac{1}{(1+{\epsilon }_H)(1+{\epsilon }_X)}·\frac{1}{1+s{\tau }_H}}$
$X\to Z$ current gain	${\displaystyle \frac{I_Z}{I_X}\simeq -\frac{1}{(1+{\epsilon }_X)}·\frac{1}{1+s{\tau }_X}}$

.

The expressions in Table 1 make the role of the previously defined error factors explicit. In particular, $\beta \left(s\right)$ is affected by both ${\epsilon }_H$ and ${\epsilon }_X$, confirming that the voltage transfer is limited by the finite gain of the internal buffer as well as by the non-ideal behavior of node X. By contrast, the current transfer depends only on ${\epsilon }_X$ at first order, which is consistent with the fact that the $X\to Z$ path is mainly shaped by the current-repetition branch.

Finally,

Table 2. Equivalent nodal parasitics at ports X, Y, and Z. At port Y, the input resistance is dominated by the reverse-biased junction leakage and is modeled as $R_Y\simeq r_j$.

	Node X	Node Y	Node Z
R	${\displaystyle R_X\approx {\left(g_{mb2}+g_{ds2}+g_{ds4}\right)}^{-1}}$	${\displaystyle R_Y\approx r_j}$	${\displaystyle R_Z\approx {\left(g_{ds5}+g_{ds6}\right)}^{-1}}$
C	${\displaystyle C_X\approx C_{bs5}+C_{bs2}+C_{gd4}}$ ${\displaystyle +C_{gd2}+C_{bd5}\frac{g_{mb5}}{g_{ds5}+g_{ds6}}}$	${\displaystyle C_Y\approx C_{bs1}+}$ ${\displaystyle +C_{bd1}\frac{g_{mb1}}{g_{m1}+g_{ds1}+g_{ds3}}}$	${\displaystyle C_Z\approx C_{ds5}+C_{gd6}+C_{bd5}}$

reports the equivalent R–C parameters at ports X, Y, and Z. For readability, the capacitive terms at nodes X and Y are split across two lines within the same cell.

The nodal quantities in Table 2 further support the previous interpretation. In particular, the relatively large equivalent resistance at port X and the parasitic capacitance accumulated at the same node explain the dominant role of ${\tau }_X$ in the current-transfer response, whereas the capacitive multiplication occurring at node H explains the weaker dynamic behavior of the voltage buffer. Therefore, even if the adopted analysis is not intended to reproduce the full post-layout transfer functions in a quantitative way, it is still useful to identify the physical origin of the dominant limitations of the proposed conveyor. This interpretation is consistent with the trends observed in the simulated AC results, where the $Y\to X$ and $X\to Z$ paths exhibit different bandwidths and sensitivities.

Noise Analysis

A compact first-order noise description of the proposed CCII⁻ can be given in terms of an input-referred voltage noise source at terminal Y, $v_{nY}$, and an input-referred current noise source at terminal X, $i_{nX}$. Based on the adopted small-signal noise model, the equivalent input-referred voltage noise can be approximated as

$$\overline{v_{nY}^2}\approx {\displaystyle \frac{{\displaystyle \sum _{i=1}^4\overline{i_{nd,i}^2}}}{g_{mb1}^2}},$$

(6)

where $\overline{i_{nd,i}^2}$ is the drain-current noise power spectral density of the i-th MOS transistor, which in first approximation can be written as

$$\overline{i_{nd,i}^2}\approx 2nkT{g}_{mi},$$

(7)

with n denoting the subthreshold slope factor, k the Boltzmann constant, T the absolute temperature, and $g_{mi}$ the transconductance of the i-th device. Moreover, $g_{mb1}$ is the bulk transconductance of the input transistor. Equation (6) shows that the input-referred voltage noise is mainly penalized by the reduced bulk transconductance, which is an intrinsic feature of bulk-driven operation.

Similarly, the equivalent input-referred current noise at terminal X can be expressed, in first approximation, as

$$\overline{i_{nX}^2}\approx \sum _{i=3}^6\overline{i_{nd,i}^2}.$$

(8)

Therefore, the dominant noise contributions of the proposed CCII⁻ can be directly related to the channel noise of the active devices, while the input-referred voltage noise is further scaled by the inverse of $g_{mb1}^2$. This confirms that noise is one of the main trade-offs of the adopted ultra-low-voltage, ultra-low-power bulk-driven design approach.

4. Simulation Results: Post-Layout Verification, PVT Corners, and Monte Carlo

The proposed CCII⁻ was verified through Spectre simulations in the Cadence Virtuoso environment in a 0.18-$\mathsf{\mu }$m TSMC CMOS technology under ultra-low supply voltage. Unless otherwise stated, all results refer to the post-layout extracted (PEX) netlist, thus accounting for interconnect and layout parasitics. The following figures of merit are considered: (i) the voltage transfer $\beta =V_X/V_Y$ (reported in dB), (ii) the current transfer $\alpha =I_Z/I_X$ (reported in dB), (iii) the DC power consumption $P_{\mathrm{DC}}$, and (iv) the terminal resistances $R_X$, $R_Y$, and $R_Z$.

Figure 2 shows the post-layout AC magnitude of the voltage transfer $\beta$. The circular marker identifies the low-frequency value at 1 Hz (tracking accuracy), while the square marker indicates the $-3$ dB cutoff frequency $f_{-3\mathrm{dB},\beta }$ extracted directly from the same curve. The response exhibits a well-defined low-frequency plateau and a monotonic roll-off, confirming stable operation of the internal $Y\to X$ buffering loop. At nominal conditions, the extracted bandwidth falls in the tens-of-kHz range, consistent with ultra-low-voltage, weak-inversion biasing and with the dominant pole predicted by the analytical discussion in Section 3. More specifically, the simulated behavior is consistent with the first-order expression of $\beta \left(s\right)$ in Table 1, where the low-frequency deviation from unity is governed by the error factors ${\epsilon }_H$ and ${\epsilon }_X$, while the roll-off is mainly associated with the time constant ${\tau }_H$. Therefore, the AC response of Figure 2 confirms that the voltage transfer is the most critical path of the proposed architecture, as already suggested by the simplified small-signal model.

Figure 3 reports the post-layout AC magnitude of the current transfer $\alpha$. As for $\beta$, the marker at 1 Hz highlights the low-frequency conveying accuracy, whereas the $-3$ dB marker provides the current-transfer cutoff $f_{-3\mathrm{dB},\alpha }$. The resulting curve confirms that the conveying action is preserved over the intended operating band. Compared to the voltage transfer, the current transfer typically shows a higher cutoff frequency, as its dominant limitation is mainly set by the internal node parasitics and the finite output conductances of the replication stage. This trend is in agreement with the simplified analytical expression of the $X\to Z$ transfer, where the current gain depends at first order only on ${\epsilon }_X$ and on the pole associated with ${\tau }_X$. Hence, the larger simulated bandwidth of $\alpha$ with respect to $\beta$ is consistent with the fact that the current path is not directly limited by the internal buffer node H, but mainly by the equivalent parasitics and small-signal conductances seen at node X.

To explicitly assess the linearity of the proposed CCII⁻, both DC transfer characteristics and THD-based transient results were considered. In particular, Figure 4a reports $V_X$ versus $V_Y$, showing the monotonic tracking behavior of the $Y\to X$ voltage path and identifying the operating region with the best linearity. Likewise, Figure 4b shows $I_Z$ versus $I_X$ in the $\pm 1$ nA range, confirming the linear current conveying behavior around the quiescent operating point. This analysis is complemented by the THD results reported in

Table 3. Post-layout PVT/corner summary at $V_{DD}=0.3$ V nominal. Process corners: SS/FF/SF/FS. Temperature corners: 0 °C and 80 °C. Supply corners: 270 mV and 330 mV (Values reproduced from the updated simulation corner table).

Metric	Nom.	Process Corners				Temperature Corners		Supply Corners
		SS	FF	SF	FS	0 °C	80 °C	270 mV	330 mV
$P_{DC}$ [nW]	2.388	2.371	2.405	2.383	2.393	2.364	2.435	2.138	2.637
${\beta }_0$ [-]	0.9452	0.9428	0.9447	0.9452	0.9432	0.9406	0.9260	0.9344	0.9502
$f_{-3\mathrm{dB},\beta }$ [kHz]	22.95	22.07	23.95	22.79	23.13	24.75	20.55	22.94	23.00
THDβ [%]	1.004	1.065	0.992	1.003	1.013	1.075	2.160	1.788	0.796
$v_{nY}\left(1\mathrm{kHz}\right)$ [$\mathsf{\mu }$V/$\sqrt{\mathrm{Hz}}$]	2.321	3.216	3.254	3.288	3.187	3.035	3.644	3.293	3.190
${\alpha }_0$ [-]	0.9609	0.9624	0.9594	0.9599	0.9619	0.9620	0.9481	0.9565	0.9639
$f_{-3\mathrm{dB},\alpha }$ [kHz]	63.95	64.59	62.63	63.46	64.44	69.50	57.19	63.98	64.06
THDα [%]	0.1267	0.1212	0.1311	0.1338	0.1206	0.0964	0.2294	0.2148	0.0915
$i_{nX}\left(1\mathrm{kHz}\right)$ [fA/$\sqrt{\mathrm{Hz}}$]	48.2	67.12	67.2	67.04	67.27	66.79	68.35	67.32	67.03
$R_X$ [M$\mathsf{\Omega }$]	46.73	46.26	47.07	47.67	45.79	43.74	51.39	47.05	46.36
$R_Z$ [G$\mathsf{\Omega }$]	1.204	1.247	1.162	1.192	1.216	1.170	1.209	1.096	1.289
$R_Y$ [G$\mathsf{\Omega }$]	392.0	390.8	393.2	392.9	391.1	421.4	8.725	405.0	371.5

, obtained from transient simulations at 100 Hz under different PVT conditions. The DC characteristics are also coherent with the first-order transfer relations of Table 1, since the finite slopes observed in both curves directly reflect the non-zero values of the error factors ${\epsilon }_H$ and ${\epsilon }_X$. In particular, the more evident deviation from ideality in the $V_X$–$V_Y$ characteristic is consistent with the fact that $\beta \left(s\right)$ is affected by both error terms, whereas the $I_Z$–$I_X$ characteristic is mainly influenced by ${\epsilon }_X$.

Finally, the small-signal terminal resistances were extracted as a function of frequency. Figure 5 reports $R_X$, $R_Z$, and $R_Y$ (in G$\mathsf{\Omega }$) together with the annotated values at 1 Hz. The results confirm the intended impedance hierarchy for current-mode operation: $R_X$ is the lowest port resistance (tens of M$\mathsf{\Omega }$), $R_Z$ is a high output resistance (about 1 G$\mathsf{\Omega }$), and $R_Y$ is the highest-impedance input port (hundreds of G$\mathsf{\Omega }$, dominated by the junction/input resistance). Moreover, the curves remain approximately flat across the frequency range of interest, indicating that the port impedances are dominated by DC conductances within the operating band. These extracted values are also consistent with the simplified expressions reported in Table 2. In particular, the relatively large value of $R_X$ confirms one of the main limitations already highlighted by the analytical model, namely the difficulty of realizing a very low-impedance X terminal under ULV weak-inversion biasing. Likewise, the very large $R_Y$ and $R_Z$ values confirm that the proposed architecture preserves the intended CCII impedance hierarchy despite the aggressive power scaling.

Large-signal linearity was also quantified through transient THD simulations at 100 Hz. For the voltage path ($\beta$), a 200 mV_pp sinusoid was applied at port Y and THD was evaluated at the tracked output $V_X$; for the current path ($\alpha$), a 2 nA_pp sinusoidal excitation was applied at port X and THD was evaluated on the replicated current at port Z. The resulting THD values (in %) are included in the corner and Monte Carlo summaries and are also discussed below.

Robustness was assessed by repeating the key tests across process, temperature, and supply corners. Table 3 summarizes the complete set of corner results (SS/FF/SF/FS, 0 °C and 80 °C, and $V_{DD}$ variations at 270 mV and 330 mV). In addition to the low-frequency tracking factors ${\beta }_0$ and ${\alpha }_0$, the table reports the $-3$ dB bandwidths $f_{-3\mathrm{dB},\beta }$ and $f_{-3\mathrm{dB},\alpha }$ extracted from the AC magnitude responses of $V_X/V_Y$ and $I_Z/I_X$, respectively, as well as the corresponding THD levels at 100 Hz and the input-referred noise quantities $v_{nY}$ and $i_{nX}$ evaluated at 1 kHz. Overall, the conveyor preserves correct functionality across all tested conditions, with bandwidths in the tens-of-kHz range, nanowatt DC power, and THD remaining bounded over PVT. From an analytical viewpoint, the corner results further support the interpretation given in Section 3: the voltage path is generally more sensitive than the current path to variations in temperature and supply, consistently with its stronger dependence on bulk-driven transconductance and on the dominant time constant ${\tau }_H$. By contrast, the current transfer remains comparatively more stable, in agreement with the simpler first-order structure of $\alpha \left(s\right)$.

A Monte Carlo (MC) analysis with device mismatch enabled was carried out to quantify the statistical dispersion of the main figures of merit at $V_{DD}=0.3$ V.

Table 4. Monte Carlo summary at $V_{DD}=0.3$ V (mismatch only): min, max, mean, and standard deviation ($\sigma$); median excluded.

Metric	Mean	$\mathit{\sigma }$	Min	Max
$R_X$ [M$\mathsf{\Omega }$]	46.75	1.126	42.88	50.95
$R_Y$ [G$\mathsf{\Omega }$]	392.0	0.330	391.0	393.4
$R_Z$ [G$\mathsf{\Omega }$]	0.9058	0.404	0.0537	1.281
${\beta }_0$ [dB]	$-0.4913$	0.02193	$-0.5917$	$-0.4248$
${\beta }_0$ [–]	0.9450	0.002385	0.9342	0.9523
$f_{-3\mathrm{dB},\beta }$ [kHz]	22.96	0.512	21.12	25.09
${\mathrm{THD}}_{\beta }$ [%]	1.10	0.144	0.960	2.40
${\alpha }_0$ [dB]	$-0.3472$	0.2766	$-1.481$	$+0.6179$
${\alpha }_0$ [–]	0.9613	0.03054	0.8432	1.074
$f_{-3\mathrm{dB},\alpha }$ [kHz]	64.02	2.497	55.46	72.80
${\mathrm{THD}}_{\alpha }$ [%]	0.14	0.05	0.07	0.36
$P_{\mathrm{DC}}$ [nW]	2.389	0.0421	2.226	2.571

summarizes the results by reporting minimum, maximum, mean, and standard deviation ($\sigma$) for each metric (median excluded). In addition to tracking factors and bandwidth, the table includes the THD statistics at 100 Hz for both $\beta$ (200 mV_pp voltage excitation) and $\alpha$ (2 nA_pp current excitation). Overall, the proposed CCII⁻ shows limited variability under mismatch: ${\beta }_0$ remains tightly clustered around its nominal value with modest spread, while ${\alpha }_0$ exhibits a larger dispersion, as expected for ultra-low-voltage operation and mismatch in the current replication path. The THD figures remain bounded and consistent with the DC transfer characteristics of Figure 4. This statistical behavior is again coherent with the first-order analytical model. In particular, the larger dispersion observed for ${\alpha }_0$ is consistent with the sensitivity of the current path to the small-signal parameters of the output branch, whereas the relatively limited spread of ${\beta }_0$ indicates that, although the voltage path is dynamically slower, its low-frequency tracking remains sufficiently controlled under mismatch. Thus, the Monte Carlo results confirm that the simplified analysis captures the main sensitivity trends of the proposed architecture, even if it is not intended as a full statistical model.

Overall, the combined PVT and MC results indicate that the conveyor maintains the intended operating point and dynamic behavior under realistic integrated constraints. The voltage path ($\beta$) shows a tightly bounded low-frequency gain and bandwidth, while the current path ($\alpha$) remains robust with moderate mismatch-induced spread. Importantly, both THD metrics remain limited at 100 Hz under nominal and corner conditions, supporting the suitability of the proposed CCII⁻ for ultra-low-power, kHz-range sensor-interface front-ends.

5. Application Example: Reconfigurable Filter

In order to further demonstrate the practical usefulness of the proposed CCII⁻, a reconfigurable filter application has been considered. The adopted topology, inspired to the one adopted in [23] and shown in Figure 6, employs a single current conveyor together with two resistors and two capacitors, and allows the realization of different transfer characteristics by properly selecting the excitation node among $V_1$, $V_2$, and $V_3$. This example enables the evaluation of the impact of the non-ideal conveyor parameters on a realistic signal-processing block, thereby complementing the standalone characterization of the active element.

Assuming ideal CCII⁻ behavior ($V_X=V_Y$, $I_Z=-I_X$, $I_Y=0$), the transfer function can be derived by writing the current balance at node X. For the sake of clarity and compactness, the analytical expressions are derived under the simplifying assumptions $C_1=C_2=C$ and $R_1=R_2=R$. Under these conditions, the resulting second-order transfer function can be written as

$$H\left(s\right)={\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{N\left(s\right)}{s^2{C}^2{R}^2+sCR+1}},$$

(9)

where the numerator $N\left(s\right)$ depends on the selected excitation node.

In particular, when the input signal is applied to $V_2$ while $V_1$ and $V_3$ are grounded, the circuit behaves as a low-pass filter, with transfer function

$$H_{\mathrm{LP}}\left(s\right)={\displaystyle \frac{1}{D\left(s\right)}}.$$

(10)

Conversely, when the input is applied to $V_1$ with $V_2=V_3=0$, a high-pass response is obtained, given by

$$H_{\mathrm{HP}}\left(s\right)={\displaystyle \frac{s^2{C}^2{R}^2}{D\left(s\right)}}.$$

(11)

Finally, when the excitation is applied to $V_3$ with $V_1=V_2=0$, the circuit provides a band-pass response, which can be expressed as

$$H_{\mathrm{BP}}\left(s\right)={\displaystyle \frac{sCR}{D\left(s\right)}},$$

(12)

where the common denominator is

$$D\left(s\right)=s^2{C}^2{R}^2+sCR+1.$$

Therefore, the same passive network can be reconfigured to implement low-pass, high-pass, or band-pass filtering by simply selecting the active input node, while grounding the remaining two terminals.

The component values were selected to obtain a cutoff frequency around 100 Hz, consistently with the low-frequency operating range targeted by the proposed ultra-low-voltage and nanowatt CCII⁻.

Figure 7 reports the simulated magnitude responses for the three configurations. The obtained curves clearly exhibit the expected low-pass, band-pass, and high-pass behaviors, confirming that the proposed CCII⁻ remains functionally effective even in the presence of non-ideal tracking factors ${\alpha }_0$ and ${\beta }_0$.

To further evaluate the large-signal behavior of the application circuit, the total harmonic distortion (THD) was analyzed by applying a 1 Hz sinusoidal input while sweeping its amplitude in the low pass filter configuration. The corresponding results are shown in Figure 8. The THD remains close to $1\%$ over a wide input-amplitude range and increases more noticeably only at higher signal levels, where the limited voltage headroom and the non-ideal transfer characteristics of the conveyor become more critical. This behavior is consistent with the ultra-low-voltage operating regime of the proposed circuit.

In order to further validate the operation in the time domain, the output waveform is reported in Figure 9. The output signal closely follows the expected filtered waveform and remains substantially sinusoidal. Only limited distortion is observed, in agreement with the THD results. The slight deviation from ideal behavior can be mainly attributed to the finite values of ${\alpha }_0$ and ${\beta }_0$, as well as to the reduced voltage headroom imposed by the $0.3$ V supply.

Overall, the combined frequency-domain, distortion, and time-domain results demonstrate that the proposed CCII⁻ can be effectively employed in practical low-frequency filtering applications. Despite its ultra-low-voltage and nanowatt operation, the circuit preserves the expected qualitative behavior and maintains acceptable signal fidelity within the intended operating range, thus supporting its suitability for energy-constrained sensor-interface applications.

6. Comparison with the Literature

Table 5. Comparison with representative CCII implementations. “Meas.” indicates whether the results are experimentally measured (Yes) or simulation-based (No), as reported in the corresponding reference.

Work	Meas.	Node [nm]	${\mathit{V}}_{\mathbf{DD}}$ [V]	${\mathit{P}}_{\mathit{D}}$ [nW]	${\mathit{\alpha }}_{\mathbf{0}}$ [–]	${\mathit{\beta }}_{\mathbf{0}}$ [–]	${\mathit{f}}_{\mathbf{-}\mathbf{3}\mathbf{dB}\mathbf{,}\mathit{\alpha }}$ [kHz]	${\mathit{f}}_{\mathbf{-}\mathbf{3}\mathbf{dB}\mathbf{,}\mathit{\beta }}$ [kHz]	${\mathit{R}}_{\mathit{X}}$ [k$\mathsf{\Omega }$]	${\mathit{R}}_{\mathit{Y}}$ [G$\mathsf{\Omega }$]	${\mathit{R}}_{\mathit{Z}}$ [M$\mathsf{\Omega }$]	FoM [dB]
This Work	No	180	0.30	2.388	0.9609	0.9452	63.95	22.95	46730	392	1204	15.88
[7]	Yes	180	0.30	19	0.999	0.9987	4.1	39.2	56	0.703	94.7	30.13
[24]	No	65	0.35	1000	0.9995	0.9998	1330	2130	1.8	190	7.46	5.38
[22]	No	350	1.5	150	0.994	0.9	4400	4600	0.052	N.A.	7.00	–23.54
[7]	Yes	180	0.50	40	0.999	0.999	578	56.4	3	0.664	8.00	24.95

compares the proposed CCII⁻ with representative low-voltage and ultra-low-power current conveyors reported in the literature. The comparison highlights the trade-off among supply voltage, DC power dissipation, conveying accuracy (${\alpha }_0$ and ${\beta }_0$), small-signal bandwidth, and port-impedance hierarchy ($R_Y\gg R_X$ and $R_Z\gg R_X$). For consistency with the rest of this manuscript, ${\alpha }_0$ and ${\beta }_0$ are reported in linear scale (low-frequency values), while $f_{-3\mathrm{dB},\alpha }$ and $f_{-3\mathrm{dB},\beta }$ denote the corresponding $-3$ dB bandwidths. When a quantity is not explicitly reported by the reference, it is marked as N.A.

In order to provide a more compact comparison among the considered designs, a Figure of Merit (FoM) is also introduced. The adopted FoM is intended as a comparative indicator that jointly accounts for power dissipation and conveying accuracy and is defined as

$$\mathrm{FoM}\left[\mathrm{dB}\right]=20{log}_{10}\left({\displaystyle \frac{1}{\left(P_D/P_{\mathrm{ref}}\right)\sqrt{{(1-{\alpha }_0)}^2+{(1-{\beta }_0)}^2}}}\right),P_{\mathrm{ref}}=1\mathrm{nW}.$$

(13)

According to (13), the FoM rewards solutions featuring lower power consumption and current/voltage transfer gains closer to unity. It is worth noting that this FoM is not intended as a universal performance metric but rather as a useful comparative parameter for the class of works considered in this paper.

From the power standpoint, the proposed design achieves nanowatt-level dissipation at $V_{DD}=0.3$ V (2.388 nW). This is significantly lower than the measured 0.3 V bulk-driven solution in [7], and orders of magnitude below designs targeting much higher bandwidth, such as [22,24]. As expected, this aggressive power reduction comes with a more pronounced degradation of the tracking factors: while [7] reports ${\alpha }_0\approx 0.999$ and ${\beta }_0\approx 0.9987$ at 0.3 V, the proposed CCII⁻ exhibits ${\alpha }_0=0.9609$ and ${\beta }_0=0.9452$, which reflects the limited transconductance available at few-nW bias currents and the stronger impact of device mismatch and parasitics at ULV.

The FoM values reported in Table 5 summarize the trade-off between power consumption and transfer accuracy in a compact form. In particular, the proposed design does not maximize the adopted FoM, since its extremely low-power operating point is obtained at the expense of non-ideal tracking factors. Nevertheless, the FoM remains useful to show how the presented solution is positioned within the considered design space, namely as an extreme nanowatt CCII⁻ optimized for minimum energy consumption rather than for best overall accuracy. In particular, the proposed design achieves an FoM of 15.88 dB, which is lower than the 30.13 dB reported for the measured 0.3 V bulk-driven solution in [7], and also lower than the 24.95 dB obtained for the corresponding 0.5 V operating point of the same architecture. At the same time, the proposed design still compares favorably with higher-power solutions such as [22,24] under the adopted normalization and accuracy criterion.

In terms of small-signal speed, the bandwidths of the proposed CCII ($f_{-3\mathrm{dB},\alpha }=63.95$ kHz and $f_{-3\mathrm{dB},\beta }=22.95$ kHz) remain compatible with low-frequency sensor interfaces and current-mode signal conditioning while staying consistent with the intended nanowatt operation. Conversely, the higher-power solutions [22,24] achieve MHz-range bandwidths by allocating substantially larger bias current (and therefore power), characteristic of the classic ULV trade-off between speed and energy budget. The measured 0.5 V operating point reported in [7] further confirms this trend: at the cost of higher supply and DC power, bandwidth and accuracy improve.

Finally, port resistances underline a key system-level aspect often overlooked by comparisons based solely on ${\alpha }_0$ and ${\beta }_0$. The proposed CCII⁻ realizes a very large input resistance at port Y ($R_Y=392$ G$\mathsf{\Omega }$) together with a high output resistance at port Z ($R_Z=1.204$ G$\mathsf{\Omega }$), supporting current-mode operation with minimal loading of high-impedance sensing nodes. At the same time, the comparatively large $R_X$ (46.73 M$\mathsf{\Omega }$) is a direct consequence of ULV, weak-inversion biasing, and represents the primary impedance-related limitation of the presented operating point.

7. Conclusions

This paper presented a post-layout verified CCII⁻ optimized for ultra-low-voltage and nanowatt operation in a 0.18-$\mathsf{\mu }$m TSMC CMOS technology. The circuit was designed to operate from a single $V_{DD}=0.3$ V supply while preserving the CCII⁻ functional relations through a bulk-driven, weak-inversion bias strategy and a port-impedance hierarchy suitable for current-mode interfaces. Post-layout extracted simulations confirm correct conveying behavior with a total DC power consumption of $P_{\mathrm{DC}}=2.388$ nW at nominal conditions. The low-frequency tracking factors measured at 1 Hz are ${\beta }_0=V_X/V_Y=0.9452$ (i.e., $-0.48$ dB) and ${\alpha }_0=I_Z/I_X=0.9609$ (i.e., about $-0.35$ dB). The corresponding $-3$ dB bandwidths are $f_{-3\mathrm{dB},\beta }=22.95$ kHz for the $Y\to X$ voltage transfer and $f_{-3\mathrm{dB},\alpha }=63.95$ kHz for the $X\to Z$ current transfer, demonstrating kHz-range operation consistent with the targeted ULV/nW regime. Small-signal resistance extraction further validates the intended port behavior: the X port exhibits $R_X=46.73$ M$\mathsf{\Omega }$, the Z port provides a high output resistance $R_Z=1.204$ G$\mathsf{\Omega }$, and the Y port shows an extremely large input resistance $R_Y=392$ G$\mathsf{\Omega }$, dominated by the reverse-biased junction input resistance at the bulk-driven input. Monte Carlo mismatch analysis indicates limited statistical spread of the main metrics, with $\sigma \left(P_{\mathrm{DC}}\right)=0.00622$ nW, $\sigma \left(R_X\right)=0.3115$ M$\mathsf{\Omega }$, $\sigma \left(R_Y\right)=0.4656$ G$\mathsf{\Omega }$, $\sigma \left(R_Z\right)=0.00954$ G$\mathsf{\Omega }$, and $\sigma \left({\beta }_0\right)=6.48\times {10}^{-4}$ (linear). Finally, the conveyor preserves functional behavior across PVT variations.

The presented results also show that the proposed CCII⁻ can be effectively employed in practical low-frequency applications. In particular, the reconfigurable filter case study confirms the correct realization of low-pass, band-pass, and high-pass responses in the target frequency range, while the corresponding time-domain and THD results indicate acceptable signal fidelity under realistic loading conditions. The obtained results further confirm the main trade-offs of the proposed solution, namely non-ideal tracking accuracy, kHz-range bandwidth, and a relatively large $R_X$, which are the price paid for operation at $0.3$ V with nanowatt power dissipation. In this sense, the proposed CCII⁻ is best suited for ultra-low-power sensor interfaces and always-on analog front-ends, where minimum energy budget is a dominant design requirement. Possible future developments may include improvements of the current replication and voltage-buffer sections to enhance $\alpha$ and $\beta$, reduce $R_X$, and extend the usable bandwidth, as well as further application-level investigations in complete low-power readout circuits.

Overall, the proposed CCII⁻ demonstrates that robust current-mode conveying can be achieved at $0.3$ V with nanowatt power dissipation in a 180 nm CMOS process, making the circuit a suitable building block for ultra-low-power sensor interfaces and always-on analog front-ends where energy budget and input loading are dominant design constraints.