Current-Mode Quadrature Oscillator Simple Designs

Abstract

Simple designs of current-mode quadrature oscillators are presented in this work. The main achievement, with regards to the literature, is the minimization of the required transistor count accomplished by the utilization of a suitable lossless integration stage. The derived post-layout simulation results confirm the validity of the presented concept and show that the resulting structure has attractive characteristics in both frequency and time-domain.

1. Introduction

Quadrature oscillators are defined as the oscillators which provide outputs with 90° phase difference and they are employed in various important applications, such as in single side-band generators, in telecommunications for quadrature mixer, for generating signal in instrumentation and measurement systems. Implementations of quadrature oscillators using the concept of current-mode signal processing have been already reported in the literature. The implementations in [1,2,3,4,5,6,7,8,9,10] are constructed from bipolar transistors, while MOS transistors are employed in the realization presented in [11,12,13,14,15,16,17,18,19,20,21].

This work is focused on the MOS implementation of quadrature oscillator. The main problem in most of the already available oscillator implementations is the increased number of transistors and this is originated from the fact that they are utilized for the realization of complicated active cells, such as Current Differencing Transconductance Amplifiers, Voltage Differencing Current Conveyors, Current Follower Current Conveyors, Current-Controlled Current Differencing Transconductance Amplifiers, Voltage Differencing Gain Amplifiers and Voltage Differencing Buffered Amplifiers.

The simplest structure is that in [11], where current-mirror based implementation of the required lossless integration stages are introduced. This is achieved by adding an extra current-mirror in the topology of the lossy integration stage, which feds the output current back to the input. Although current-mirrors are very promising cells for implementing current-mode signal processing [22,23,24,25,26,27,28,29,30,31,32,33,34], this approach faces challenges, such as increased sensitivity due to the transistor matching requirements in the additional current mirror, as well as a limited maximum operating frequency caused by the cascaded extra stage.

A simpler lossless integration stage is recently introduced in [35], where the required lossless integration operation is performed by adding just one bias current source in the topology of the lossy integrator. Following this, the aforementioned obstacles are overcome opening the door for solutions with circuit complexity minimization and, also, significant reduction of the power dissipation.

The contribution made at this work is that novel current-mode quadrature oscillator topologies are presented which offer the minimum number of the required transistors with regards to the literature. This is achieved through the utilization of the concept introduced in [35].

The work is organized as follows: the integration stages are discussed in Section 2. The proposed oscillator topologies are introduced in Section 3, where comparison with the literature is also performed. The layout of the simplest presented topology is given in Section 4 and, using the Cadence IC design suite results about the frequency and time-domain behavior of the oscillator are provided in this Section. The main findings of this work are summarized in Section 5.

2. Current-Mode Integration Stages Based on Current-Mirrors

Considering the typical current-mirror structure in Figure 1a, the low-frequency input impedance of this stage ($Z_{in}$) is equal to $1/g_{m1}$, with $g_{m1}$ being the small-signal transconductance parameter of the diode-connected transistor M_n1 and neglecting its output impedance [22,23,25,29]. The input current $i_{in}$ is converted into a voltage ${\upsilon }_{in}=i·Z_{in}$ by transistor M_n1 and this voltage is converted back into a current by transistor M_n2, according to the formula: $i_{out}=g_{m2}{\upsilon }_{in}$. Assuming that M_n1–M_n2 are matched, the topology acts as a unity gain current-mirror. These operations are described by the small-signal equivalent depicted in Figure 1b.

Adding a capacitor $C_1$ at the input of the stage, as it is shown in Figure 2a, the input impedance becomes: $Z_{in}=(1/g_{m1})//(1/C_{1}s)$ and the structure realizes a lossy integrator (i.e., a first-order unity gain low-pass current transfer function) with cut-off frequency (${\omega }_c$) given by the formula: ${\omega }_c=g_{m1}/C_1$, as it is derived from the small-signal equivalent in Figure 2b [22,23,25].

The realization of a lossless integration stage could be performed through the concept presented in Figure 3a,b. Performing a routine analysis in Figure 3a, it is readily obtained that: $i_{in}+i_1=i_1$; this condition is only fulfilled for $i_{in}=0$, making the input impedance to be infinity. In other words, this technique is based on the neutralization of the resistance $1/g_{m1}$, by establishing in parallel a negative resistance equal to $-1/g_{m1}$. This is demonstrated in Figure 3b. It should be noted that the aforementioned transistor-level method is valid only if transistors M_n1–M_n2 and M_n3–M_n4 are matched, i.e., $g_{m1}=g_{m2}$ and $g_{m3}=g_{m4}$.

Moreover, the addition of a capacitor $C_1$ at the input of the stage, as it is shown in Figure 4, makes it to behave as a lossless integration stage with the time-constant given by the formula: $\tau =C_1/g_{m2}$, provided that $g_{m1}=g_{m2}=g_{m3}$ and $g_{m4}=g_{m5}$ [22,23].

Another way for implementing a lossless integrator is by establishing an open circuit in the path of the resistor $1/g_{m1}$. This concept has been introduced in [35] and is demonstrated in Figure 5a. Due to the addition of the extra current source $I_0$ in the input branch, the current that flows through M_n1 during the small-signal operation is equal to zero and from the equivalent in Figure 5b it is readily derived that the input impedance of the topology becomes equal to $1/C_{1}s$, because the resistor $1/g_{m1}$ is floating.

The input voltage is

$${\upsilon }_{in}={\displaystyle \frac{i_{in}}{C_{1}s}},$$

(1)

and, taking into account that the output current is given by the formula: $i_{out}=g_{m2}{\upsilon }_{in}$, the resulting expression of the realized transfer function is

$$H\left(s\right)\equiv {\displaystyle \frac{i_{out}}{i_{in}}}={\displaystyle \frac{1}{(C_1/g_{m2})s}},$$

(2)

making the associated time constant to be

$$\tau ={\displaystyle \frac{C_1}{g_{m2}}}.$$

(3)

Inspecting the topologies in Figure 2, Figure 4 and Figure 5, the following conclusions could be obtained:

(a)

The topology in Figure 5 is derived from that in Figure 2, just by adding an extra current source.

(b)

The component count in the topology in Figure 5 is significantly reduced with regards to that in Figure 4.

(c)

The power dissipation of the integrator in Figure 4 equals to $5\left(V_{DD}-V_{SS}\right)I_0$, while in Figure 5 the dissipation is $\left(V_{DD}-V_{SS}\right)\left(I_B+I_0\right)$.

(d)

There is not any matching requirement between the transistors M_n1 − M_n2, in contrast to the topology in Figure 5. The reason is that, under the assumption that the capacitor is initially discharged, the value of the voltage at the common-gate connection of M_n1 − M_n2 is equal to zero. Therefore, the gate-source voltage of M_n2 becomes equal to $-V_{SS}$, making its transconductance to be: $g_{m2}=2I_0/\mid V_{SS}\mid$ offering linear dependence from the current $I_0$.

The aspect ratio of M_n1 is chosen in such a way that there will be a suitable headroom voltage, for a given value of $I_B$, available for the operation of the current source which is connected at its source terminal.

3. Proposed Sinusoidal Quadrature Oscillator

The Functional Block Diagram (FBD) of a current-mode sinusoidal quadrature oscillator, constructed from a two-integrator loop is depicted in Figure 6. As the open-loop gain is given by the formula: $L\left(s\right)=-1/\left({\tau }_1{\tau }_2{s}^2\right)$, it is readily obtained that the topology unconditionally oscillates at frequency (${\omega }_0$=$2\pi f_0$)

$$f_0={\displaystyle \frac{1}{2\pi \sqrt{{\tau }_1{\tau }_2}}}.$$

(4)

The implementation of the FBD in Figure 6 can be performed using the lossless integration stage presented in Figure 7.

The resulting expression of the oscillation frequency is

$$f_0={\displaystyle \frac{g_{m2}{g}_{m5}}{2\pi \sqrt{C_1{C}_2}}}.$$

(5)

According to the analysis provided in [35], the open-loop gain of the integrator is

$$L^{\prime }\left(s\right)={\displaystyle \frac{g_{m2}{g}_{m5}{(r_{ds,n}//r_{ds,p})}_1{(r_{ds,n}//r_{ds,p})}_4}{[{(r_{ds,n}//r_{ds,p})}_1{C}_{1}s+1]·[{(r_{ds,n}//r_{ds,p})}_4{C}_{2}s+1]}},$$

(6)

with ${(r_{ds,n}//r_{ds,p})}_i$ ($i=1,4$) being the output resistances of the MOS transistors which implement the current sources associated with the transistors M_n1 and M_n4, respectively. According to (6), the system behaves as cascade connection of two first-order low-pass filter functions with cut-off frequencies given by the formulas: ${\omega }_{c1}=1/{(r_{ds,n}//r_{ds,p})}_1{C}_1$ and ${\omega }_{c2}=1/{(r_{ds,n}//r_{ds,p})}_4{C}_2$, respectively. At the high frequency range (i.e., $\omega >>{\omega }_c$) both the intermediate stages behave as pure lossless integrators and, consequently, the designer must take care of realizing accurate current-mirrors [28,30,36,37,38] in order the oscillation frequency to be unaltered.

Another possible implementation of the oscillator is that demonstrated in Figure 8, where the core of the second integrator is realized by the pair of M_p1 − M_p2 pMOS transistors. Inspecting the topologies in Figure 7 and Figure 8, it is readily obtained the reduction of the number of the required bias current sources, as 10 are employed in Figure 7 and 6 in Figure 8. The price paid for this achievement is that the maximum frequency of operation is reduced and this is originated from the reduced mobility of the pMOS transistors, with regards to their nMOS transistors.

The performance of the realized oscillator is compared with that offered by the corresponding CMOS-based current-mode implementations published in the literature. According to the results provided in

Table 1. Performance comparison results of the lossless oscillators in Figure 7 and Figure 8.

Topology	No. of Active Elements	No. of Transistors	Resistors	Independent Control of O.C. 7 and O.F. 8	Electronic Tunability
[13]	3 CDTA 1	69	—	yes	yes
[14]	1 CDTA 1	47	1	yes	yes
[18]	2 VDCC 2	60	2	yes	yes
[16]	2 CFCC 3	104	5	yes	no
[19]	2 VDCC 2	60	3	yes	yes
[12]	2 CCCDTA 4	70	—	yes	yes
[20]	1 VDGA 5	27	1	yes	yes
[21]	4 CDTA 1	116	—	yes	yes
[15]	2 VDBA 6	44	1	yes	yes
[17]	2 CCFTA 1	70	—	yes	yes
[11]	—	22	—	no	yes
Figure 7	—	18	—	yes	yes
Figure 8	—	14	—	yes	yes

¹ CDTA: Current Differencing Transconductance Amplifier. ² VDCC: Voltage Differencing Current Conveyor. ³ CFCC: Current Follower Current Conveyor. ⁴ CCCDTA: Current-Controlled Current Differencing Transconductance Amplifier. ⁵ VDGA: Voltage Differencing Gain Amplifier. ⁶ VDBA: Voltage Differencing Buffered Amplifier. ⁷ O.C.: Oscillation Condition. ⁸ O.F.: Oscillation Frequency.

, the presented topologies offer minimization of the circuit complexity with regards to the literature, with that in Figure 8 being the most economical one.

4. Simulation Results

The behavior of the proposed oscillator shown in Figure 8 is analyzed using the Cadence IC design suite with the Design Kit provided by the AMS CMOS 0.35 μm process design kit. The aspect ratios of the nMOS and pMOS transistors M_n1 − M_n6 and M_p1 − M_p2 are 1 μm/10 μm and 4 μm/10 μm, respectively. The circuit operates with a supply voltage of $V_{DD}$ = $-V_{SS}$ = 1.5 V, while $I_B$ = 1 μA and $I_0$ = 5.84 μA. The distribution of the dc bias currents $I_B$ and $I_0$ is performed through the utilization of the scheme in Figure 9, where the aspect ratios of M_bn1 and M_bp1 are 1 μm/10 μm and 8 μm/15 μm, respectively, while the scale factor k is equal to $I_0/I_B$. The capacitances are set to $C_1$ = $C_2$ = 7.43 pF in order to achieve an oscillation frequency of 250 kHz. The layout design of the topology in Figure 8 is depicted in Figure 10, with the dimensions being 168 μm × 138 μm.

Considering the open-loop configuration of the oscillator, its gain response is depicted in Figure 11a with the simulated value of the unity-gain frequency (which is also the oscillation frequency) being equal to 251.1 kHz. The sensitivity performance of the proposed oscillator is evaluated using the Monte-Carlo analysis tool, for $N=500$ runs. The resulting statistical histogram of the open-loop unity-gain frequency is given in Figure 11b, where the value of the standard deviation, derived by considering the effects of both the process parameters variation and MOS transistors parameters mismatching, is 17.5 kHz. As the mean value is 251.1 kHz, it is concluded that the oscillator has reasonable sensitivity characteristics.

The time-domain post-layout results of the current outputs are given in Figure 12, where the oscillation frequency and the phase difference between the outputs being 251.1 kHz and 87.1°, close to the theoretical values 250 kHz and 90°, respectively.

The Total Harmonic Distortion (THD) is measured equal to 3.78% for the first output and 4% for the second one, using Periodic Steady-State (PSS) analysis offered by the IC design Cadence suite.

As next step, the phase noise of both outputs is evaluated and the resulting plots are provided in Figure 13. The values of the spot phase noise at $2f_0$ and $3f_0$ are 3.44 pA/$\sqrt{\mathrm{Hz}}$ and 22.89 pA/$\sqrt{\mathrm{Hz}}$ for $i_{out1}$ and 4.19 pA/$\sqrt{\mathrm{Hz}}$ and 23.51 pA/$\sqrt{\mathrm{Hz}}$ for $i_{out2}$, respectively.

5. Conclusions

The presented oscillator topology offers significant reduction of the required circuit complexity, with regards to the literature. This is achieved through the realization of a slightly modified version of the simple lossy integration stage, avoiding the conventional way where an extra feedback path must be added for neutralizing the small-signal equivalent resistance of diode connected transistor. The layout design of the presented topology is demonstrated and the obtained post-layout simulation results in both frequency and time-domain confirm that the scheme has reasonable performance in terms of accuracy, sensitivity, and linearity. Consequently, it is an attractive candidate for implementing analog signal processing systems, where the demand of reduced low power dissipation is crucial.