Special Issue "Image Processing Using FPGAs"

A special issue of Journal of Imaging (ISSN 2313-433X).

Deadline for manuscript submissions: 30 November 2018

Special Issue Editor

Guest Editor
Prof. Donald Bailey

School of Engineering and Advanced Technology, Massey University, Palmerston North 4442, New Zealand
Website | E-Mail
Interests: machine vision; FPGA based design; digital image processing

Special Issue Information

Dear Colleagues,

Field Programmable Gate Arrays (FPGAs) are increasingly being used for the implementation of image processing applications. This is especially the case for real-time embedded applications, where latency and power are important consideration. An FPGA embedded in a smart camera is able to perform much of the image processing directly as the image is streamed from the sensor, providing a processed data stream, rather than images. The parallelism of hardware is able to exploit the spatial and temporal parallelism implicit within many image processing tasks. Unfortunately, simply porting a software algorithm onto an FPGA often gives disappointing results, because many image processing algorithms have been optimised for a serial processor. It is usually necessary to transform the algorithm to efficiently exploit the parallelism and resources available on an FPGA. This can lead to novel algorithms and hardware computational architectures, both at the image processing operation level and also the application level.

The aim of this Special Issue is to present and highlight novel algorithms, architectures, techniques and applications of FPGAs for image processing.

Prof. Donald Bailey
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Imaging is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) is waived for well-prepared manuscripts submitted to this issue. Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Hardware algorithms for imaging
  • Computational imaging architectures
  • Reconfigurable image processing systems
  • Parallel image processing
  • Hardware acceleration for imaging applications
  • FPGA based smart cameras

Published Papers (1 paper)

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Research

Open AccessArticle Accelerating SuperBE with Hardware/Software Co-Design
J. Imaging 2018, 4(10), 122; https://doi.org/10.3390/jimaging4100122
Received: 11 September 2018 / Revised: 29 September 2018 / Accepted: 16 October 2018 / Published: 18 October 2018
PDF Full-text (1830 KB) | HTML Full-text | XML Full-text
Abstract
Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall
[...] Read more.
Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for simplicity and reducing computational complexity while maintaining state-of-the-art levels of accuracy. We explore both software and hardware acceleration opportunities, converting the original algorithm into a greyscale, integer-only version, and using Hardware/Software Co-design to develop hardware acceleration components on FPGA fabric that assist a software processor. We achieved a 4.4× speed improvement with the software optimisations alone, and a 2× speed improvement with the hardware optimisations alone. When combined, these led to a 9× speed improvement on a Cyclone V System-on-Chip, delivering almost 38 fps on 320 × 240 resolution images. Full article
(This article belongs to the Special Issue Image Processing Using FPGAs)
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Planned Papers

The below list represents only planned manuscripts. Some of these manuscripts have not been received by the Editorial Office yet. Papers submitted to MDPI journals are subject to peer-review.

Topic: Architectures (FPGA) of Visual Lossless CODECs Based on JND Functions
Author: Sven Simon
Affiliation: Institute for Parallel and Distribute Systems (IPVS), Universitat Stuttgart, Germany

Title: FPGA-based Processor Acceleration for Image Processing Applications
Authors: Fahad Manzoor Siddiqui, Moslem Amiri, Umar Ibrahim Minhas, Tiantai Deng, Roger Woods, Karen Rafferty and Daniel Crookes
Affiliation: School of Electronics, Electrical Engineering and Computer Science, Queen's University Belfast, UK
Abstract: Embedded image processing systems presents challenges in terms of computing resources and energy. The paper describes an approach based on an FPGA-based processor called IPPro which can operate up to 337 MHz on Xilinx FPGA families and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on a Xilinx FPGA-based Zedboard. A number of options were explored giving a speedup of 8 for the k-means clustering using 16 IPPros, and a speedup of 9.6 for the morphology operation of the traffic sign recognition using 16 IPPros when compared to ARM-based software implementations. We show that for k-means clustering, the 8 IPPro version gives a design that is 9.6 times more power efficient than a modern GPU implementation.

Title: Customizable Hardware Architectures for Shape- and Feature-Based Object Recognition
Authors: Gundolf Kiefer and Michael Schäferling
Affiliation: Efficient Embedded Systems Lab, Faculty of Computer Science, University of Applied Sciences Augsburg, Germany
Abstract: With the upcoming expected end of Moore's Law, major enhancements in performance and energy consumption of complex algorithms are no longer possible with standard processors alone and increasingly require specialized hardware. The optical recognition of objects under difficult conditions regarding lighting, noise or partial occlusions is a frequently required task in many computer vision applications. This paper reviews a variety of image processing operations related to object and shape recognition together with their optimized FPGA implementations. Several architectural aspects, benefits and trade-offs for using FPGAs are presented and discussed. The operations include feature detection using the SURF point features and variations of the Hough Transform including the Generalized Hough Transform. These operations have been integrated into complete image processing systems using a common framework (ASTERICS).

Author: John Morris
Affiliation: The University of Auckland, New Zealand

Author: Hayden So
Affiliation: Hong Kong University

Title: Using the Hough Transform to Automatically Detect and Correct Lens Distortion
Authors: Donald Bailey, Yuan Chang and Steven Le Moan
Affiliation: Massey University, Palmerston North, New Zealand
Abstract: Lens distortion is a common artefact associated with low cost and wide angle lenses. Image quality (both subjective for metrology) requires a calibration procedure to characterise the distortion, enabling it to be removed. The automatic calibration procedure proposed in this article detects curved lines within the image using a Hough transform, and uses the shape of the peak pattern in the Hough domain to identify the distortion characteristics. These enable the parameters of a first order distortion model to be directly calculated, enabling the distortion to be removed from the output image. The proposed design is realised using a low cost commodity FPGA (an Intel Cyclone V), producing corrected images (1024 × 768 resolution) at 60 frames per second.

Author: Andreas G. Andreou
Affiliation: Johns Hopkins University, USA

Author: Lindsay Kleeman
Affiliation: Monash University, Australia

Author: Muhammad Bilal
Affiliation: King Abdulaziz University, Jeddah, Saudi Arabia

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