Next Article in Journal
Macrosight: A Novel Framework to Analyze the Shape and Movement of Interacting Macrophages Using Matlab®
Next Article in Special Issue
Efficient FPGA Implementation of Automatic Nuclei Detection in Histopathology Images
Previous Article in Journal
Comparison of Piezoelectric and Optical Projection Imaging for Three-Dimensional In Vivo Photoacoustic Tomography
Previous Article in Special Issue
Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing
Article Menu

Article Versions

Export Article

Open AccessArticle
J. Imaging 2019, 5(1), 16; https://doi.org/10.3390/jimaging5010016

FPGA-Based Processor Acceleration for Image Processing Applications

1
School of Electronics, Electrical Engineering and Computer Science, Queen’s University Belfast, Belfast BT7 1NN, UK
2
School of Computing, Electronics and Maths, Coventry University, Coventry CV1 5FB, UK
These authors contributed equally to this work.
*
Author to whom correspondence should be addressed.
Received: 27 November 2018 / Revised: 23 December 2018 / Accepted: 7 January 2019 / Published: 13 January 2019
(This article belongs to the Special Issue Image Processing Using FPGAs)
PDF [2329 KB, uploaded 13 January 2019]

Abstract

FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively.
Keywords: FPGA; hardware acceleration; processor architectures; image processing; heterogeneous computing FPGA; hardware acceleration; processor architectures; image processing; heterogeneous computing
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
SciFeed

Share & Cite This Article

MDPI and ACS Style

Siddiqui, F.; Amiri, S.; Minhas, U.I.; Deng, T.; Woods, R.; Rafferty, K.; Crookes, D. FPGA-Based Processor Acceleration for Image Processing Applications. J. Imaging 2019, 5, 16.

Show more citation formats Show less citations formats

Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Related Articles

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
J. Imaging EISSN 2313-433X Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top