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J. Imaging 2018, 4(12), 138;

Border Handling for 2D Transpose Filter Structures on an FPGA

School of Engineering and Advanced Technology, Massey University, Palmerston North 4442, New Zealand
Author to whom correspondence should be addressed.
Received: 31 October 2018 / Revised: 20 November 2018 / Accepted: 21 November 2018 / Published: 26 November 2018
(This article belongs to the Special Issue Image Processing Using FPGAs)
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It is sometimes desirable to implement filters using a transpose-form filter structure. However, managing image borders is generally considered more complex than it is with the more commonly used direct-form structure. This paper explores border handling for transpose-form filters, and proposes two novel mechanisms: transformation coalescing, and combination chain modification. For linear filters, coefficient coalescing can effectively exploit the digital signal processing blocks, resulting in the smallest resources requirements. Combination chain modification requires similar resources to direct-form border handling. It is demonstrated that the combination chain multiplexing can be split into two stages, consisting of a combination network followed by the transpose-form combination chain. The resulting transpose-form border handling networks are of similar complexity to the direct-form networks, enabling the transpose-form filter structure to be used where required. The transpose form is also significantly faster, being automatically pipelined by the filter structure. Of the border extension methods, zero-extension requires the least resources. View Full-Text
Keywords: stream processing; image borders; window filters; pipeline stream processing; image borders; window filters; pipeline

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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

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Bailey, D.G.; Ambikumar, A.S. Border Handling for 2D Transpose Filter Structures on an FPGA. J. Imaging 2018, 4, 138.

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