Next Article in Journal
An Overview of Watershed Algorithm Implementations in Open Source Libraries
Next Article in Special Issue
Border Handling for 2D Transpose Filter Structures on an FPGA
Previous Article in Journal
Signed Real-Time Delay Multiply and Sum Beamforming for Multispectral Photoacoustic Imaging
Article Menu
Issue 10 (October) cover image

Export Article

Open AccessArticle
J. Imaging 2018, 4(10), 122;

Accelerating SuperBE with Hardware/Software Co-Design

Embedded Systems Research Group, Department of Electrical and Computer Engineering, The University of Auckland, Auckland 1023, New Zealand
Author to whom correspondence should be addressed.
Received: 11 September 2018 / Revised: 29 September 2018 / Accepted: 16 October 2018 / Published: 18 October 2018
(This article belongs to the Special Issue Image Processing Using FPGAs)
Full-Text   |   PDF [1830 KB, uploaded 18 October 2018]   |  


Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for simplicity and reducing computational complexity while maintaining state-of-the-art levels of accuracy. We explore both software and hardware acceleration opportunities, converting the original algorithm into a greyscale, integer-only version, and using Hardware/Software Co-design to develop hardware acceleration components on FPGA fabric that assist a software processor. We achieved a 4.4× speed improvement with the software optimisations alone, and a 2× speed improvement with the hardware optimisations alone. When combined, these led to a 9× speed improvement on a Cyclone V System-on-Chip, delivering almost 38 fps on 320 × 240 resolution images. View Full-Text
Keywords: background estimation; image segmentation; System-on-Chip; embedded systems; real-time systems; hardware accelerators background estimation; image segmentation; System-on-Chip; embedded systems; real-time systems; hardware accelerators

Figure 1

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

Share & Cite This Article

MDPI and ACS Style

Chen, A.T.-Y.; Gupta, R.; Borzenko, A.; Wang, K.I.-K.; Biglari-Abhari, M. Accelerating SuperBE with Hardware/Software Co-Design. J. Imaging 2018, 4, 122.

Show more citation formats Show less citations formats

Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Related Articles

Article Metrics

Article Access Statistics



[Return to top]
J. Imaging EISSN 2313-433X Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top