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J. Imaging 2019, 5(1), 7; https://doi.org/10.3390/jimaging5010007

Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing

1
Department of Systems and Computer Engineering, Carleton University, Ottawa, ON K1S 5B6, Canada
2
Div. of Computing Science and Mathematics, University of Stirling, Stirling FK9 4LA, UK
3
School of Mathematical and Computer Sciences, Heriot Watt University, Edinburgh EH14 4AS, UK
4
School of Engineering and Physical Sciences, Heriot Watt University, Edinburgh EH14 4AS, UK
*
Author to whom correspondence should be addressed.
Received: 19 November 2018 / Revised: 24 December 2018 / Accepted: 27 December 2018 / Published: 1 January 2019
(This article belongs to the Special Issue Image Processing Using FPGAs)
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Abstract

Memory is the biggest limiting factor to the widespread use of FPGAs for high-level image processing, which require complete frame(s) to be stored in situ. Since FPGAs have limited on-chip memory capabilities, efficient use of such resources is essential to meet performance, size and power constraints. In this paper, we investigate allocation of on-chip memory resources in order to minimize resource usage and power consumption, contributing to the realization of power-efficient high-level image processing fully contained on FPGAs. We propose methods for generating memory architectures, from both Hardware Description Languages and High Level Synthesis designs, which minimize memory usage and power consumption. Based on a formalization of on-chip memory configuration options and a power model, we demonstrate how our partitioning algorithms can outperform traditional strategies. Compared to commercial FPGA synthesis and High Level Synthesis tools, our results show that the proposed algorithms can result in up to 60% higher utilization efficiency, increasing the sizes and/or number of frames that can be accommodated, and reduce frame buffers’ dynamic power consumption by up to approximately 70%. In our experiments using Optical Flow and MeanShift Tracking, representative high-level algorithms, data show that partitioning algorithms can reduce total power by up to 25% and 30%, respectively, without impacting performance. View Full-Text
Keywords: field programmable gate array (FPGA); memory; power; image processing; design field programmable gate array (FPGA); memory; power; image processing; design
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Garcia, P.; Bhowmik, D.; Stewart, R.; Michaelson, G.; Wallace, A. Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing. J. Imaging 2019, 5, 7.

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