Modeling and Mitigating Output-Dependent Modulation in Current-Steering DAC Based on Differential-Quad Switching Scheme

: This brief presents a comprehensive analysis of the output-dependent modulation (ODM) in a current-steering digital-to-analog converter (CS-DAC) based on the differential-quad switching (DQS) structure. A mathematical model is proposed to accurately describe ODM, which is categorized into two types: output transition errors and boundary effect errors. A novel approach of adding isolation devices is introduced and reinterpreted to mitigate the effect of ODM. The simulation results indicate that the inclusion of isolation devices efficiently suppresses the odd harmonics at mid-to-high frequency by a value that is 13 dB lower than before. Experimental validation is conducted on a 16-bit 250 MS/s CS-DAC fabricated in a 180 nm process.


Introduction
CS-DACs have been widely used in wireless communication systems for their excellent speed performance.The dynamic performance of CS-DACs, particularly the SFDR, has attracted significant attention in engineering.Prior works [1][2][3] have developed analytical models and examined the relationship between the SFDR and output impedance.However, high-speed DACs may still experience performance degradation when converting highfrequency signals, even with ideal current sources.
Currently, various techniques have been proposed to enhance the SFDR, including dynamic element matching (DEM) [4][5][6], differential-quad switching (DQS) [7][8][9], and the combination of these approaches [10,11].The DEM technique eliminates the mapping between the digital input code and the corresponding current elements of DAC, minimizing the impact of mismatch between current elements on the SFDR.Nevertheless, studies have shown that DACs still suffer from harmonic distortion with the DEM scheme [12], as they are also affected by output-dependent modulation (ODM).Conventional DEM only deals with mismatches of an individual DAC; a new time-interleaving DEM (T-DEM) that randomizes the residual offset, gain, and skew mismatches is introduced in [13].T-DEM tackles the mismatches between the two DACs, reducing the constraint of TI spur on the performance of high-speed TI DACs.
The DQS structure, first introduced in [7], eliminates the code-dependent distortion by incorporating a pair of complementary switches.Similarly, the switching process in the DQS structure is also modulated by the output signal, and the mismatch between switches can deteriorate the dynamic performance of DACs [11].Work [10] applies the novel grouped random rotation thermometer code (GRTC) and differential-quad switching (DQS) and has good dynamic performance without calibrations.This is because the GRTC suppresses the harmonics caused by element mismatches, while the DQS reduces the output-dependent distortion to achieve a high SFDR.The GRTC relies on intricate digital logic for its implementation, and its design challenges and performance are closely linked to the segmentation method of DACs.
Up to now, many novel calibration schemes and circuit structures have been proposed to improve the linearity and dynamic performance of DACs.Work [14] presents a Nyquistrate CS-DAC that achieves a peak SFDR of better than 87 dB, which is enabled by a fully integrated digital calibration technique that measures and cancels both static and dynamic mismatch errors over the first Nyquist band.
In [15,16], a switching-glitch compensation (SGC) technique greatly reduced the codedependent switching glitch effect: thus, the SFDR performance at high Fout is improved.The SGC is realized with glitch duplicators and is proposed to generate a complementary amount of switching glitch at the DAC output, which results in significant area consumption.An output impedance compensation (OIC) technique [17] using a compensation resistor, implemented by a PMOS with code-dependent gate voltage control, is proposed to remedy the nonlinearity induced by the insufficient output impedance of the non-cascoded current cells.The DAC achieves > 65 dBc SFDR over the entire Nyquist bandwidth at 10 GS/s.While the circuit structure of this technology is simple, it requires ingenious design, which often leads to an increase in certain costs.
To mitigate the effects of ODM, a new theoretical model for describing ODM is introduced and validated.Additionally, an approach utilizing isolation devices is suggested in this brief, which can reduce output-dependent errors by a factor of 4-5 and maximize the reduction of third harmonic components at high signal frequencies by 13 dB, significantly improving the SFDR of DACs based on the DQS structure.
The structure of this brief is as follows: Section 2 analyzes the mechanism of ODM in DQS-based DACs and presents the harmonic analysis model.Section 3 outlines the CS-DAC architecture and the circuit implementations.Section 4 reports the measured results.The conclusion is drawn in Section 5.

Output-Dependent Modulation Based on DQS Structure
The circuit and timing sequence of DQS structure are depicted in Figure 1.In terms of the number of switches, the DQS structure consists of four switches, while the normal structure only has two switches.The typical feature of the DQS structure is that during each conversion, only one pair of switches undergoes switching in a single switched current source.The DQS structure effectively eliminates code-dependent distortion, but ODM that can compromise the system's dynamic performance remains.In this brief, ODM mainly involves two types of errors: those caused by output transition as well as the different output boundaries before and after conversion.This section presents a comprehensive model of ODM utilizing a seven-bit DQS-based CS-DAC with a full temperature encoder.The model can be easily extended to various DACs encoded in binary as well as hybrid encoding.

Opposite-Side Switching Errors (OSEs)
With the circuit configuration mentioned in [12], this work initially investigates the switching distortion caused by output transition through SPICE simulation.As shown in Figure 2a, for transitions from zero to one (U1: S1 or S3 is on, S2 or S4 is off) and from one to zero (U2: S1 or S3 is off, S2 or S4 is on), we define the differences in output current between the unit with output transition and the unit without it as δ01 and δ10, respectively, representing the switching errors on opposite sides.
For transitions from one to one (S1 and S3 alternate conducting, S2 and S4 are always off) and from zero to zero (S1 and S3 are always off, S2 and S4 alternate conducting), similarly, the corresponding differences can be expressed as δ11 and δ00, respectively, representing the switching errors on same side.
For the code transition from V 1 to V 2 , we set: where V mid denotes the value of middle code of the input sequence.Specifically, for a seven-bit DAC, the value of V mid is equivalent to 64 (b'1000000).
During each conversion, both δ01 and δ10 exhibit the same multiplicative effect with the magnitude of output transition ∆V(∆V = V 2 − V 1 ), as illustrated in Figure 2b.However, there is a slight difference between them, and the waveform of δ01-δ10 is in the inset.The error is independent of the transition direction and can be represented by an even function f (∆V).Its size increases with the absolute value of ∆V, but it is not a simple linear relationship.Due to its relatively low energy, the tiny errors cannot be considered as a major source of distortion.To facilitate analysis of switching errors, we summarize a general model by directly correlating the switching events with the OSEs.Before analyzing the impact of OSEs on SFDR, the following assumptions are necessary: (1) Assume that δ11 (δ00) and δ01 (δ10) have the same output dependency.
(2) Ignore the influence of initial and final output voltages on errors; the OSEs are solely related to output transition.
During each conversion from V 1 to V 2 , the total number of switching events is equal to the current elements' number, defined as N.The OSEs are completely opposed to each other under the constant ∆V conditions, as follows: Thus, the OSEs can be expressed as follows: 3) where ε O1 represents the unit switching error when the output increases by 1 LSB, and ∆V denotes the amplitude of the output transition.In a DQS structure, the distortion introduced by OSEs can be expressed as: Based on ( 1)-( 6), it can be proved that (Details are provided in Appendix A): Clearly, the first term of Equation ( 7) contains third harmonic components.If the input signal contains the offset error, even harmonics will emerge, which is consistent with the conclusion in work [12].And the unit switching error ε O1 pertaining to OSEs does not introduce harmonic components.
In a normal structure, the distortion introduced by OSEs can be expressed as: where aiming for simplicity, q is introduced: Compared with the DQS structure, the first term of Equation (8) shows that the normal structure is affected by OSEs, leading to the incorporation of additional odd harmonics.Therefore, the DQS structure exhibits better dynamic performance, which is attributed to the code independence of the DQS structure itself.

Same-Side Switching Errors (SSEs)
Actually, Assumption (1) in Section 2.1 is invalid due to the distinct external environments of the opposite-side switches and the same-side switches, i.e., δ11 ̸ = δ01, δ00 ̸ = δ10.It is expected that they will exhibit varying impacts from the output transition.The opposite-side switching can be transformed into the same-side switching by modifying the switch logic of U1 and U2 to direct current towards the same resistor.Subsequently, the SSEs δ11 and δ00 can be obtained under the initial condition V 1 =V mid .
Figure 3 illustrates the differences between the OSEs and SSEs under the same ∆V, i.e., δ00-δ10 and δ11-δ01, whose magnitudes are directly proportional to ∆V and whose signs follow the direction of ∆V.Therefore, the SSEs in ( 3) and ( 4) can be reformulated as: where ε O2 represents δ00-δ10 and δ11-δ01 when the output increases by 1 LSB.Rewriting (7), Err O,S includes the effects of both OSEs and SSEs: As we can see from (12), one of the primary sources of odd harmonics in the DQS structure is ε O2 , the difference between SSEs and OSEs.By substituting the sine input signals the second term, we can derive the third harmonic distortion; the remaining odd-order components are too minor to be considered significant: When ε O2 doubles, HD3 increases by 6 dB in a DQS structure.However, for the normal structure of a current element with a pair of switches, ε O1 s are the primary sources of distortion.Ultimately, this difference leads to the DAC with the DQS structure being less affected by ODM.
Through MATLAB simulation, the influence of output transition on the SFDR of a full thermometer-coded 16-bit DAC with a normal structure can be obtained under different output signal frequencies, as shown in Figure 4. Figure 4a depicts the DAC spectrum with the introduction of OSEs due to output transitions when the input signal frequency is 41MHz.It can be observed that there are distinct third harmonics present.Figure 4b illustrates the curve of the DAC's SFDR varying with the output signal frequency under the condition of Nε O1 = 5 × 10 −8 .In practical circuit design, due to the low amplitude limit, it is difficult to directly observe the unit error.However, the error waveform can be obtained through simulation utilizing the property of the output transition error being related to ∆V.

Boundary Effect Errors (BEEs)
Except for output transition, the ODM also includes the influence of output voltages before and after the conversion, that is, the boundary effect.This effect is an inescapable factor for estimating errors.The simulation configuration is depicted in Figure 5a.Taking the initial condition V 1 = V mid as a reference, simulations are carried out for different V 1 (such as N/8, N/2, 3N/4, etc.).The BEEs are obtained by subtracting this referred error from the switching errors corresponding to different V 1 .As shown in Figure 5b, the magnitude and direction of the BEEs are nearly linearly related to ∆ = V 1 − V mid under a constant ∆V.We also compare the BEEs under different output transition and find that the BEEs are unrelated to ∆V.
Due to the symmetry of the current element, the errors for opposite-side switching (i.e., δ01 and δ10) or same-side switching (i.e., δ00 and δ11) are affected by the same boundary effect.For the two cases, the unit BEE with ∆ = 1LSB is defined as ε f 1 or ε f 2 .Based on the above analysis, we analyze the distortion solely caused by the boundary effect: With ( 5) and ( 6), the distortion introduced by the boundary effect can be expressed as: Equations ( 16) and (17) demonstrate that in DACs with the DQS structure, the oddorder harmonic distortion is proportional to ε f 1 − ε f 2 , whereas in DACs with the normal structure, it is solely proportional to ε f 1 .Consequently, the smaller amplitude of the former results in less distortion.
There are two prerequisites for the validity of the above model: the integrity of ODM, including the output transition and boundary effect, and the symmetry of errors.For both DQS and normal structure, the symmetry can be expressed as follows: Figure 6 illustrates the impact of ODM on SFDR in DQS and normal structures based on a 16-bit DAC.The deterioration of the SFDR in the DQS structure is smaller than that in the normal structure due to the fact that the former (latter) is dominated by ε O2 (ε O1 ) and the energy of ε O1 is much bigger than ε O2 .However, a large ε O1 will slightly increase the noise floor in the DQS structure.On the other hand, the OSEs and SSEs are independent on the output impedance of the current source, indicating that the harmonic distortion (e.g., (13)) cannot be reduced by increasing output impedance.As depicted in Figure 6a, SFDR attenuation from ε f 1 is notably worse at low frequencies compared with ε O1 , yet ε O1 's attenuation intensifies more steeply as frequency rises.Figure 6b shows that the DQS structure eliminates the role of ε f 1 and uses ε f 1 − ε f 2 as the source of harmonics.For ease of comparing the effects of BEEs and SSEs, we set The degeneration of the SFDR caused by ε O2 is greater than that by ε f 1 − ε f 2 with the input signal frequency increasing.However, the latter's attenuation effect on the SFDR is manifested at lower frequencies in the DQS structure.Both of them contribute to HD3 in practice.
Overall, compared with the normal structure, the advantage of DQS-based DACs is that their harmonic component is only associated with the difference of switching errors ε O2 , (ε f 1 − ε f 2 ) with lower energy, rather than ε O1 , ε f 1 .Therefore, DQS-based DACs typically exhibit better SFDRs in theory.
We have delved into the output-dependent errors of the DAC, exploring the effects of output transition errors (both OSEs and SSEs) and errors caused by different initial output magnitude (BEEs) on the MSB's current error.δ 01 , δ 10 , δ 00 , and δ 01 reflect the unit current error under four switching directions in the DQS scheme.However, the DAC with the normal two-switch structure in the switched current source only has two types of switching directions, δ 01 and δ 10 , which leads to differences in performance between the two structures under the influence of output-dependent errors.The entire model is based on Equations ( 7), ( 8), ( 12), ( 16) and (17).
In the MATLAB model, we have defined ε O1 , ε O2 , and ε f separately to represent the smallest units of current error, distinguishing OSEs, SSEs (which only appear in the DQS structure), and BEEs (ε f 1 in the normal structure, ε f 1 and ε f 2 in DQS structure).As shown in Figure 6, we have modeled the impact of different error sources individually based on a 16-bit thermometer-coded current-steering DAC, aiming to more intuitively reflect the magnitude and speed of SFDR degradation caused by them as the output signal frequency increases.
Figure 7 shows the block diagram of overall model.Err(V mid , V mid ) represents the in- herent glitch introduced by the switching operation, which is output-independent because the output has not changed.Err(V mid , V mid + ∆V) represents the current errors that occur when the output transition takes place, and Err(V 1 , V 1 + ∆V) represents the total current errors under different initial output magnitudes.

DAC Architecture and Implementation of Circuits
The structure of the overall DAC is depicted in Figure 8.This work presents a "7 bit MSBs+4 bit ISBs+5 bit LSBs" segmented current-steering DAC, whose supply voltage is 3.3 V and full-scale output current is 20 mA.When calibration is activated, I SUMn and I REF serve as the inputs of the calibration circuit and are connected to it via switches.I OUTP and I OUTN are externally connected to a 50 Ω output load.The MSB unit (U1-U127) consists of a gain-boosted cascoded current source, the DQS array, and a pair of always-on switches serving as the isolation devices.Prior works have utilized the always-on switches [12,[18][19][20] to reduce parasitic capacitance.However, this structure also plays a crucial role in minimizing output-dependent errors in practice.Despite the dynamic external environment of switches, the impact of ODM is effectively suppressed to a certain extent due to the effect of isolation devices.During each conversion, the always-on switches operating in saturation provide a stable DC level for the drain of switches and a significantly higher output impedance.To achieve a ±1V swing amplitude, this work avoids the two-cascode structure in [21].
The MSBs and ISBs are thermometer-coded, and the LSBs are binary-coded.MP0 and MP1 have the same size, and the lower nine bits are implemented by splitting MP0.ISBs and LSBs are gain-boosted by a single operational amplifier to enhance their output impedance while incorporating DQS structures and isolation devices to guarantee the precise matching of the DAC's internal circuit.
As shown in Figure 9a, a calibration circuit is employed to enhance the static performance of the DAC.The calibration scheme of this structure is as follows: initially, taking I SUM1 as the reference, I REF is calibrated to I REF = I SUM1 + I OS (the offset current) through the internal comparator.Subsequently, taking I REF as the reference, I SUMn is successively calibrated to ensure I SUMn = I SUM1 , effectively eliminating I OS [22].Figure 9b outlines the basic circuit of the calibration DAC, where the upper two bits are thermometer-coded and the lower four bits are binary-coded.The output I OP is directly connected to the output terminal of the MSBs current source for calibration purposes, and the excess current I OM is absorbed.Once all MSBs have undergone thorough calibration, the full-scale output current is fine-tuned by accurately measuring the output current and adjusting the bias voltage VBP accordingly.To verify the effect of isolation devices, this paper compares the magnitudes of outputdependent errors between two different structures: the two-cascode structure and the DQS structure with isolation devices.As shown in Figure 10a, when the output transition is N/8, the magnitudes of the SSEs for the unit employing the two-cascode structure are approximately 8 µA.However, with the unit utilizing the isolation devices introduced in this paper, the magnitudes of the SSEs are significantly reduced to approximately 2 µA, and the magnitudes of errors that are proportional to ∆V are diminished to one-fourth of their original size.Similarly, as depicted in the Figure 10b, the magnitudes of BEEs are reduced to one-fifth of their original size after adopting isolation devices.Implementing isolation devices reduces the amplitudes of both SSEs and BEEs by a factor of 4-5 compared with the two-cascode structure under the same output environment.
With the appropriate low-cross-point design for the switch drive circuits, the speed before and after employing isolation devices remains unaffected.
Based on the preceding analysis, the third harmonic distortion caused by outputdependent errors can be suppressed.Consequently, this paper proceeds to compare the harmonic energy and SFDR of the DAC in the two structures, as depicted in Figure 11.
Figure 11a shows the comparison of harmonic distortions with and without isolation devices in the simulation results.As output signal frequency increases, the HD3 of the DAC with isolation devices begins to level off beyond 20 MHz, whereas the HD3 without isolation devices monotonously increases from −93 dB to −79 dB.At 60 MHz, the primary distortion in the case of employing isolation devices begins to mutate into the second harmonics (HD2) instead of HD3, unlike the without-isolation devices case wherein HD3 is always larger than HD2.At high frequencies of 80 MHz to 120 MHz, the HD3 is effectively suppressed by an average of 10dB compared with the case without isolation, even reaching 13 dB at 93 MHz. Figure 11b shows the simulation results of the SFDR at different frequencies.The shift of the primary harmonic component with increasing frequency further affects the SFDR and results in a maximum improvement of 6.6 dB at 60 MHz.

Measurement Results
Figure 12 illustrates the die micrograph and the layout of the proposed DAC.The area occupied by a single DAC is 3.06 mm × 2.14 mm.In this design, the current source array adopts a common centroid layout, and a large number of dummy devices are added to ensure the symmetry of the layout.Additionally, the AUX DAC can be programmed to either source or sink current, enabling it to effectively eliminate the DC offset of this DAC.
Figure 13 displays the measured curves of the DAC's DNL and INL when the proposed calibration method was off.The DNL and INL are ±3LSB and ±13LSB, respectively.when the proposed calibration method was on, the DNL and INL of the DAC are within the ranges of ±2LSB and ±4LSB, as illustrated in Figure 14.Evidently, this calibration scheme significantly improves the linearity of the DAC.
Figure 15 shows the test spectrum of DAC at 5 MHz, 60 MHz, and 122 MHz, respectively.At 5 MHz, HD3 is approximately 8dB higher than HD2; meanwhile, at 60 MHz and the Nyquist frequency, HD3 is 7-8 dB lower than HD2.Comparing the spectra within the first Nyquist zone, at low-frequency outputs, HD3 is higher than HD2, determining the SFDR of the DAC.However, in the mid-to-high-frequency range, the new structure suppresses output-dependent errors, resulting in HD3 being lower than HD2 and thus no longer dominating the SFDR.As depicted in Figure 16a, at an output frequency of 60MHz, the primary harmonic that dominates the DAC's SFDR transitions from HD3 to HD2.Furthermore, when the output frequency exceeds 60 MHz, HD3 averages approximately 6 dB lower than HD2, suggesting that the isolation device effectively suppresses the influence of odd harmonics.When considering the third harmonic component alone, a significant suppression of the third harmonic can be observed in the mid-frequency range.This finding is consistent with the trends observed in simulation results and corroborates our previous analysis.In Figure 16b, the solid line represents the test results for the SFDR, and the dashed line depicts the attenuation curve due to the limited output impedance of the DAC as the frequency increases.It can be observed that the SFDR is elevated in the mid-to-high frequency range, indicating that the combination of the DQS structure and isolation components enhances the dynamic performance of the DAC in this frequency range.Nevertheless, in this study, while the suppression of odd harmonics remains unaffected, the amplitude of HD2 is unexpectedly high in both simulation and measurement.The key factor contributing to this issue is the DQS structure, which comprises four switches that demand a high level of synchronization in their control signals.As discussed in work [23], the asymmetry among the switches can trigger the emergence of even harmonics.
A comparison of the performance of the proposed DAC with that of the state-of-the-art designs is presented in Table 1.Dummy circuits are added to each DQS switch to ensure the synchronization of the switches.These dummy circuits make the driving signal's load the same, resulting in an increase in the area consumption of the entire DAC.Furthermore, the employment of calibration circuits and isolation devices necessitates a certain degree of area consumption.In this design, the low-frequency SFDR of the DAC is lower than that of work [19] and higher than that of work [15].This is due to a slight decrease in the output impedance of the unit current source after adopting isolation devices.At the Nyquist frequency, the SFDR is superior to work [9] and is close to work [20,24].Comparing with work [10], the scheme presented in this paper is not dependent on segmentation, making it significantly easier to design.The work [19] applies the same calibration scheme as this work, utilizing thermometer DEM to tackle voltage and time errors, thus achieving a better INL.
None the other works incorporate calibration schemes and consequently fail to present the DNL and INL performance of the DAC.This ultimately accounts for the relatively smaller product area.

Conclusions
This work has analyzed the mechanism of output-dependent modulation in DACs based on a DQS structure.A comprehensive mathematical model has been developed, which theoretically explains the impact of originally ambiguous output-dependent errors on CS-DACs.Based on this model, a 16-bit 250 MS/s current-steering DAC is proposed.
A calibration scheme for improving the static performance of DAC has been proposed, enabling the DAC to achieve linearity with a DNL and INL of ±2LSB and ±4LSB, respectively.
Additionally, a novel switched current source structure is introduced, which integrates the DQS structure with always-on switches.The simulation results show that this structure suppresses odd harmonics caused by output-dependent errors by up to 13 dB, making the second-order harmonic dominant when calculating the spurious-free dynamic range (SFDR), resulting in a maximum improvement of the SFDR of 6.6dB, thereby significantly improving the dynamic performance of the DAC.The measurement results show that the SFDR of the DAC at the low-frequency output is 76.13 dB, 71.74 dB at 60 MHz, and 59.55 dB at 122 MHz after adopting the novel structure.The third harmonic is significantly suppressed in the mid-to-high frequency range, exhibiting the same trend to the simulation results, which is also in agreement with the proposed model.

Figure 1 .
Figure 1.The (a) circuit and (b) timing sequence of the DQS structure.

Figure 2 .
Figure 2. (a) Simulation configuration and (b) results of the OSEs.

Figure 3 .
Figure 3. (a) Simulation configuration and (b) results of the SSEs.

Figure 4 .
Figure 4.The impact of output transition on SFDR with different output frequencies: (a) spectrum and (b) SFDR.

Figure 5 .
Figure 5. (a) Simulation configuration and (b) results of the BEEs.

Figure 6 .
Figure 6.Simulation results of the impact of ODM on SFDR in (a) normal and (b) DQS structures.

Figure 7 .
Figure 7. Block diagram of the overall model.

Figure 8 .
Figure 8. Structure of the proposed DAC.

Figure 9 .
Figure 9. (a) Calibration scheme and (b) circuit of calibration of the DAC.

Figure 10 .
Figure 10.Suppressing effects of isolation devices on (a) SSEs and (b) BEEs.

Figure 11 .
Figure 11.The simulation results of (a) harmonics and (b) SFDR of DACs adopting the two structures separately.

Figure 12 .
Figure 12.Die micrograph and layout of the proposed DAC.

Figure 13 .
Figure 13.Measured (a) DNL and (b) INL when the proposed calibration method was off.

Figure 14 .
Figure 14.Measured (a) DNL and (b) INL when the proposed calibration method was on.

Figure 16 .
Figure 16.The test results of (a) harmonics and (b) SFDR of the proposed DAC.

Table 1 .
Comparison with precious studies.