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Electronics
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Low Power RFIC Architectures for Emerging Wireless Standards
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Low Power RFIC Architectures for Emerging Wireless Standards

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microwave and Wireless Communications".

Deadline for manuscript submissions: closed (1 September 2022) | Viewed by 6729

Special Issue Editors

Dr. Cristian Andriesei

E-Mail Website
Guest Editor
Faculty of Electronics, Telecommunications and Information Technology, Gheorghe Asachi Technical University of Iasi (TU Iasi), Iasi, Romania
Interests: LNA; microstrip antenna; hardware security; transceivers / RF front-end; smart city
Prof. Dr. Farid Temcamani

E-Mail Website
Guest Editor
ENSEA, Université de Cergy-Pontoise, 95000 Cergy, France
Interests: microwaves; GaN; active filters; aging; RFIC

Special Issue Information

Dear Colleagues,

The successful adoption of 5G and IoT standards, the coming standardization of 6G mobile communications, the continuous smartification of cities and integration of blockchain technology, the emerging vehicles connectivity and autonomous driving, all these push increased pressure on the practical development of more efficient RF architectures, able to cover multiple bands, at higher frequencies, and with improved power efficiency. To address such challenges, this Special Issue covers RFIC architectures with low power capability demonstrated on circuit or system level by means of prototype measurement and/or simulations. Wireless sensors and RFID implementations are not excluded.

Extended versions of conference articles are accepted as long as they have at least 50% novelty.

Dr. Cristian Andriesei
Prof. Dr. Farid Temcamani
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • 6G
  • IoT
  • low power
  • RFIC
  • wireless

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Published Papers (2 papers)

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Research

11 pages, 5400 KiB  
Article
A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS
by Zhe Chen, Debin Hou, Jixin Chen and Pinpin Yan
Electronics 2022, 11(12), 1828; https://doi.org/10.3390/electronics11121828 - 9 Jun 2022
Cited by 1 | Viewed by 2332
Abstract
In this article, a dual-loop dual-output frequency synthesizer designed for IEEE802.11aj (45 GHz) standard is presented. In order to support the super-heterodyne transceiver, the Loop1 output frequency is fixed for easy design of high-performance IF transceiver and filter, and the Loop2 output frequency [...] Read more.
In this article, a dual-loop dual-output frequency synthesizer designed for IEEE802.11aj (45 GHz) standard is presented. In order to support the super-heterodyne transceiver, the Loop1 output frequency is fixed for easy design of high-performance IF transceiver and filter, and the Loop2 output frequency varies for the channel selection according to the IEEE802.11aj (45 GHz) standard. The power hungry high-speed prescaler (or multi-modulus-divider) is replaced with a mixer in Loop2, thus the in-band phase noise and DC power consumption can be improved. The dual-loop dual-output synthesizer is fabricated in 0.13 µm SiGe BiCMOS technology, occupies an area of 2.7 mm × 2.4 mm, and consumes 610 mW DC power. Measured results show the phase noise of the frequency synthesizer are −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The low-reference spur of −69.2 dBc and low-power level spurious tones at the outputs are observed during the measurement. To the best of our knowledge, this work is the first reported dual-loop dual-output synthesizer designed for IEEE802.11aj (45 GHz) standard. Full article
(This article belongs to the Special Issue Low Power RFIC Architectures for Emerging Wireless Standards)
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13 pages, 2443 KiB  
Article
A Wideband Low-Power Balun-LNA with Feedback and Current Reuse Technique
by Muhammad Fakhri Mauludin, Dong-Ho Lee and Jusung Kim
Electronics 2022, 11(9), 1372; https://doi.org/10.3390/electronics11091372 - 25 Apr 2022
Cited by 8 | Viewed by 3082
Abstract
This paper presents a low-noise amplifier (LNA) with single to differential conversion (Balun) for multi-standard radio applications. The proposed LNA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage to cancel the noise and distortion of the CG [...] Read more.
This paper presents a low-noise amplifier (LNA) with single to differential conversion (Balun) for multi-standard radio applications. The proposed LNA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage to cancel the noise and distortion of the CG stage. Using the proposed technique, a low noise figure (NF) is achieved while providing a wideband of operation. Furthermore, a feedback connection from the CS stage to the gate of the CG is employed to boost the transconductance of the CG stage (gmCG), and an additional complementary transistor is applied at the CS stage using current reuse to increase the overall transconductance of the CS stage (gmCS) without increasing the power consumed by the stage. This LNA was designed using TSMC 65 nm technology, and post-layout simulation results show operation across 0.5–5 GHz, a maximum power gain of 20 dB, 4 dB minimum NF, and third-order intercept point (IIP3) of −10 dBm while consuming only 5 mW of power from a 1.2 V supply. Full article
(This article belongs to the Special Issue Low Power RFIC Architectures for Emerging Wireless Standards)
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