A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS

Abstract

In this article, a dual-loop dual-output frequency synthesizer designed for IEEE802.11aj (45 GHz) standard is presented. In order to support the super-heterodyne transceiver, the Loop1 output frequency is fixed for easy design of high-performance IF transceiver and filter, and the Loop2 output frequency varies for the channel selection according to the IEEE802.11aj (45 GHz) standard. The power hungry high-speed prescaler (or multi-modulus-divider) is replaced with a mixer in Loop2, thus the in-band phase noise and DC power consumption can be improved. The dual-loop dual-output synthesizer is fabricated in 0.13 µm SiGe BiCMOS technology, occupies an area of 2.7 mm × 2.4 mm, and consumes 610 mW DC power. Measured results show the phase noise of the frequency synthesizer are −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The low-reference spur of −69.2 dBc and low-power level spurious tones at the outputs are observed during the measurement. To the best of our knowledge, this work is the first reported dual-loop dual-output synthesizer designed for IEEE802.11aj (45 GHz) standard.

1. Introduction

Recently, high-data-rate communication systems with increasing bandwidth requirements have drawn much attention. The millimeter-wave frequency band with rich spectrum resources is well-matched for massive data-driven communications, such as 5G, wireless high-definition video streaming, and future ultra-high-speed wireless communication. Millimeter-wave systems, in 28/39 GHz band for 5G new radio standard and in 60 GHz bands for IEEE802.11ad/WiGig standard, have been developed for the increasing data-rate demands [1,2,3,4,5,6].

In Q-band, IEEE 802.11aj (45 GHz) standard was approved in 2018 as a IEEE802.11 family member for high-data-rate wireless personal area networks and portable devices. These devices define 10 channels with a channel bandwidth of 540 MHz or 5 channels of 1080 MHz, as shown in Figure 1, with up to 15 Gb/s data rate [7,8]. Although there are many reported synthesizer studies [9,10,11,12,13,14,15], very few synthesizer studies have been reported for the IEEE802.11aj (45 GHz) standard [16]. For the millimeter-wave transceiver design, super-heterodyne system is preferred for high-dynamic range, alleviated LO leakage, and DC-offset issues, where two or more LO frequencies (denoted as LO1, LO2, etc.) are needed in the system. To simplify the synthesizer design, sliding-IF transceiver topology is often used [2,5,6], where the LO1 frequency is harmonic-related to the LO2, so one single-loop frequency synthesizer can support the transceiver application, as shown in Figure 2a. However, in sliding-IF topology, both LO1 and LO2 are variable for selecting different channels, which add complexity in wide-band IF transceiver and filter design. On the contrary, for super-heterodyne topology with dual-loop LO synthesizer, LO1 frequency can be fixed for high-performance IF transceiver and band-pass filter design, while LO2 frequency is variable for channel selection, as shown in Figure 2b. Moreover, since LO1 and LO2 are generated by independent phase locked loops synchronized with a reference source, the overall phase noise performance can be improved, with the price of more chip area and DC power consumption.

In this article, the design of the dual-loop dual-output frequency synthesizer for the IEEE802.11aj (45 GHz) standard is presented. Thanks to the dual-loop topology, the frequency of Loop1 is fixed for easy design of high-performance IF transceiver and filter, and the frequency of Loop2 varies for the channel selection. In addition, the power hungry high-speed prescaler or multi-modulus-divider (MMD) is replaced with a mixer in Loop2, thus in-band phase noise degeneration can be avoided, which helps to improve the integrated phase noise for high-data-rate communications. The dual-loop dual-output synthesizer is fabricated in 0.13 µm SiGe BiCMOS process. Measured results have shown the phase noise of −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. Low-level reference spurs and spurious tones are also obtained at the outputs. In Section 2, the proposed dual-loop dual-output frequency synthesizer is designed and implemented. In Section 3, measured results of the dual-output synthesizer are provided in detail, and the conclusion is presented in Section 4.

2. Design and Implementation of the Dual-Loop Dual-Output Frequency Synthesizer

In this article, the dual-loop dual-output frequency synthesizer is proposed for the IEEE802.11aj (45 GHz) applications, and the block diagram is shown in Figure 3. In the proposed dual-loop synthesizer, the frequency of LO1 is fixed at 12.96 GHz, and the frequency of LO2 varies between 29.835~35.1 GHz for the channel selection. In this way, the output RF carrier frequency (LO2 + LO1) is 42.795~48.06 GHz, while the image frequency (LO2-LO1) is 16.875~22.14 GHz, which is reasonably away from LO1 and LO2. If needed, a bandpass filter is easy to design to suppress unwanted signals. Thus, the frequency allocation scheme is carefully chosen to simplify IF transceiver and filter design, avoiding most spurious mixing product falling into the signal band. Meanwhile, a RF down-conversion mixer is proposed in Loop2, where the Loop1′s output (12.96 GHz signal) is also the LO signal for the mixer. In this way, power consumption can be reduced by omitting high-speed prescaler/MMD, and in-band phase noise can be improved, as well. The frequency step also can be reserved as reference frequency with the Integer-N synthesizer.

Considering the frequency synthesizer implementation issues, such as the VCO phase noise performance, harmonic-frequency suppression, DC power consumption, etc., the LO1 at Ku-band (12.96 GHz) can be generated directly from VCO1, and LO2 at Ka-band from 29.835 to 35.1 GHz can be generated with VCO2, followed by a frequency doubler. In order to cover all the 540/1080 MHz channels in IEEE802.11aj (45 GHz) standard, the reference frequency of 67.5 MHz is chosen for the dual-loop Integer-N synthesizer. The VCO1, VCO2, doubler, mixer, and prescaler (in Loop1) are designed with SiGe HBT devices for low-phase noise and high-speed performance in Ku/Ka-band, which are designed and optimized with full-wave EM simulator to take into account the parasitic effects. Phase-frequency detector (PFD), charge pump (CP), and low dropout regulators (LDOs) are designed with thick gate-oxide CMOS transistors and MMD1/MMD2. Serial peripheral interface (SPI) circuits are designed with thin gate-oxide CMOS transistors, both offered with the 0.13 μm SiGe BiCMOS technology. The on-board loop filters (LPF1 and LPF2) are not integrated on the chip for flexibility and saving chip area.

2.1. Voltage Controlled Oscillator using Cap Bank and Ka-Band Doubler

Figure 4a shows the schematic of the Ku-band Colpitts VCO with 3-bit cap bank (in Loop2). The Ku-band Colpitts VCO with single varactor pair (in Loop1) uses the same topology without cap bank. The 3-bit cap bank is utilized to lower the VCO gain. The NMOS transistor is used as RF switch, which is controlled by Vsw. The capacitance in the 3-bit cap bank is binary weighted. In the Colpitts VCO, the LC tank consists of C₁, C₂, L₂, C_var, L_e, and the 3-bit cap bank. C_var is capacitance of the varactor, which is biased with tuning voltage, Vt. Bipolar transistor T_1,2 generates the desired negative resistance to sustain oscillation. The biasing condition for T₁~T₄ are optimized for noise and output power. The emitter lengths for T_1,2 and T_3,4 are 18 µm and 10 µm, respectively. The switching signal, Vsw, is controlled by on-chip SPI. Figure 4b shows the designed Ka-band doubler, using differential Cascode core to generate second harmonic signal with sufficient gain and output power. The emitter lengths for T_5,6,7,8 are all 16 µm.

2.2. High-Speed Prescaler and Double-Balanced Down-Conversion Mixer

The synthesizer Loop1 outputs a fixed frequency signal at 12.96 GHz. The corresponding prescaler consists of two current-mode logic (CML) divide-by-2 stages [17], as shown in Figure 5a, which divides the 12.96 GHz VCO output to 3.24 GHz signal. CML divider has the advantages of small area, compared to the injection-locked frequency divider. Circuit parameters are optimized for each CML stage to obtain better RF performance and lower power consumption for input signals at 12.96/6.48 GHz.

The synthesizer Loop2 outputs Ku-band signal covering 14.9175~17.55 GHz. Normally, a high-speed MMD needs to be used after VCO to achieve the reference frequency step. This step introduces high-power consumption and in-band phase noise degeneration with 20lg(N), where N is the integer division ratio. In this work, instead, a down-conversion mixer is used to down-convert the Ku-band VCO signal from ~16 GHz to ~3 GHz with the 12.96 GHz LO signal from synthesizer Loop1. In this way, the power hungry high-speed prescaler or MMD can be avoided, and in-band phase noise can be improved. The double-balanced structure of down-conversion mixer reduces the LO and RF to IF port feed-through, as shown in Figure 5b. The mixer gm-stage is resistively degenerated to improve linearity. To make trade-off between the operating bandwidth and power-handling capacity, the transistor sizes are optimized for the switching quads (8 µm) and gm stage (16 µm).

2.3. Phase-Frequency Detector and Charge Pump

The PFD compares the reference signal, Fref, and the divided signal, Fdiv, and controls the CP current according to the phase and frequency difference, as shown in Figure 6a. The charge pump needs to provide matched up-and-down currents for most of the CP output voltage range. The charge-pump architecture employs dual operation amplifiers (Op-Amps), where both amplifiers utilize a high-swing topology [10]. The CP includes 3 binary weighted branches so that the current can be digitally controlled from 150 μA to 1050 μA, adapting the PLL’s loop bandwidth/settling time for various configurations. Finally, the simulated phase noise of the dual-loop dual-output synthesizer is shown in Figure 7. Figure 7a shows the simulated phase noise contributions at the Output1 from Loop1, while Figure 7b shows the simulated phase noise contributions at the Output2 from Loop2 with the frequency doubler. The loop bandwidth has been optimized to balance the in-band and out-of-band phase noise. From the phase noise contribution plot, most of them result from the integrated VCO, PFD, and CP.

3. Results

The proposed dual-loop dual-output frequency synthesizer is implemented using 0.13 µm SiGe BiCMOS technology. The top metal and second metal with thickness of 4 and 1.42 µm are used in the design of RF signal interconnections/passive parts, as well as the power routing, while the third metal with thickness of 0.6 µm is used as the RF/DC ground. The implemented synthesizer chip is wire-bonded to the printed circuit board (PCB), on which the PLL’s loop filters are implemented for low cost and flexibility. The output spectrum and the phase noise of the chip are measured with Keysight PXA N9030A, and R&S phase noise analyzer FSWP, which also provides the supply voltage to the low noise LDOs on PCB board, distributing the required voltages to each core circuit. The total DC power consumption is 610 mW for the dual-loop synthesizer chip. Figure 8 shows the measurement setup environment and the photograph of the wire-bonded dual-loop dual-output synthesizer. The chip size including all pads is 2.7 mm × 2.4 mm.

Figure 9a shows the measured output frequency of the Colpitts VCO1 in Loop1, which is from 12.28 to 13.25 GHz. Figure 9b shows the measured phase noise for VCO1 at 1 MHz offset, from −112 to −116 dBc/Hz. Thanks to the high-Q varactor provided by the process, the VCO1 shows good phase noise performance with the average VCO gain, Kvco, of 485 MHz/V for the varactor tuning voltage, Vt, from 0.2~1.6 V, where the charge pump has well-matched up/down currents to optimize the phase noise and spur performance for the frequency synthesizer.

Figure 9c shows the measured output frequency of the Colpitts VCO2 with three-bit cap bank in Loop2, which is from 14.81 GHz to 17.78 GHz. The VCO2, together with the frequency doubler, can cover 29.835~35.1 GHz, which is designed to support all 540/1080 MHz channels in IEEE802.11aj (45GHz) standard. Figure 9d shows the measured phase noise for VCO2 at 1 MHz offset, from −110 dBc/Hz to −115 dBc/Hz. With the three-bit cap bank, the average Kvco is kept below 450 MHz/V for the eight sub-bands, optimizing for the phase noise performance and loop dynamics of the frequency synthesizer.

Figure 10a,b shows the measured phase noise of the dual-loop dual-output frequency synthesizer, which are −79.3 dBc/Hz@10 kHz, −88.9 dBc/Hz@100 kHz, and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz, −80.2 dBc/Hz@100 kHz, and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The two outputs of the frequency synthesizer can support the channel centered at 45.495 GHz for IEEE 802.11aj (45 GHz) in a super-heterodyne transceiver, as shown in Figure 2b. By configuring a series of division ratios (N = 29, 31, 33, …, 57, 64, 66, 68) for MMD in Loop2, all the 540/1080 MHz channels of IEEE802.11aj (45 GHz) can be supported. The loop bandwidth of the two loops is designed as ~50 kHz and ~450 kHz, respectively, to optimize the in-band/out-of-band phase noise and spur attenuation. Compared to the simulated phase noise performance in Figure 7, the measured loop bandwidths shrink 50~100 kHz for Loop1 and Loop2, possibly due to some parasitic capacitance in the loop, and the measured phase noise degrades 2~5 dB for in-band and out-of-band noise, which possibly results from the 1/f noise model for the transistor provided by the process. Compared to the Loop1, there are more spurs from Output2 of the synthesizer at 1~10 MHz offset, which is probably due to the noise coupling from the cap-bank biasing and power supply network.

Figure 11a shows the measured output spectrum for the frequency synthesizer at 12.96 GHz with a span of 200 MHz, where the reference spur is below −69.2 dBc at 67.5 MHz offset. For the full span from ~DC to 50 GHz, Figure 11b shows the measured output spectrum at Output1, where the LO1 signal is with the highest power level of −4.5 dBm, and the second peak is the coupled LO2 (2 × fvco2) signal, with −17.3 dBc around ~32 GHz. Although the signal at fvco2 is close to fvco1, the power level is −39.8 dBc below. Figure 11c shows the measured output spectrum at Output2, where the LO2 (2 × fvco2) signal has the highest power level of +2 dBm, and the second peak is −19.2 dBc at fundamental frequency, fvco2. If spurious products in the mixing process are concerned, an extra band-pass filter can be used to further suppress the fvco2 signal.

Table 1. Comparison of state-of-the-art frequency synthesizers for communications.

Ref.	Tech.	Topology	Freq. (GHz)	Phase Noise 1 @100 kHz	Phase Noise 1 @10 MHz	Ref. Spur (dBc)	Power (mW)
[9]	90 nm CMOS	Single Loop	39.7~41.2	−62.3	−111.5	−38	110
[10]	90 nm CMOS	Single Loop	39.1~41.6	−60.6	−114.5	−54	64 2
[11]	65 nm CMOS	Single Loop	35~41.88	−67.9	−122.1	−50	80
[16]	90 nm CMOS	Single Loop	38.61~44.55	−84.9	−116.9	−46	76 2
This Work (Loop1)	0.13-μm SiGe	Dual Loop	12.96	−81.6	−121.8	−69	153 2
This Work (Loop2)	0.13-μm SiGe		29.835~35.1	−81.2	−118.1	−68	167 2

¹ Normalized phase noise for 30 GHz carrier = PN(f₀) + 20log(30 GHz/f₀); ² W.O. output buffer.

compares the details of the state-of-the-art frequency synthesizers for high-speed communications. The proposed dual-loop dual-output synthesizer shows good phase noise, tuning range, and reference spurs performances. The DC power consumption is higher compared with other works in the table, mainly due to the power hungry HBT transistors in the SiGe process.

4. Conclusions

In this article, the development of dual-loop dual-output frequency synthesizer for IEEE802.11aj (45 GHz) is presented. By utilizing dual-loop topology, the Output1 frequency is fixed for easy design of IF filter and IF transceiver, and the Output2 frequency is variable for channel selection. In addition, the power hungry high-speed prescaler (or MMD) is replaced with a mixer in the second loop, to improve both in-band phase noise and DC power consumption. Experimental prototype has been designed and fabricated in 0.13 μm SiGe BiCMOS process. The measured phase noise are −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The low-reference spur of −69.2 dBc and low-power level spurious tones at the outputs are also observed during the measurement. With the properly designed super-heterodyne transceiver, the proposed dual-loop dual-output frequency synthesizer is well suited for the IEEE802.11aj (45 GHz) standard.