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Electronics
Special Issues
Low-Power CMOS and Beyond-CMOS Front-End Circuits and Systems
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Low-Power CMOS and Beyond-CMOS Front-End Circuits and Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 May 2024) | Viewed by 3644

Special Issue Editors

Dr. Rafaella Fiorelli

E-Mail Website
Guest Editor
Instituto de Microelectrónica de Sevilla, University of Seville, 41092 Seville, Spain
Interests: CMOS integrated circuits; biomedical electronics; neurophysiology; analogue-digital conversion; bioelectric potentials; low-power electronics
Special Issues, Collections and Topics in MDPI journals
Dr. Juan Núñez

E-Mail Website
Guest Editor
Instituto de Microelectrónica de Sevilla, University of Seville, 41092 Sevilla, Spain
Interests: emerging technologies; new computing paradigms; low-power circuit design; coupled-oscillator systems
Dr. Julián Oreggioni

E-Mail Website
Guest Editor
Instituto de Ingeniería de Eléctrica, Universidad de la República, 10129 Montevideo, Uruguay
Interests: ultra-low-power CMOS integrated circuits; biomed-ical circuits and systems; low-power embedded sys-tems

Special Issue Information

Dear Colleagues,

The evolution of the Internet of Things (IoE) will eventually enable a plethora of sensors, inanimate and living entities, people, processes, and data to be seam-lessly interconnected and autonomously coordinated over the Internet.

These applications tie into the concept of edge computing, which requires plat-forms to extract task-relevant information from increasingly large amounts of data with stringent constraints on energy efficiency, performance, cost, and reliability.

In particular, the requirements of IoE and edge computing systems can be met thanks to the evolution of embedded CMOS or beyond-CMOS circuit technolo-gies (spintronic, resistive, ferroelectric, etc.).

To enable this connected universe, from molecular sensors to vehicles and peo-ple, requires the development of enabling technologies, which poses several challenges to circuit designers. For the IoE and edge computing paradigm to be viable, devices must operate at low-power levels. This requirement is a chal-lenge for front-end circuit designers, especially for nanometer CMOS or be-yond-CMOS technologies.

This Special Issue aims to collect contributions focusing on different topics in the design of low-power front-end circuits and systems using CMOS and emerging technologies. The topics of interest include, but are not limited to:

  1. Device modeling and biasing techniques for low-power circuits.
  2. The design of test circuits.
  3. Low-power analog and digital circuit design.
  4. Energy-harvesting circuits and systems.
  5. 4. Variability-aware design techniques for low-power design.
  6. Low-power sensor readout interfaces.
  7. Low-power data converters.
  8. The benchmarking of novel devices for front-end circuits.
  9. Implantable devices for biomedical applications.
  10. Low-power wearable electronics for body sensor networks.
  11. Autonomous healthcare circuits and systems.
  12. Neuromorphic computing systems.

Dr. Rafaella Fiorelli
Dr. Juan Núñez
Dr. Julián Oreggioni
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • low-power
  • CMOS
  • beyond-CMOS
  • front-end circuit
  • energy harvesting
  • varia-bility-aware
  • ADC
  • implantable devices
  • biomedical
  • wearable
  • body sensor
  • IoE
  • healthcare
  • neuromorphic

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Published Papers (2 papers)

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Research

15 pages, 6556 KiB  
Article
Simple Modeling and Analysis of Total Ionizing Dose Effects on Radio-Frequency Low-Noise Amplifiers
by Taeyeong Kim, Gyungtae Ryu, Jongho Lee, Moon-Kyu Cho, Daniel M. Fleetwood, John. D. Cressler and Ickhyun Song
Electronics 2024, 13(8), 1445; https://doi.org/10.3390/electronics13081445 - 11 Apr 2024
Cited by 1 | Viewed by 1695
Abstract
In this study, the degradation characteristics of radio frequency (RF)-low-noise amplifiers (LNA) due to a total ionizing dose (TID) is investigated. As a device-under-test (DUT), sample LNAs were prepared using silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) as core elements. The LNA was based [...] Read more.
In this study, the degradation characteristics of radio frequency (RF)-low-noise amplifiers (LNA) due to a total ionizing dose (TID) is investigated. As a device-under-test (DUT), sample LNAs were prepared using silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) as core elements. The LNA was based on a cascode stage with emitter degeneration for narrowband applications. By using a simplified small-signal model of a SiGe HBT, design equations such as gain, impedance matching, and noise figure (NF) were derived for analyzing TID-induced degradations in the circuit-level performance. To study radiation effects in circuits, the SiGe-RF-LNAs fabricated in a commercial 350 nm SiGe technology were exposed to 10-keV X-rays to a total ionizing dose of up to 3 Mrad(SiO2). The TID-induced performance changes of the LNA were modeled by applying degradation to device parameters. In the modeling process, new parameter values after irradiation were estimated based on information in the literature, without direct measurements of SiGe HBTs used in the LNA chip. As a result, the relative contributions of parameters on the circuit metrics were compared, identifying dominant parameters for degradation modeling. For the TID effects on input matching (S11) and NF, the base resistance (RB) and the base-to-emitter capacitance (Cπ) of the input transistor were mostly responsible, whereas the transconductances (gm) played a key role in the output matching (S22) and gain (S21). To validate the proposed approach, it has been applied to a different LNA in the literature and the modeling results predicted the TID-induced degradations within reasonable ranges. Full article
(This article belongs to the Special Issue Low-Power CMOS and Beyond-CMOS Front-End Circuits and Systems)
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13 pages, 3751 KiB  
Article
An Improved Dual-Gate Compact Model for Carbon Nanotube Field Effect Transistors with a Back-Gate Effect and Circuit Implementation
by Zhifeng Chen, Yuyan Zhang, Jianhua Jiang and Chengying Chen
Electronics 2024, 13(3), 620; https://doi.org/10.3390/electronics13030620 - 1 Feb 2024
Cited by 1 | Viewed by 1175
Abstract
Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) [...] Read more.
Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (Vbg) and threshold voltage (Vth) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model. Full article
(This article belongs to the Special Issue Low-Power CMOS and Beyond-CMOS Front-End Circuits and Systems)
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