1. Introduction
The scaling of CMOS technology, and the diffusion of applications requiring very low power consumption, such as IoT (Internet of Things) nodes [
1,
2] or biomedical and wearable devices [
3,
4], have paved the way to the development of compact and ultralow voltage (ULV) circuits. The operation of MOS devices in the deep subthreshold region is mandatory [
5,
6], to achieve ultralow-power (ULP) consumption and to allow the usage of very low supply voltages.
However, to allow such ultralow supply voltages, specific design approaches are required: floating-gate [
7] techniques have been proposed in the past, but the most common solutions are the body-driven (BD) technique and the inverter-based design approach.
Several amplifier designs operating at supply voltages in the order of 0.6 V or lower and exploiting multi-stage, folded cascode or symmetrical OTA topologies have been presented in the last years. The use of a very low supply voltage often requires to eliminate the bias current generator of the differential pair: the resulting pseudo-differential amplifier shows class-AB behavior, but no common mode rejection if the common mode output is exploited. Moreover, there is no control on the bias current, resulting in large variations of small signal performances under process, supply voltage and temperature (PVT) variations.
In BD amplifiers [
8,
9,
10,
11,
12,
13], the body is used as input terminal instead of the gate, thus allowing the input dc level not to be constrained by the threshold voltage of the devices, at the cost of reduced transconductance gain, higher noise, and an input impedance that is not purely capacitive. In this context, Ferreira et al. proposed a Miller amplifier designed in 350 nm CMOS process and operating at a supply voltage of 0.6 V in 2007 [
8]. Magnelli et al. published an amplifier with a supply voltage of 0.5 V and 75 nW power consumption in 2014 [
10]. In the same year, Ferreira et al. designed an amplifier with a supply voltage as low as 0.25 V [
9]. Abdelfattah et al. presented an ULV self-biased amplifier, insensitive to CMOS process variations in 2016 [
14]. In 2018 Kulej et al. presented bulk-driven 0.5 V amplifiers, exploiting different gain-boosting techniques in 0.18 µm CMOS process [
12]. In 2020 the same authors presented an ULV-ULP class AB amplifier, biased in deep sub-threshold region, that exploits the body-driven non-tailed differential pair [
13], attaining state of the art performance in terms of the most important figures of merit.
Inverter-based solutions [
15,
16,
17,
18] exploit the CMOS inverter, or inverter-like structures, such as the Arbel cell [
19], as building blocks that allow rail-to-rail signal swing with reduced supply voltages. Moreover, in these structures, the elimination of the bias current generator of the differential pair worsens the common mode rejection (CMRR) and results in large variations of small signal parameters under PVT variations.
In this paper, we propose an inverter-based, differential, body-driven input stage, with a replica bias loop that accurately sets the common mode current of the input stage by controlling the gate terminals of the MOS devices. The novel input stage is used to build an ULV, ULP, two-stage amplifier, in which a dual path compensation strategy is exploited to improve the frequency response of the amplifier.
The paper is structured as follows:
Section 2 presents the proposed amplifier topology and describes the replica bias loop that sets the common mode current of the inverter based input stage as well as the CMFF technique adopted to improve the CMRR.
Section 3 focuses on small signal analysis of dc-gain, CMRR, and frequency response explaining the adopted compensation strategy.
Section 4 discusses the design of the amplifier and presents the simulation results and comparisons with ULV, ULP state of the art amplifiers. Finally some conclusions are reported in
Section 5.
2. Proposed Topology
Due to its capability to allow almost rail-to-rail input and output swing, the Arbel cell (or differential inverter) is often used as a building block for low-voltage analog CMOS circuits. To further reduce the minimum supply voltage of the Arbel cell, the bias current generators can be removed and the common mode current can be set by controlling the body terminals of MOS transistors following the approach proposed in [
20]. However, for supply voltages lower than 0.5 V, the limited swing of the control voltage at the body terminals reduces the effectiveness of the current setting loop. To overcome this limitation, we propose a body-driven fully differential inverter (
Figure 1a) as input stage of the amplifier. We then exploit the gate terminals of the four MOS devices to set both the common mode current by means of a replica bias control loop, and the output common mode voltage through a common mode feed-forward (CMFF) approach. By using the gates as control terminals we are able to enhance the loop gain, thus requiring a smaller swing of the control voltages to guarantee proper operation of the bias control loop even at a very low supply voltage.
A simple push-pull second stage (
Figure 1b) is exploited to convert the differential output of the first stage to a single-ended one, providing further gain to compensate for the reduced gain of the first stage due to the use of the body transconductance. One output of the first stage is directly applied to the gate of the PMOS common-source device, whereas the other one is applied to a NMOS common-source followed by a current mirror, to provide the required dc reversal needed both for the dual path compensation strategy and to improve the CMRR. The bias current of the output stage is given by:
where M is the ratio between the form factor (
/
) of transistor
and the form factor (
/
) of transistor
.
is therefore determined by the current source
, by the sizing of
, and by the current mirror ratio M. This is also the maximum current that can be sinked by the stage, that thus presents a class-A behavior, whereas the maximum sourced current is limited only by the available excursion of the gate voltage of
.
The replica bias loop to set the common mode current of the first stage is shown in
Figure 2. The reference current, set by transistor
, is applied to devices
-
, that are a replica of the N-part of the input stage and are diode connected: The loop acts varying the gate voltage
to contrast variations of the input common mode and of device parameters. This bias voltage is applied to the gates of the NMOS transistors of the input stage, thus setting its bias current to a scaled replica of the reference current (scaling factor is given by the ratio of the form factors of the devices).
The gate control voltage
is exploited to set the output common voltage of the first stage using a common mode feed-forward (CMFF) technique: In the left part of
Figure 2, the reference current is mirrored through devices
-
and applied to
-
that are a replica of the P-part of the input stage and are diode connected. The gate voltage
is applied to the PMOS transistor of the input stage, thus forming a current mirror, and it can be shown (detailed analysis in the
Appendix A) that the output common mode voltage of the first stage is set to
. The proposed CMFF does not exploit any reference to set the value of the output common mode voltage of the input stage that is determined by the sizing of the devices. In fact, by looking at
Figure 2, it is evident that
is equal to (
-
), and therefore, the output common mode is set close to the analog ground for an appropriate sizing of
. For example, assuming a dual supply voltage with
= 0.15 V and
= −0.15 V,
can be set to about 0.15 V in order to have
about equal to 0 V which in this example is the analog ground.