A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

Abstract

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.

1. Introduction

The scaling of CMOS technology, and the diffusion of applications requiring very low power consumption, such as IoT (Internet of Things) nodes [1,2] or biomedical and wearable devices [3,4], have paved the way to the development of compact and ultralow voltage (ULV) circuits. The operation of MOS devices in the deep subthreshold region is mandatory [5,6], to achieve ultralow-power (ULP) consumption and to allow the usage of very low supply voltages.

However, to allow such ultralow supply voltages, specific design approaches are required: floating-gate [7] techniques have been proposed in the past, but the most common solutions are the body-driven (BD) technique and the inverter-based design approach.

Several amplifier designs operating at supply voltages in the order of 0.6 V or lower and exploiting multi-stage, folded cascode or symmetrical OTA topologies have been presented in the last years. The use of a very low supply voltage often requires to eliminate the bias current generator of the differential pair: the resulting pseudo-differential amplifier shows class-AB behavior, but no common mode rejection if the common mode output is exploited. Moreover, there is no control on the bias current, resulting in large variations of small signal performances under process, supply voltage and temperature (PVT) variations.

In BD amplifiers [8,9,10,11,12,13], the body is used as input terminal instead of the gate, thus allowing the input dc level not to be constrained by the threshold voltage of the devices, at the cost of reduced transconductance gain, higher noise, and an input impedance that is not purely capacitive. In this context, Ferreira et al. proposed a Miller amplifier designed in 350 nm CMOS process and operating at a supply voltage of 0.6 V in 2007 [8]. Magnelli et al. published an amplifier with a supply voltage of 0.5 V and 75 nW power consumption in 2014 [10]. In the same year, Ferreira et al. designed an amplifier with a supply voltage as low as 0.25 V [9]. Abdelfattah et al. presented an ULV self-biased amplifier, insensitive to CMOS process variations in 2016 [14]. In 2018 Kulej et al. presented bulk-driven 0.5 V amplifiers, exploiting different gain-boosting techniques in 0.18 µm CMOS process [12]. In 2020 the same authors presented an ULV-ULP class AB amplifier, biased in deep sub-threshold region, that exploits the body-driven non-tailed differential pair [13], attaining state of the art performance in terms of the most important figures of merit.

Inverter-based solutions [15,16,17,18] exploit the CMOS inverter, or inverter-like structures, such as the Arbel cell [19], as building blocks that allow rail-to-rail signal swing with reduced supply voltages. Moreover, in these structures, the elimination of the bias current generator of the differential pair worsens the common mode rejection (CMRR) and results in large variations of small signal parameters under PVT variations.

In this paper, we propose an inverter-based, differential, body-driven input stage, with a replica bias loop that accurately sets the common mode current of the input stage by controlling the gate terminals of the MOS devices. The novel input stage is used to build an ULV, ULP, two-stage amplifier, in which a dual path compensation strategy is exploited to improve the frequency response of the amplifier.

The paper is structured as follows: Section 2 presents the proposed amplifier topology and describes the replica bias loop that sets the common mode current of the inverter based input stage as well as the CMFF technique adopted to improve the CMRR. Section 3 focuses on small signal analysis of dc-gain, CMRR, and frequency response explaining the adopted compensation strategy. Section 4 discusses the design of the amplifier and presents the simulation results and comparisons with ULV, ULP state of the art amplifiers. Finally some conclusions are reported in Section 5.

2. Proposed Topology

Due to its capability to allow almost rail-to-rail input and output swing, the Arbel cell (or differential inverter) is often used as a building block for low-voltage analog CMOS circuits. To further reduce the minimum supply voltage of the Arbel cell, the bias current generators can be removed and the common mode current can be set by controlling the body terminals of MOS transistors following the approach proposed in [20]. However, for supply voltages lower than 0.5 V, the limited swing of the control voltage at the body terminals reduces the effectiveness of the current setting loop. To overcome this limitation, we propose a body-driven fully differential inverter (Figure 1a) as input stage of the amplifier. We then exploit the gate terminals of the four MOS devices to set both the common mode current by means of a replica bias control loop, and the output common mode voltage through a common mode feed-forward (CMFF) approach. By using the gates as control terminals we are able to enhance the loop gain, thus requiring a smaller swing of the control voltages to guarantee proper operation of the bias control loop even at a very low supply voltage.

A simple push-pull second stage (Figure 1b) is exploited to convert the differential output of the first stage to a single-ended one, providing further gain to compensate for the reduced gain of the first stage due to the use of the body transconductance. One output of the first stage is directly applied to the gate of the PMOS common-source device, whereas the other one is applied to a NMOS common-source followed by a current mirror, to provide the required dc reversal needed both for the dual path compensation strategy and to improve the CMRR. The bias current of the output stage is given by:

$$I_{oQ}=M\left(I_6-I_5\right),$$

(1)

where M is the ratio between the form factor ($W_8$/$L_8$) of transistor $M_8$ and the form factor ($W_7$/$L_7$) of transistor $M_7$. $I_{oQ}$ is therefore determined by the current source $M_6$, by the sizing of $M_5$, and by the current mirror ratio M. This is also the maximum current that can be sinked by the stage, that thus presents a class-A behavior, whereas the maximum sourced current is limited only by the available excursion of the gate voltage of $M_9$.

The replica bias loop to set the common mode current of the first stage is shown in Figure 2. The reference current, set by transistor $M_{b1}$, is applied to devices $M_{b2}$-$M_{b3}$, that are a replica of the N-part of the input stage and are diode connected: The loop acts varying the gate voltage $V_B$ to contrast variations of the input common mode and of device parameters. This bias voltage is applied to the gates of the NMOS transistors of the input stage, thus setting its bias current to a scaled replica of the reference current (scaling factor is given by the ratio of the form factors of the devices).

The gate control voltage $V_A$ is exploited to set the output common voltage of the first stage using a common mode feed-forward (CMFF) technique: In the left part of Figure 2, the reference current is mirrored through devices $M_{b4}$-$M_{b5}$ and applied to $M_{b6}$-$M_{b7}$ that are a replica of the P-part of the input stage and are diode connected. The gate voltage $V_A$ is applied to the PMOS transistor of the input stage, thus forming a current mirror, and it can be shown (detailed analysis in the Appendix A) that the output common mode voltage of the first stage is set to $V_A$. The proposed CMFF does not exploit any reference to set the value of the output common mode voltage of the input stage that is determined by the sizing of the devices. In fact, by looking at Figure 2, it is evident that $V_A$ is equal to ($V_{DD}$-$|V_{GSb6}|$), and therefore, the output common mode is set close to the analog ground for an appropriate sizing of $|V_{GSb6}|$. For example, assuming a dual supply voltage with $V_{DD}$ = 0.15 V and $V_{SS}$ = −0.15 V, $|V_{GSb6}|$ can be set to about 0.15 V in order to have $V_A$ about equal to 0 V which in this example is the analog ground.

3. Small Signal Analysis

In this section, we report the small signal analysis of the proposed amplifier focusing both on the dc performance (in terms of differential gain and CMRR) and ac performance by computing the frequency response and presenting considerations about the compensation strategy.

3.1. DC-Gain and Common Mode Rejection

The replica bias stage contributes to enhance the common mode rejection ratio (CMRR) of the input stage that would otherwise be one (same gain for differential and common mode signals). Denoting with $V_{id}$ and $V_{o1d}$ the input and the output differential voltage of the input stage, respectively, the differential gain can be easily derived referring to the circuit in Figure 1a:

$$A_{d1}=\frac{V_{o1d}}{V_{id}}=\frac{V_{o1p}-V_{o1m}}{V_{ip}-V_{im}}=\frac{G_1}{G_{o1}}=\frac{g_{m{b}_1}+g_{m{b}_3}}{g_{d{s}_1}+g_{d{s}_3}}$$

(2)

where $G_1$ and $G_{o1}$ are the transconductance and the output conductance of the input stage respectively, $g_{mb}$, $g_m$ and $g_{ds}$ denote the body transconductance, the gate transconductance and the output conductance of the different MOS transistors, as usual, and the subscripts 1 and 3 refer to PMOS and NMOS devices in Figure 1a, respectively.

Denoting with $V_{ic}$ = ($V_{ip}$+$V_{im}$)/2 and $V_{oc}$ = ($V_{o1p}$+$V_{o1m}$)/2 the input and output common mode voltage of the input stage, respectively, the common mode gain, with the effect of the replica bias control loop, can be derived referring to the common mode equivalent circuit of the input stage shown in Figure 3:

$$A_{c1}=\frac{V_{o1c}}{V_{ic}}=-\frac{g_{m_1}{g}_{m{b}_3}+\left(g_{m{b}_1}+g_{m{b}_3}\right)g_{d{s}_3}}{\left(g_{m_3}+g_{d{s}_3}\right)\left(g_{m_1}+g_{d{s}_3}+g_{d{s}_1}\right)}\approx -\frac{g_{m{b}_1}}{g_{m_1}}$$

(3)

where the approximation holds with the usual assumtpions $g_m>>g_{mb}$ and $g_m>>g_{ds}$. The resulting CMRR can then be calculated as

$$CMR{R}_1=\frac{A_{d1}}{A_{c1}}=\frac{g_{m{b}_1}+g_{m{b}_3}}{g_{m{b}_1}}\frac{g_{m_1}}{g_{d{s}_1}+g_{d{s}_3}}$$

(4)

and is proportional to the intrinsic gain $g_m/g_{ds}$ of the devices.

The CMRR is further improved by the second stage, since, with the dual path approach, the common mode components at the output of the first stage arrive to the output with opposite phases. The analysis of the circuit in Figure 1b provides:

$$V_o=\left(g_{m_8}\frac{g_{m_5}}{g_{m_7}}{V}_{o{1}_p}-g_{m_9}{V}_{o{1}_n}\right)\frac{1}{G_o}$$

(5)

where $V_{o1p}$ and $V_{o1m}$ can be expressed as follows:

$$V_{o_{1p,m}}=\pm A_{d_1}\frac{V_{id}}{2}+A_{c_1}{V}_{ic}$$

(6)

and

$$G_o=g_{d{s}_8}+g_{d{s}_9}$$

(7)

is the output conductance of the second stage.

The overall CMRR is therefore given by

$$CMRR=CMR{R}_1·CMR{R}_2$$

(8)

with,

$$CMR{R}_2=\frac{1}{2}\frac{g_{m_5}{g}_{m_8}+g_{m_7}{g}_{m_9}}{g_{m_5}{g}_{m_8}-g_{m_7}{g}_{m_9}}$$

(9)

It is clear from (9) that the CMRR can become infinite by choosing:

$$g_{m_5}{g}_{m_8}=g_{m_7}{g}_{m_9}$$

(10)

3.2. Frequency Response and Compensation

The use of a dual signal path in the second stage allows some flexibility in optimizing the frequency response: in particular, the zero provided by the dual path can be exploited to cancel one pole of the overall transfer function thus improving the phase margin.

An approximate analysis of the amplifier can be carried out by exploiting the Miller approximation and referring to the small signal equivalent circuit reported in Figure 4, where $G_1$ and $G_{o1}$ are defined in (2), $G_o$ is given by (7), $C_L$ is the load capacitance and the other capacitances can be expressed as

$$C_1=C_{g{d}_1}+C_{g{d}_3}+C_{d{b}_1}+C_{d{b}_3}+C_{g{s}_9}+C_{g{d}_9}\left(1+g_{m_9}/G_o\right)$$

(11)

$$C_2=C_{g{d}_1}+C_{g{d}_3}+C_{d{b}_1}+C_{d{b}_3}+C_{g{s}_5}+C_{g{d}_5}\left(1+g_{m_5}/g_{m_7}\right)$$

(12)

$$C_x=C_{g{d}_5}\left(1+\frac{g_{m_7}}{g_{m_5}}\right)+C_{g{d}_6}+C_{g{s}_7}+C_{g{s}_8}+C_{g{d}_8}\left(1+\frac{g_{m_8}}{G_o}\right)$$

(13)

Since $C_1$ results much larger than $C_2$, the transfer function $V_o/V_{id}$ has to be calculated by separately considering the paths from $V_{ip}$=$V_{id}/2$ and $V_{im}$= $-V_{id}/2$ to $V_o$:

$$A_d\left(s\right)=\frac{V_o}{V_{ip}}{{|}_{V_{im}=0}+\frac{V_o}{V_{im}}|}_{V_{ip}=0}$$

(14)

The analysis of the circuit in Figure 4 yields a transfer function in the form:

$$A_d\left(s\right)=\frac{A_{0}N\left(s\right)}{\left(1+s{\tau }_1\right)\left(1+s{\tau }_2\right)\left(1+s{\tau }_3\right)\left(1+s{\tau }_4\right)}$$

(15)

where

$$A_0=\frac{G_1}{2G_{o1}}\left(g_{m9}+g_{m8}\frac{g_{m5}}{g_{m7}}\right)\frac{1}{G_o}$$

(16)

is the dc gain, the time constants of the poles are

$${\tau }_1=C_L/G_o$$

(17)

$${\tau }_2=C_1/G_{o1}$$

(18)

$${\tau }_3=C_2/G_{o1}$$

(19)

$${\tau }_4=C_x/g_{m7}$$

(20)

and

$$N\left(s\right)=1+s\frac{C_1{g}_{m8}{g}_{m5}+C_2{g}_{m9}{g}_{m7}+C_x{G}_{o1}{g}_{m9}}{G_{o1}\left(g_{m8}{g}_{m5}+g_{m9}{g}_{m7}\right)}+s^2\frac{C_x{C}_2{g}_{m9}}{G_{o1}\left(g_{m8}{g}_{m5}+g_{m9}{g}_{m7}\right)}$$

(21)

which can be solved by means of well known approximations to obtain the expression of the two zeros as follows:

$${\tau }_{z1}\approx \frac{C_1{g}_{m8}{g}_{m5}+C_2{g}_{m7}{g}_{m9}+C_x{G}_{o1}{g}_{m9}}{G_{o1}\left(g_{m8}{g}_{m5}+g_{m7}{g}_{m9}\right)}$$

(22)

$${\tau }_{z2}\approx \frac{g_{m9}{C}_x{C}_2}{C_1{g}_{m8}{g}_{m5}+C_2{g}_{m7}{g}_{m9}+C_x{G}_{o1}{g}_{m9}}$$

(23)

For large load capacitances $C_L$, $1/{\tau }_1$ is the dominant pole, and the circuit can be sized to cancel the second pole with one of the zeros, thus improving the phase margin and providing stability without sacrificing the bandwidth. To add a further degree of freedom and achieve an adequate phase margin even for smaller load capacitances, a compensation capacitor $C_c$ can be added between $V_{o1n}$ and $V_o$ (i.e., between gate and drain of $M_9$ in Figure 1b): Its pole-splitting effect leads to some reduction of the bandwidth that is however negligible if $C_c<<C_L$ and moves the pole $1/{\tau }_2$, placing it nearer to the zero $1/{\tau }_{z1}$. To evaluate the effect of $C_c$, we can still exploit the Miller approximation and use the previous results; the capacitance $C_L$ now becomes

$$C_L^{\prime }=C_L+C_c$$

(24)

and the capacitance $C_1$ has to be substituted by

$$C_1^{\prime }=C_1+C_c\left(1+\frac{g_{m9}}{G_o}\right)\approx C_c\frac{g_{m9}}{G_o}$$

(25)

The expression of the Gain Bandwidth product for the proposed amplifier can be easily derived by combining Equations (16) and (17) as follows:

$$GBW=A_0·\frac{G_0}{C_L}=\frac{1}{2}\frac{g_{m{b}_1}+g_{m{b}_3}}{g_{d{s}_1}+g_{d{s}_3}}\left(g_{m9}+g_{m8}\frac{g_{m5}}{g_{m7}}\right)\frac{1}{C_L}$$

(26)

A simple expression of the negative slew rate $S{R}_{-}$ can be obtained by noting that, during the discharge of the load capacitor $C_L$, the amplifier exhibits a class A behaviour with a bias current given by $M·I_{bias}$:

$$S{R}_{-}=\frac{M·I_6}{C_L}$$

(27)

During the charge of the load capacitor $C_L$, the amplifier exhibits a class B behaviour (maximum current is only limited by the voltage swing at the gate of $M_9$), and a formula expressing the positive slew rate $S{R}_{+}$ can be obtained by using the equation for the subthreshold conduction of the MOS transistor [21] as follows:

$$S{R}_{+}=\frac{I_{D_{0_9}}·exp\left(\frac{V_{DD}+|V_{SS}|-|V_{th}|}{n·U_T}\right)}{C_L}$$

(28)

A theoretical analysis of offset and noise performance of the proposed amplifier is reported in the Appendix A.

4. Amplifier Design and Simulation Results

The proposed amplifier has been designed in a 130 nm CMOS technology from STMicroelectronics featuring a $|V_{th}|\approx 0.35V$.

4.1. Sizing

All the devices have been biased in the subthreshold region at |$V_{gs}$|=|$V_{ds}$| = 150 mV, and a dual supply of ±0.15 V with $V_{DD}$−$V_{SS}$ = 2|$V_{gs}$| has been adopted. All the devices in the circuit have been sized with extremely long gates: this choice allows to minimize noise and increase the output resistance and the intrinsic gain of MOS devices as shown in [13]. The bias current of transistors in the input stage has been set to 5 nA as a tradeoff between power consumption and noise performance. For what concerns the second stage, simulations have shown that a design maximizing the CMRR according to (10) is very sensitive not only to mismatches but also to PVT variations; the stage has thus been optimized to provide good CMRR performance in the different PVT conditions by means of a design centering approach.

To minimize power consumption, a 4 nA bias current has been adopted for the second stage. Even if this current is lower than the bias current of the first stage, the amplifier can still be efficiently compensated because the body driven input stage has a much lower transconductance than the second stage. A load capacitance $C_L$ of 50 pF has been assumed and a compensation capacitor $C_c$ of 1.2 pF has been added to provide an adequate phase margin.

Table 1. Nominal transconductance, sizing and output resistance of transistors.

	W [μm]	L [μm]	${\mathbf{I}}_{\mathbf{D}}$ [nA]	${\mathbf{g}}_{\mathbf{m}}$ [$\mathbf{nS}$]	${\mathbf{g}}_{\mathbf{mb}}$ [$\mathbf{nS}$]	${\mathbf{r}}_{\mathbf{ds}}$ [$\mathbf{G}\mathbf{\Omega }$]
$M_1$,$M_2$,$M_{b6}$, $M_{b7}$	6.63	10	5	152.1	25.44	1.864
$M_3$,$M_4$,$M_{b2}$,$M_{b3}$,$M_{b4}$,$M_{b5}$	0.9	10	5	131.8	23.68	0.667
$M_{b1}$	6.63	10	10	304.3	50.89	0.932
$M_6$	20	7.53	4	121.8	20.78	2.229
$M_9$	10	7.53	4	121.8	20.78	0.037
$M_5$,$M_7$	0.73	10	2	55.65	50.89	0.93
$M_8$	1.47	10	4	111.3	23.5	0.85

reports sizing, bias current, and small signal parameters for all the devices.

4.2. Simulation Results

The circuit has been simulated in the Cadence Virtuoso environment to test both open-loop and closed-loop performance. Figure 5 reports the magnitude and phase of the open-loop differential gain: a 64.6 dB dc gain with a 3.58 kHz unity gain frequency and a phase margin of about 54° are achieved in typical conditions. The amplifier has been simulated in a unity-gain buffer configuration to test closed-loop performance. Figure 6a shows the dc input-output characteristic of the buffer, highlighting a rail-to-rail output swing. The bias control loop is able to keep the common mode current of the input stage constant under input common mode variations, as shown in Figure 6b, thus improving common mode rejection and linearity. The CMRR is approximately 61 dB as shown in Figure 7. Supply rejection is around 27 dB, and the amplifier power dissipation is only 11.4 nW.

The slew rate has been evaluated simulating the response to a full swing (300 $m{V}_{pp}$) input step, shown in Figure 8: The positive slew rate is 1.7 V/ms, whereas a much lower negative slew rate of 0.14 V/ms is achieved, limited by the current source $M_6$. Total harmonic distortion (THD) for a 300 $m{V}_{pp}$ input signal at 10 Hz is 0.84%. To give more detailed informations about linearity performance, the THD versus the peak-to-peak input voltage is shown In Figure 9a, whereas the differential voltage gain (in dB) as a function of the input common mode voltage is reported in Figure 9b to demonstrate the almost rail to rail input voltage range of the proposed amplifier. Finally the equivalent input referred noise is depicted in Figure 10 showing a spot noise at 100 Hz of about 2.69 $\mu V/\sqrt{Hz}$.

An area footprint of the amplifier of about 0.0064 mm${}^2$ has been estimanted by using the Cadence Layout XL tool.

To assess the robustness of the proposed design, PVT and Monte-Carlo simulations have been carried out.

Table 2. Amplifier performance for different process corners.

	TT	SS	FF	SF	FS
$Gain\left[dB\right]$	64.60	59.85	68.83	64.96	62.90
$GBW\left[kHz\right]$	3.58	2.56	4.15	3.59	3.18
$m\phi \left[deg\right]$	53.76	59.04	45.77	52.22	60.98
$CMRR\left[dB\right]$	61	59.83	67.51	65.02	62.85
$PSR{R}_{+}/PSR{R}_{-}\left[dB\right]$	26/28	23/26	28/29	27/28	24/26
$S{R}_{+}/S{R}_{-}[V/ms]$	1.7/0.15	1.19/0.15	2.31/0.15	2.46/0.15	1.09/0.15
$S{R}_{AVG};[V/ms]$	≈0.93	≈0.67	≈1.23	≈1.31	≈0.62
$noise[\mu V/\sqrt{Hz}]$	0.76	0.71	0.78	0.77	0.74
$P_{DISS}\left[nW\right]$	10.9	11.8	10.95	9.9	11.36

reports the simulated performance under different process corners, highlighting a very good stability of the amplifier performance. The amplifier’s robustness has been tested also under supply voltage and temperature variations. Main amplifier parameters under supply voltage variations from 0.24 to 0.36 V are reported in

Table 3. Amplifier performance vs. supply voltage $V_{DD}$−$V_{SS}$.

$V_{DD}-V_{SS}\left[V\right]$	0.24	0.26	0.28	0.3	0.32	0.34	0.36
$Gain\left[dB\right]$	41.8	50.06	57.71	64.6	70.71	75.96	80.05
$GBW\left[kHz\right]$	1.05	1.78	2.5	3.58	4.42	4.86	4.92
$m\phi \left[deg\right]$	71.47	66.75	64.27	53.76	40.97	31.91	29.02
$S{R}_{+}[V/ms]$	0.54	0.86	1.27	1.7	2.03	2.18	2.18
$S{R}_{-}[V/ms]$	0.14	0.14	0.15	0.15	0.15	0.15	0.15

, whereas simulation results under temperature variations in the range from −10 °C to 110 °C are shown in

Table 4. Amplifier performance vs. temperature.

$T\left[C\right]$	−10	0	27	50	80	110
$Gain\left[dB\right]$	55.05	57.76	64.6	67.51	61.36	50.07
$GBW\left[kHz\right]$	1.87	2.228	3.58	3.89	2.49	1.159
$m\phi \left[deg\right]$	59.74	61.06	53.76	48.45	67.84	83.52
$S{R}_{+}[V/ms]$	1.11	1.28	1.7	1.96	2.16	2.29
$S{R}_{-}[V/ms]$	0.14	0.15	0.15	0.15	0.14	0.13
$Pdiss\left[nW\right]$	12.0	11.9	9.9	10.9	11.1	11.96

.

Monte-Carlo simulations have been performed to evaluate the effect of mismatches;

Table 5. Monte Carlo simulations.

	Mean	Std_dev
$Gain\left[dB\right]$	65.48	7.43
$GBW\left[kHz\right]$	2.33	1.21
$m\phi \left[deg\right]$	50.14	13.7
$CMRR\left[dB\right]$	46.5	10.7
$S{R}_{+}[V/ms]$	2.51	0.062
$S{R}_{-}[V/ms]$	0.183	0.006
$Pdiss\left[nW\right]$	11.35	0.831
$V_{offset}$ [mV]	2.91	5.01

reports mean values and standard deviations of the main performance parameters for a 200-run Monte-Carlo mismatch simulation, highlighting a good stability.

4.3. Results and Comparision

Table 6. Comparison with ultralow voltage (ULV) state of the art amplifiers.

	This Work	[13]	[18]	[22]	[12]	[23]	[14]	[10]	[9]	[8]
Year	2021	2020	2020	2020	2018	2018	2015	2014	2014	2007
Technology $\left[\mu m\right]$	0.13	0.18	0.18	0.18	0.18	0.04	0.065	0.18	0.13	0.35
$V_{DD}\left[V\right]$	0.3	0.3	0.3	0.5	0.3	0.6	0.35	0.5	0.25	0.6
$V_{DD}/V_{TH}\left[V\right]$	0.86	0.6	0.6	1.19	0.6	1.27	1.16	1.29	1.16	1.02
$D{C}_{gain}\left[dB\right]$	64.6	64.7	39	69.5	65.8	41.35	43	70	60	69.4
$C_L\left[pF\right]$	50	30	10	15	20	5	3	30	15	15
$GBW\left[kHz\right]$	3.58	2.96	0.9	36	2.78	8260	3600	18	1.88	11.3
$m\phi \left[deg\right]$	53.76	52	90	65	61	86.6	56	55	52.5	65
$S{R}_{+}[V/ms]$	1.7	1.9	-	9.7	6.44	844	5600	3	0.64	14.6
$S{R}_{-}[V/ms]$	0.15	6.4	-	9.7	7.8	844	5600	3	0.77	14.6
$S{R}_{avg}[V/ms]$	0.93	4.15	-	9.7	7.12	844	5600	3	0.71	14.6
$CMRR\left[dB\right]$	61	110	30	90	72	52	46	-	-	75
$spot-noise[\mu V/\sqrt{Hz}]$	2.69	1.6	0.81	0.91	1.85	-	0.93	0.31	3.3	0.29
@freq	100	-	1000	1000	36	-	-	1000	100	1000
$Power\left[nW\right]$	11.4	12.6	0.6	60	15.4	15,735	17,000	75	18	548
$Mode$	BD	BD	GD	BD	BD	GD	BD	GD	BD	BD
$FO{M}_1[MHz·pF/mA]$	4711	2114	4500	4500	1083	1575	223	3600	392	186
$FO{M}_2[V·pF/(\mu s·mA)]$	1224	2964	-	1213	2790	161	346	680	146	240
$FO{M}_3[MHz·pF/mW]$	15,702	7047	15,000	9000	3610	2625	635	7200	1568	311
$FO{M}_4[V·pF/(\mu s·mW)]$	4079	9880	-	2425	9247	268	988	1200	587	400
$FO{M}_{4_{WC}}[V·pF/(\mu s·mW)]$	658	4524	-	2425	8364	268	988	1200	583	400
$Area\left[m{m}^2\right]$	0.0064	0.0085	0.00047	0.0034	0.0082	-	0.0050	0.057	0.083	0.06

compares the simulated performance of the proposed amplifier with other ULV, ULP implementations from the literature. In order to compare the performance of several different designs, we have considered the usually adopted four figures of merit (FOMs) defined as follows:

$$FO{M}_1=\frac{GBW·C_L}{I_{TOT}}$$

(29)

$$FO{M}_2=\frac{S{R}_{AVG}·C_L}{I_{TOT}}$$

(30)

$$FO{M}_3=\frac{GBW·C_L}{P_{DISS}}$$

(31)

$$FO{M}_4=\frac{S{R}_{AVG}·C_L}{P_{DISS}}$$

(32)

$$FO{M}_{4_{WC}}=\frac{S{R}_{WC}·C_L}{P_{DISS}}$$

(33)

where the large signal $FO{M}_4$ has been computed both referring to the average slew rate and to the worst case one ($FO{M}_{4_{WC}}$). The comparison in Table 6 shows the effectiveness of the proposed approach: Extremely high values of the small signal FOMs ($FO{M}_1$ and $FO{M}_3$) are achieved. $FO{M}_3$ is particularly high thanks to the adoption of an extremely low supply voltage. This result is due to the combination of an Arbel-type approach, that doubles the gain of the first stage and thus the GBW product, and a dual-path second stage that allows achieving stability without sacrificing the bandwidth. Similar values of the small signal FOMs are obtained only by [22], that however uses a higher supply voltage, resulting in a lower $FO{M}_3$, and [18]. This latter however is a single-stage amplifier with limited input common mode range and which provides a much lower gain, and is biased at an extremely low current; no additional circuit is used to stabilize the dc current, that therefore presents large variations in PVT conditions. The proposed amplifier has not been optimized for large signal performance, and the negative slew rate is limited by the bias current set by $M_6$ resulting in a limited value for the worst case large signal $FO{M}_{4_{WC}}$. If we consider the average slew rate for the computation of the large signal $FO{M}_4$, the obtained values are comparable with state-of-the-art class-A amplifiers. Much better $FO{M}_4$ is achieved only by [12,13] that present a class-AB behavior.

5. Conclusions

In this paper, we have proposed an ultralow voltage Amplifier operating at 0.3 V supply voltage. The Arbel (differential inverter) approach and a dual-path differential-to-single-ended second stage are exploited to achieve 64.6 dB gain with high CMRR and an extremely high efficiency, resulting in an unity-gain frequency of about 3.6 kHz for a 50 pF load with a power consumption of only 11.4 nW. A replica-based bias control loop and a common-mode feed-forward approach are exploited to set the bias current and the output common mode voltage of the input stage, thus allowing a high robustness against PVT and mismatch variations. Comparison against the state of the art has shown that the proposed amplifier outperforms all the previously published Amplifiers in terms of the small signal figures of merit, while guaranteeing a very good tradeoff between noise, power consumption, area footprint, gain and CMRR.