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Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition

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A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: 20 September 2026 | Viewed by 3243

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Editors

Prof. Dr. Alexander Barkalov

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Guest Editor

Institute of Metrology, Electronics and Computer Science, University of Zielona Gora, 65-417 Zielona Gora, Poland
Interests: logic synthesis; FSM design; FPGA; ASIC; embedded systems; CAD of VLSI-based digital systems
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Prof. Dr. Larysa Titarenko

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Guest Editor

Institute of Metrology, Electronics and Computer Science, University of Zielona Gora, 65-417 Zielona Gora, Poland
Interests: logic synthesis; FSM design; FPGA; ASIC; telecommunications; antenna arrays; hardware-software co-design; CAD of VLSI-based digital systems
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Dr. Kazimierz Krzywicki

E-Mail Website
Guest Editor

Department of Technology, The Jacob of Paradies University, ul. Fryderyka Chopina 52/b.7, 66-400 Gorzow Wielkopolski, Poland
Interests: distributed embedded systems; embedded system design; IoT; hardware synthesis; process control
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

As you know, virtually every aspect of human functioning depends on the widespread use of and advances in electrical, electronic, and telecommunications engineering. Over the past decade, “Electrical, Electronics and Communications Engineering”, a Section of Applied Sciences, has published many papers dedicated to the fundamental and applied aspects of these three important disciplines.

This Special Issue, “Feature Paper Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition”, to be published in 2024–2025, will present a collection of feature papers on recent developments in these areas of science.

We are seeking papers related (but not limited) to the following:

Fundamental problems in modern electrical engineering.
Fundamental problems in modern electronic engineering.
Fundamental problems in telecommunication systems.
Development and use of mathematical models to simulate components and their interaction within electrical circuits and systems.
Development of new tools for circuit analysis.
Prevention of interference between different electrical components or systems.
Automatization of component selection.
Development of tools for preventing voltage drop.
Reducing circuit noise.
Improving the power quality of circuits and systems.
Development of tools for protection from overvoltage.
Development of tools for lightning protection.
Improving heat managing in circuits and systems.
Using troubleshooting techniques in design.
Improving signal processing.
Signal processing and communication techniques in modern electrical engineering.
Emerging trends in electrical engineering.
Development methods aimed at Smart Grids.
Development of telecommunication tools aimed in 5G Networks.
Development of telecommunication tools providing secure and reliable services.
Development and use of artificial intelligence (AI) tools in telecommunication systems.
Using machine learning applications in telecommunication systems.
Development of telecommunication tools oriented on Internet of Things.
Development of Machine to Machine (M2M) devices.
Using cloud computing in telecommunications.
Decentralized telecom networks.
Virtualized network services in telecommunications.
Using new wireless technologies in telecommunications.
Development of tools for defence from cyberattacks.
Using green technologies in telecommunication systems.

For this Special Issue, we seek papers that feature original research, as well as review articles. The journal offers high-quality peer review and a rapid publication process. Submission to this Special Issue is now open and will be open until 31 March 2025. Invited papers may be considered for a full or partial waiver of the publication cost. If you would like to be invited to contribute to this Special Issue, please send the (tentative) title and abstract of your potential paper/review to one of the two Co-Guest Editors listed below.

We look forward to receiving your insightful contribution.

Prof. Dr. Alexander Barkalov
Prof. Dr. Larysa Titarenko
Dr. Kazimierz Krzywicki
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-anonymized peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

electrical engineering
electronics
telecommunications
analysis
improvement

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Published Papers (10 papers)

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Research

21 pages, 503 KB

Open AccessArticle

Hierarchical Modulation Classification with Channel-Type-Guided Blind Preprocessing for High-Order QAM in Multipath Fading Channels

by Sungsoo Park and Gyuyeol Kong

Appl. Sci. 2026, 16(13), 6568; https://doi.org/10.3390/app16136568 - 1 Jul 2026

Viewed by 102

Abstract

Automatic modulation classification (AMC) becomes challenging in multipath fading channels, particularly for high-order quadrature amplitude modulation (QAM) signals whose constellation points are strongly distorted by inter-symbol interference, phase rotation, and fading. This paper presents a channel-type-guided hierarchical AMC framework that combines blind preprocessing with deep learning. In the first stage, the received in-phase and quadrature (IQ) signal is downsampled and preprocessed using blind signal processing techniques. Blind source separation (BSS) is used for additive white Gaussian noise (AWGN) and flat fading channels, whereas the constant modulus algorithm (CMA) followed by BSS is used for multipath fading channels. A convolutional neural network (CNN) then performs first-stage modulation classification and generates a QAM-family flag. If the first-stage output corresponds to a QAM-family signal, a second-stage refinement path is activated. In this path, a convolutional denoising autoencoder (CDAE) is applied to the original received signal to mitigate multipath-induced distortion, followed by BSS preprocessing and a dedicated CNN classifier for 16-QAM, 64-QAM, and 256-QAM. Simulation results over AWGN, flat fading, and multipath Rician fading channels show that the proposed hierarchy improves high-order QAM classification in the considered settings, especially for 64-QAM and 256-QAM under multipath fading with stronger time variation. Multi-frame Softmax averaging further improves decision stability. The results support the use of classical blind preprocessing and selective CDAE-based refinement as a practical, complementary front end for AMC in controlled multipath simulation scenarios, while real over-the-air validation and automatic channel-category detection remain future work. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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45 pages, 7798 KB

Open AccessArticle

FilterForge: An LLM-Based, Semi-Automated Agentic VS Code Extension for Microwave Bandpass Filter Design

by Hüseyin Nuri Gülmez, Yunus Koç, Agah Oktay Ertay, Bora Döken and Mesut Kartal

Appl. Sci. 2026, 16(13), 6379; https://doi.org/10.3390/app16136379 - 25 Jun 2026

Viewed by 189

Abstract

We present FilterForge, a chat-driven VS Code environment that pulls the synthesis, analysis, simulation, and optimization stages of microwave bandpass filter design, normally coordinated by hand across tools written in different languages, into one workflow. A deployed Model Context Protocol (MCP) server exposes deterministic Python implementations of coupling-matrix synthesis, uniform predistortion, topology reconfiguration, a genetic-algorithm transmission-zero selector, a mode-matching engine for H-plane iris-coupled rectangular waveguide geometries, and a skill that generates PyAEDT/HFSS notebooks for various dimensioning design-curves. A language-model orchestrator turns natural-language requests into typed tool calls, while every reported quantity stays inside the deterministic kernels, so the numerics remain reproducible and model-agnostic. We evaluate the call layer on a 45-task benchmark across the five tool categories: gemini-3-flash reaches

96.3 %

tool-selection and

94.8 %

full-call accuracy with an

88.9 %

pass³ rate, which an ablation traces to the curated tool-selection prompt rather than to raw model capability. The mode-matching engine is validated against full-wave HFSS on a six-pole 4 GHz Chebyshev filter tuned from the chat panel, and on an 8 GHz WR-112 counterpart taken end-to-end with no engineer in the loop, where a deterministic critique gates each round until a manufacturable geometry is reached. We then exercise the full workflow on two folded six-pole WR-90 cross-coupled filters at

10 GHz

, a high-selectivity design synthesized against a stop-band mask and a group-delay-equalized variant whose positive cross-coupling uses a pair of side-wall irises, the latter settling to a peak-to-peak in-band group-delay ripple below

1.5 ns

while recovering the synthesized return loss. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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15 pages, 6911 KB

Open AccessArticle

Theoretical Analysis and Optimization of Coupled Inductor for Boost-Extender Topology

by Vikas Kumar Rathore, Michael Evzelman and Mor Mordechai Peretz

Appl. Sci. 2026, 16(13), 6368; https://doi.org/10.3390/app16136368 - 25 Jun 2026

Viewed by 185

Abstract

A coupling coefficient optimization procedure for a boost-extender topology converter with coupled inductors is presented. The method focuses on minimizing inductor current ripple to reduce losses and improve magnetic core utilization, enabling a potential increase in converter power density. The major innovation of this study is the theoretical formulation of the coupling coefficient and leakage inductance in the UU/UI cores. The study includes a theoretical loss analysis covering two dominant loss mechanisms of the topology. A magnetic core structure enabling current ripple cancelation is presented and analyzed using a reluctance model. To address the analytically intractable field distribution at the core center tap, an empirical leakage model is introduced. The model is validated through ANSYS Maxwell simulations 2023.R1 and corroborated by experimental measurements. The results demonstrate that appropriate coupling coefficient selection significantly suppresses current ripple and enables a more efficient and compact converter design. Simulation and experimental results on experimental prototype of 100 W running at 100 kHz and attaining voltage gain of 20 V to 200 V confirm the accuracy of the models and the effectiveness of the optimization procedures. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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22 pages, 392 KB

Open AccessArticle

A Low-Power JPEG XS Frame Buffer Codec for On-Chip Display Systems

by Piotr Chodorowski and Dariusz Kania

Appl. Sci. 2026, 16(12), 6263; https://doi.org/10.3390/app16126263 - 22 Jun 2026

Viewed by 317

Abstract

Power consumption in portable display systems is significantly affected by the energy cost of frame buffer memory accesses between the graphics processing unit (GPU) and the display processing unit (DPU). This paper presents the design and FPGA implementation of a visually lossless frame buffer codec based on the JPEG XS standard, intended for integration into on-chip systems to reduce memory bandwidth and associated power consumption. The codec is implemented in VHDL and targets the AMD Artix UltraScale+ xcau15p-2ffvb676e device. The codec supports both the standard ISO/IEC 21122 entropy coding path and a simplified non-standard Golomb–Rice mode intended for closed on-chip systems. Post-place-and-route results at PPC = 4 show that the Standard Precinct codec occupies 22.0% of device LUTs, while the proposed Golomb–Rice variant requires only 15.8%. At a compression ratio of 11:1, the codec achieves a PSNR of 40.20 dB, consistent with visually lossless operation reported for JPEG XS. Power estimation at 200 MHz shows that the Golomb–Rice mode reduces total codec power consumption by 44 mW (4.7%) relative to the Standard Precinct mode, with the decoder contributing the majority of this saving. The proposed solution is applicable to portable devices with built-in displays, including smartphones, tablets, and augmented reality headsets, where tile-based frame buffer compression is required without inter-frame dependencies. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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14 pages, 4727 KB

Open AccessArticle

Aging Effect on IMC Evolution in Bi-Based and SAC Soldering Pastes on 3D-Shaped Aluminum Cores

by Aneta Chołaj, Marek Kościelski, Izabela Spocińska, Wojciech Szymański, Sonia Boczkal, Anna Sitek, Dorota Liszewska and Mirosław Kozłowski

Appl. Sci. 2026, 16(12), 5962; https://doi.org/10.3390/app16125962 - 12 Jun 2026

Viewed by 161

Abstract

The increasing power density of modern electronic systems intensifies challenges related to heat dissipation and long-term reliability. Insulated metal substrates (IMS), particularly three-dimensional (3D), are increasingly used as integrated thermal–mechanical solutions in high-power electronics. However, their complex geometry and material interfaces introduce new reliability concerns, especially at solder joints. This study investigates the evolution of intermetallic compounds (IMCs) in solder joints formed on 3D aluminum IMSs with ENIG metallization, focusing on SAC305 and Sn42Bi57Ag1 solder alloys. Solder joints were subjected to environmental aging under high-temperature, high-humidity, and thermal-shock conditions to simulate realistic service environments. Microstructural and compositional analyses of the interfacial IMC layers were performed, together with measurements of IMC thickness evolution. The results show that aging significantly modifies the chemical composition and morphology of IMC layers in both solder systems. In SAC305 joints, progressive development of (Cu,Ni)₆Sn₅ phases with increasing Cu participation was observed. In Sn42Bi57Ag1 joints, Bi affected reaction kinetics but did not alter the diffusion-controlled nature of IMC growth. Thickness measurements indicate higher sensitivity of SAC305 joints to environment-assisted interfacial degradation, while Sn42Bi57Ag1 joints exhibit greater susceptibility to stress-assisted IMC growth during severe thermal cycling. These findings highlight the distinct reliability behaviors of tested solders on 3D IMSs and provide insight into their suitability for high-power electronic applications. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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22 pages, 1480 KB

Open AccessArticle

Multi-Dimensional Charge Diffusion–Collection Model in Semiconductor Devices Subjected to Single Ionizing Particles

by Alexandre Autran, Daniela Munteanu and Jean-Luc Autran

Appl. Sci. 2026, 16(11), 5551; https://doi.org/10.3390/app16115551 - 2 Jun 2026

Viewed by 284

Abstract

Analytical modeling of charge collection is essential for predicting single-event effects in integrated circuits subjected to radiation. This work proposes a unified model of charge collection by diffusion in semiconductors in one, two, and three dimensions, accounting for recombination effects. We derive exact expressions for the carrier density, diffusion current, and collected charge using the solution of the diffusion equation for a point source. We formulate the collected charge using Bessel functions, which allow for a more general and fully analytical description of the problem. The model emphasizes the role of geometry by explicitly accounting for the dimensionality of the problem. It also establishes that, for any dimension, the collected current peaks before the carrier density does. We also propose analytical expressions for the collection efficiency and the recombination factor, with simplified forms in the absence of recombination. A minimal Python implementation is provided to facilitate the practical application of the model. Finally, we outline how to use the proposed model to perform realistic simulations of single events and relate the results to the soft error rate of a given device. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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14 pages, 1470 KB

Open AccessArticle

Research on Safety Distance Calculation and Altitude Correction Methods for On-Site Withstand Voltage Tests of UHV AC Equipment

by Wenlong Liao, Yueping Yang, Xiaoxu Ma, Yu Tian and Yujian Ding

Appl. Sci. 2026, 16(11), 5547; https://doi.org/10.3390/app16115547 - 2 Jun 2026

Viewed by 297

Abstract

On-site withstand voltage testing is essential for evaluating insulation performance and detecting defects in UHV AC equipment; however, existing safety distance criteria are mainly based on empirical experience or extrapolated from low-altitude and lower-voltage conditions, limiting their applicability. To address this issue, a systematic framework for safety distance calculation and altitude correction is developed. The selection principles and circuit configuration of the test system are analyzed to clarify the constraints between power capacity and tuning under high-voltage, large-capacity conditions. Based on air-gap discharge characteristics, a minimum safety distance model is established for the 1000 kV main transformer with respect to grounded structures and personnel. Meteorological factors and proximity effects are further incorporated to propose correction methods and on-site zoning strategies. Results indicate that a baseline safety distance of approximately 10 m is appropriate at altitudes up to 1000 m, and the model captures the nonlinear degradation of insulation strength in long air gaps at higher altitudes. A case study at 3620 m yields a minimum safety distance of 16.4 m, providing a quantitative basis for safe UHV AC on-site testing under varying altitude conditions. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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14 pages, 917 KB

Open AccessArticle

A Discrete-Time Suboptimal Robust MPC Framework for Systems with Inverse-Proportional Dynamics

by Gisela Pujol-Vázquez, Leonardo Acho and Pablo Buenestado

Appl. Sci. 2026, 16(11), 5520; https://doi.org/10.3390/app16115520 - 2 Jun 2026

Viewed by 282

Abstract

This study presents the development and implementation of a robust model predictive control (MPC) strategy for dynamically inverse-proportional systems. Such systems arise frequently in practical settings, particularly in applications involving electronic sensors, among other domains. However, the existing literature lacks a comprehensive and systematic design framework for robust MPC specifically tailored to this class of systems. To address this gap, we realize an inverse-proportional system by employing a Van der Pol oscillator in conjunction with a low-pass filter stage. For the purpose of robust MPC design, a dynamically inverse-proportional system is modeled as a linear perturbed system characterized by a negative gain in the input channel. This formulation is considered within the discrete-time control framework, where a suboptimal control problem is effectively formulated. Furthermore, the explicit realization of an inverse-proportional system enables a rigorous assessment of controller performance in this setting. The effectiveness of the proposed control scheme is supported through a reproducible numerical experiment, which serves as validation of the approach. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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29 pages, 4468 KB

Open AccessArticle

Reducing LUT Counts in Moore FSMs with Twofold State Assignment

by Alexander Barkalov, Larysa Titarenko and Kazimierz Krzywicki

Appl. Sci. 2026, 16(7), 3540; https://doi.org/10.3390/app16073540 - 4 Apr 2026

Viewed by 376

Abstract

In this paper, we propose a new synthesis method for LUT-based Moore finite state machines (FSMs) with twofold state assignment (TSA). The method introduces an additional core of partial input memory functions (IMFs), resulting in an architecture with two IMF cores. The first core is based on structural decomposition using additional partial state variables, whereas the second uses maximum binary state codes. Both cores are implemented as single-level circuits. We formulate the conditions under which the proposed method can be applied and show that it improves both the area and timing characteristics of the resulting FSM circuits. The method exploits pseudoequivalent state classes to reduce the number of literals in sum-of-products describing partial IMFs. The developed FSM architecture is organized into three logic stages. At the first stage, two dedicated blocks generate partial IMFs. At the next stage, these intermediate functions are merged and used to form the maximum binary state code. The final stage produces both the output signals and the partial state encoding. The proposed method is illustrated by a synthesis example and validated using standard benchmark FSMs. The obtained results indicate that the method is particularly suitable for larger and more complex Moore FSM implementations. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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24 pages, 518 KB

Open AccessArticle

A Secure Authentication Scheme for Hierarchical Federated Learning with Anomaly Detection in IoT-Based Smart Agriculture

by Jihye Choi and Youngho Park

Appl. Sci. 2026, 16(7), 3211; https://doi.org/10.3390/app16073211 - 26 Mar 2026

Viewed by 531

Abstract

Unmanned Aerial Vehicle (UAV)-assisted hierarchical federated learning (HFL) has emerged as a promising architecture for Internet of Things (IoT)-based smart agriculture, which enables scalable model training over large and sparse farmlands. In this setting, UAVs act as mobile edge servers, aggregating local updates from distributed agricultural IoT devices and relaying them to the cloud server. While HFL improves scalability and reduces communication overhead, it still faces critical security threats due to its reliance on public wireless channels and the vulnerability of model aggregation to malicious updates. In this paper, we propose a secure authentication scheme that integrates anomaly detection with elliptic curve cryptography (ECC)-based mutual authentication to protect both the communication and training phases. In the proposed scheme, UAVs authenticate participating clients before receiving their local models, then perform anomaly detection to identify and exclude malicious participants. If a client is found to be malicious, its identity credentials are revoked and broadcast by the cloud server to prevent future participation. The security of the proposed scheme is formally verified using Burrows–Abadi–Needham (BAN) logic, the Real-or-Random (RoR) model, and the Automated Validation of Internet Security Protocols and Applications (AVISPA) tool, along with informal security analysis. The performance evaluation includes comparisons of security features, computation cost, and communication cost with other related schemes, and an experimental assessment of anomaly detection performance. The results demonstrate that our scheme provides strong security guarantees, low overhead, and effective malicious client detection, making it well suited for UAV-assisted HFL in smart agriculture. Full article

(This article belongs to the Special Issue Feature Papers Collection in the Section ‘Electrical, Electronics and Communications Engineering’, Second Edition)

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