Special Issue "Finite State Machines: Theory, Design and Applications"

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: 31 October 2021.

Special Issue Editors

Prof. Larysa Titarenko
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Guest Editor
1. Institute of Metrology, Electronics and Computer Science, University of Zielona Gora, Zielona Gora, Poland
2. Department of Infocommunications, Kharkov National University of Radio Electronics, Kharkiv, Ukraine
Interests: logic synthesis; FSM design; FPGA; ASIC; telecommunications; antenna arrays; hardware–software co-design
Prof. Dr. Alexander Barkalov
Website
Guest Editor
1. Institute of Metrology, Electronics and Computer Science, University of Zielona Gora, Zielona Gora, Poland
2. Chair of Applied Mathematics and Theory of Control Systems, Vasyl’ Stus Donetsk National University, Vinnytsia, Ukraine
Interests: logic synthesis; strucrural decomposition; state assignment; FSM design; FPGA; ASIC; CPLD; embedded systems

Special Issue Information

Dear Colleagues,

The model of finite state machine (FSM) has been used for about 70 years in order to specify and design logic circuits of sequential blocks of different digital systems. Basic characteristics of digital systems always strongly depend on the quality of FSM-based blocks. Currently, we are witnessing the rapid development of semiconductor technology. As a result of the transition from microelectronics to nanoelectronics, new families of microchips have appeared. Now, it is enough for a single chip to implement very complex digital and mixed digital–analogue systems. This phenomenon has led to the emergence and development of various mobile and autonomous systems. In turn, this helps to implement different systems for smart homes, smart cities, Internet-of-Things, and a lot of systems we do not know about right now. So, FSMs are now only small parts of the systems hidden inside these chips. However, FSM designers face all of the same challenges, namely: it is necessary to implement an FSM circuit with the smallest possible hardware amount, propagation time, and consumed energy. All of these challenges must be met in a new and rapidly changing environment. The ever-increasing complexity of modern and future industrial projects requires the development of efficient computer-aided design tools for implementing complex FSM circuits. Also, it is necessary to develop a unified library of benchmark FSMs to compare the outcomes of different design methods. 

 The aim of this Special Issue is to accumulate scientific manuscripts on the practical and theoretical aspects associated with the design of FSM circuits and the application of FSM-based blocks in modern digital and cyber–physical systems. The key focus is to present theoretical advances, as well as new design and verification methods in order to improve the quality of FSM circuits as elements of modern complex systems. Topics may include, but are not limited to, the following: 

Topics may include, but are not limited, the following:

  • Development of theory of finite state machines
  • Development of methods of state assignment targeting improving basic characteristics of FSM circuits (chip area, performance, and consumed energy)
  • Improving the specification of FSMs targeting real-scale projects
  • Design of energy-efficient FSMs
  • Development of hardware-dependent design methods targeting FSMs implemented with FPGAs, ASICs, and CPLDs
  • Development of design methods for asynchronous FSMs
  • Development of hardware-dependent and hardware-independent computer-aided design tools targeting FSMs
  • Development of design methods for parallel FSMs and networks of FSMs
  • Development of design methods for hierarchical FSMs
  • Development of FSM design methods targeting cyber–physical systems
  • Development of methods of functional and structural decomposition of FSM logic circuits targeting the process of technology mapping
  • Improving testability of complex FSMs
  • Development of advanced methods of verification of FSM circuits
  • Application of FSM-based devices in telecommunications, Internet-of-Things, and mobile and autonomous systems
  • Development of a library of benchmark FSMs to compare different design methods 
Prof. Larysa Titarenko
Prof. Alexander Barkalov
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • finite state machine
  • specification
  • synthesis
  • decomposition
  • technology mapping
  • testability
  • verification
  • FPGA
  • ASIC
  • CPLD
  • system-on-a-programmable chip
  • computer-aided design
  • benchmark FSMs

Published Papers (2 papers)

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Research

Open AccessArticle
Reducing LUT Count for FPGA-Based Mealy FSMs
Appl. Sci. 2020, 10(15), 5115; https://doi.org/10.3390/app10155115 - 25 Jul 2020
Cited by 1
Abstract
Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper [...] Read more.
Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method optimizing LUT counts of LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the replacement of FSM inputs and encoding of the collections of outputs. The proposed method results in three-level logic circuits of Mealy FSMs. These circuits have regular systems of interconnections. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). This gain is accompanied by a small loss of FSM performance. Full article
(This article belongs to the Special Issue Finite State Machines: Theory, Design and Applications)
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Open AccessArticle
Technology Mapping of FSM Oriented to LUT-Based FPGA
Appl. Sci. 2020, 10(11), 3926; https://doi.org/10.3390/app10113926 - 05 Jun 2020
Abstract
The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped [...] Read more.
The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output function. The proposed idea makes it possible to conduct decomposition that may enable to share logic blocks, which can lead to the reduction of using resources of FPGA. The decomposition process was conducted using the analyzed DECOMP system. The effectiveness of the proposed idea of the FSM description was also confirmed by conducting decomposition with the usage of the ABC system. The obtained results prove the efficiency of the proposed synthesis method of FSM in comparison with the separate synthesis of a transition block and an output block. Full article
(This article belongs to the Special Issue Finite State Machines: Theory, Design and Applications)
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