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Algorithms
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Algorithms in Reconfigurable Computing
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Algorithms in Reconfigurable Computing

A special issue of Algorithms (ISSN 1999-4893). This special issue belongs to the section "Algorithms for Multidisciplinary Applications".

Deadline for manuscript submissions: closed (15 March 2023) | Viewed by 11852

Special Issue Editors

Prof. Dr. Mário Véstias

E-Mail Website
Guest Editor
Department of Electronics, Telecommunications and Computer Engineering, Polytechnic of Lisbon, 1500-310 Lisboa, Portugal
Interests: reconfigurable computing; embedded high-performance computing; reconfigurable architectures for deep learning; computer arithmetic
Special Issues, Collections and Topics in MDPI journals
Dr. Paulo Flores

E-Mail Website
Guest Editor
INESC-ID, Instituto Superior Técnico (ECE Department), University of Lisbon, Lisbon, Portugal
Interests: embedded systems architectures; dedicated and reconfigurable computation (FPGAs); design and optimization of models and algorithms applied to electronic design automation (EDA) problems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Reconfigurable Computing has emerged as a low cost, high-performance computing platform able to execute algorithms in many application domains faster than other computing platforms, like CPU-based systems. Its reconfigurability allows the design and implementation of circuits following the most appropriate computing paradigm for a particular algorithm. This flexibility and the need for hardware design brings two main challenges to the design of algorithms in reconfigurable computing: algorithmic development for hardware and hardware design of algorithms. Algorithms are usually described sequentially, while hardware is parallel by nature. Adaptation of algorithms for parallel execution is an important high-level step. Then, mapping software descriptions into hardware is still a hot research topic with new achievements in high-level synthesis.

This Special Issue aims to collect recent innovations to deploy algorithms in reconfigurable computing. Potential topics include, but are not limited to:

  • Mapping algorithms in FPGA with high-level synthesis;
  • Template-based reconfigurable architectures for particular domains of algorithms;
  • FPGA accelerators for algorithms;
  • Algorithm optimization with arbitrary-precision data types;
  • Algorithms in coarse-grained reconfigurable architectures;
  • Design methodologies to map algorithms on reconfigurable computing devices;
  • Design of data-centric algorithms with reconfigurable computing;
  • Reconfigurable embedded devices for algorithms applied to health, smart-home, etc;
  • Design of algorithms in high-performance reconfigurable computing platforms;
  • Designing algorithms in SoC (System-on-Chip) FPGAs;
  • Case studies of algorithm design with reconfigurable computing.

Prof. Dr. Mário Véstias
Prof. Dr. Paulo Flores
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Algorithms is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Algorithms in hardware
  • Algorithm acceleration
  • Algorithms in reconfigurable computing
  • Reconfigurable computing
  • Field-Programmable Gate Array
  • Coarse-grain reconfigurable architecture
  • FPGA accelerators
  • High-performance computing with FPGA
  • High-level synthesis.

Published Papers (4 papers)

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Research

27 pages, 582 KiB  
Article
Linear Computation Coding: A Framework for Joint Quantization and Computing
by Ralf Reiner Müller, Bernhard Martin Wilhelm Gäde and Ali Bereyhi
Algorithms 2022, 15(7), 253; https://doi.org/10.3390/a15070253 - 20 Jul 2022
Cited by 5 | Viewed by 2027
Abstract
Here we introduce the new concept of computation coding. Similar to how rate-distortion theory is concerned with the lossy compression of data, computation coding deals with the lossy computation of functions. Particularizing to linear functions, we present an algorithmic approach to reduce the [...] Read more.
Here we introduce the new concept of computation coding. Similar to how rate-distortion theory is concerned with the lossy compression of data, computation coding deals with the lossy computation of functions. Particularizing to linear functions, we present an algorithmic approach to reduce the computational cost of multiplying a constant matrix with a variable vector, which requires neither a matrix nor vector having any particular structure or statistical properties. The algorithm decomposes the constant matrix into the product of codebook and wiring matrices whose entries are either zero or signed integer powers of two. For a typical application like the implementation of a deep neural network, the proposed algorithm reduces the number of required addition units several times. To achieve the accuracy of 16-bit signed integer arithmetic for 4k-vectors, no multipliers and only 1.5 adders per matrix entry are needed. Full article
(This article belongs to the Special Issue Algorithms in Reconfigurable Computing)
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13 pages, 18548 KiB  
Article
Algorithmic Design of an FPGA-Based Calculator for Fast Evaluation of Tsunami Wave Danger
by Mikhail Lavrentiev, Konstantin Lysakov, Andrey Marchuk, Konstantin Oblaukhov and Mikhail Shadrin
Algorithms 2021, 14(12), 343; https://doi.org/10.3390/a14120343 - 26 Nov 2021
Cited by 3 | Viewed by 2295
Abstract
Events of a seismic nature followed by catastrophic floods caused by tsunami waves (the incidence of which has increased in recent decades) have an important impact on the populations of littoral regions. On the coast of Japan and Kamchatka, it takes nearly 20 [...] Read more.
Events of a seismic nature followed by catastrophic floods caused by tsunami waves (the incidence of which has increased in recent decades) have an important impact on the populations of littoral regions. On the coast of Japan and Kamchatka, it takes nearly 20 min for tsunami waves to approach the nearest dry land after an offshore seismic event. This paper addresses an important question of fast simulation of tsunami wave propagation by mapping the algorithms in use in field-programmable gate arrays (FPGAs) with the help of high-level synthesis (HLS). Wave propagation is described by the shallow water system, and for numerical treatment the MacCormack scheme is used. The MacCormack algorithm is a direct difference scheme at a three-point stencil of a “cross” type; it happens to be appropriate for FPGA-based parallel implementation. A specialized calculator was designed. The developed software was tested for precision and performance. Numerical tests computing wave fronts show very good agreement with the available exact solutions (for two particular cases of the sea bed topography) and with the reference code. As the result, it takes just 17.06 s to simulate 1600 s (3200 time steps) of the wave propagation using a 3000 × 3200 computation grid with a VC709 board. The step length of the computational grid was chosen to display the simulation results in sufficient detail along the coastline. At the same time, the size of data arrays should provide their free placement in the memory of FPGA chips. The rather high performance achieved shows that tsunami danger could be correctly evaluated in a few minutes after seismic events. Full article
(This article belongs to the Special Issue Algorithms in Reconfigurable Computing)
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20 pages, 1903 KiB  
Article
Design of an FPGA Hardware Optimizing the Performance and Power Consumption of a Plenoptic Camera Depth Estimation Algorithm
by Faraz Bhatti and Thomas Greiner
Algorithms 2021, 14(7), 215; https://doi.org/10.3390/a14070215 - 15 Jul 2021
Cited by 1 | Viewed by 2333
Abstract
Plenoptic camera based system captures the light-field that can be exploited to estimate the 3D depth of the scene. This process generally consists of a significant number of recurrent operations, and thus requires high computation power. General purpose processor based system, due to [...] Read more.
Plenoptic camera based system captures the light-field that can be exploited to estimate the 3D depth of the scene. This process generally consists of a significant number of recurrent operations, and thus requires high computation power. General purpose processor based system, due to its sequential architecture, consequently results in the problem of large execution time. A desktop graphics processing unit (GPU) can be employed to resolve this problem. However, it is an expensive solution with respect to power consumption and therefore cannot be used in mobile applications with low energy requirements. In this paper, we propose a modified plenoptic depth estimation algorithm that works on a single frame recorded by the camera and respective FPGA based hardware design. For this purpose, the algorithm is modified for parallelization and pipelining. In combination with efficient memory access, the results show good performance and lower power consumption compared to other systems. Full article
(This article belongs to the Special Issue Algorithms in Reconfigurable Computing)
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17 pages, 4997 KiB  
Article
Decision Tree-Based Adaptive Reconfigurable Cache Scheme
by Wei Zhu and Xiaoyang Zeng
Algorithms 2021, 14(6), 176; https://doi.org/10.3390/a14060176 - 01 Jun 2021
Cited by 5 | Viewed by 3059
Abstract
Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can [...] Read more.
Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms. Full article
(This article belongs to the Special Issue Algorithms in Reconfigurable Computing)
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