A Two-Step Method for Diode Package Characterization Based on Small-Signal Behavior Analysis

Abstract

This article presents a comprehensive and intuitive analysis of the impact of packaging on diode performance and a two-step method for packaging parameter extraction. This is performed using a single forward bias point, one-port measurements and probe tips on a conventional printed circuit board (PCB). A PIN diode was used to validate the method, biased from reverse (−5 V) to forward (1.22 V) bias. Measurements were performed up to 27 gigahertz (GHz). The complete diode characterization process—from the design and the electrical modeling of the test fixture to the extraction of the unpackaged diode measurements—is detailed. The parameters of the package model were extracted, its effects were removed from the measurement, and the behavior of the unpackaged diode was determined. Three operating regions based on their radiofrequency and direct current (RF-DC) behavior were proposed, and an electrical model of the unpackaged diode was derived for each region. The results showed that the influence of the package caused the diode to remain in an unchanged behavior under different biases, indicating that it no longer rectified. The results presented herein are validated by the excellent correlation between the diode’s measured S-parameters, impedance, and admittance and their corresponding models.

1. Introduction

The study of high-frequency devices [1,2,3] has become more relevant in recent years due to the evolution of wireless electronics. Special attention has been given to the study of packaged devices, mainly because package effects that are negligible at low frequencies become significant as the frequency increases and, therefore, must be considered and properly modeled. Among these devices, the diode has attracted special attention, since the parasitic effects introduced by the package can significantly impact its performance when used as a rectifier [1,2,3,4,5,6,7].

The electrical model of a packaged diode can be divided into intrinsic and extrinsic parts. A schematic representation (not to scale) of the cross-sectional view of a packaged diode and its electrical model is presented in Figure 1a and Figure 1b, respectively. The intrinsic part is the device’s innermost aspect, and depends on the biasing conditions (shown in a small green circle in Figure 1a,b). The extrinsic part is independent of the bias, and it interfaces with the external environment and the intrinsic part of the diode. It typically consists of internal connections (shown in the red box, excluding the green circle, in Figure 1a,b) and a dielectric box with external contact pads (shown in the blue box, excluding the red box, in Figure 1a,b). Typically, diode packaging models account for both the internal interconnections and the external contact pads. The electrical model includes inductances $L_{p1}$ and $L_{p2}$ associated with the external metallic contact pads; the pad-to-pad capacitances ($C_{pp1}$ and $C_{pp2}$); the inductance $L_f$ associated with the internal connections; the capacitance between the internal connections and the pad ($C_{fp}$); and the series resistance ($R_s$). The capacitances $C_{pp1}$ and $C_{pp2}$ model the electrical coupling between the pads over the air and through the substrate, respectively, and are grouped into a single capacitance $C_{pp}$ (which modeled in Figure 1b). Throughout this work, the intrinsic part of the diode is referred to as the unpackaged diode, the extrinsic part as the diode package/packaging, and the complete device (intrinsic + extrinsic) as the packaged diode. The electrical model of the diode’s packaging has been discussed [8,9,10,11,12], yet the influence of packaging on the diode’s performance is still not fully clear.

Figure 1. (a) Schematic representation of the cross-sectional view of a packaged diode and (b) its electrical model. The size of the intrinsic part is about 10 µm, the internal connections are approximately 100 µm, and the packaging box is larger than 500 µm.

Large-signal [7,13] and small-signal [1,2,8,10,11] approaches can be used for modeling and extraction of the diode parameters. The large-signal approach uses voltage and current waveforms to model the diode. In [13], the diode is modeled from S-parameter measurements to extract the extrinsic elements, modeled as lumped components. Meanwhile, the intrinsic part is derived from the current and voltage waveform measurements, in order to obtain equations for internal current sources that model the resistive and capacitive components. In [7], the SPICE model of the diode is derived from I-V and C-V curves, while the extraction of the linear parasitic parameters is performed through S-parameter measurements. The verification of the method is performed through voltage waveforms. Although the methods demonstrate high accuracy ([13], with approximately 10% error), they require both small-signal and large-signal measurements to obtain the full diode model.

The small-signal approach extracts those parasitic elements which are not bias-dependent, using S-parameters from a device (bias-dependent) by polarizing the device at a specific bias. It has previously been applied to transistors [14,15]. In [14], the parameters of the transistor are extracted under the cold condition (V_gs = 0, V_ds = 0), based on linear regressions. In [15], the parameters are determined from measurements under the cold condition along with optimization from the hot condition for greater accuracy. Regarding diodes, in [1,2], the extraction of the parameters is performed from a resonance observed in the S-parameters, with 2-port measurement. However, no analysis is presented regarding the significance of this resonance or its impact on the packaging. In [8,10], the impact of the internal diode connections is analyzed, showing their influence in the terahertz range. In [11], the focus has been on modeling the diode as a noise source.

When a commercial packaged diode is acquired from a manufacturer, only the packaged device is available, meaning that measurements are performed on a single structure [2,5,6], and its parameters are obtained by curve fitting. In [2], diode packaging is modeled using a single inductor and a capacitor. In [5], only the total packaging capacitance is extracted from the measurements, while the remaining parameters are optimized by fitting the measured S-parameters. In [6], a numerical optimization method is applied to determine the parameters by curve fitting. Furthermore, the information provided by the manufacturer often includes limited data, which is tested under highly constrained conditions. For instance, if radiofrequency (RF) measurements are performed, the frequency range is typically limited to a few gigahertz (GHz), making it difficult to extrapolate the data to higher frequencies. Rarely is the electrical model of the packaging provided.

Despite all these diode modeling works, none provide an explanation of the individual and combined behaviors of the diode’s intrinsic part and packaging, which is critical to accurately assessing the impact of packaging. However, the analysis requires measurements that intuitively and clearly help in identifying the intrinsic and overall behavior of the diode. The common approach for characterizing diodes is based on two-port measurements [1,2,5,6,7,8]. In such studies, the diode is modeled and compared against its measured S-parameters or its representation on a Smith Chart. Although models and measurements show good agreement, the way measurements and results are presented does not allow clear identification of the intrinsic part response, the packaging response, or the impact of packaging on overall diode performance. Therefore, a clear explanation of both the packaging and the intrinsic diode behavior is essential, with an emphasis on analyzing the packaging’s contribution to the device performance. Furthermore, proposing a practical and straightforward method for parameter extraction from this analysis is required.

This paper presents a contribution to the state-of-the-art by proposing an analysis of the diode’s small-signal behavior across crucial bias points, as well as a two-step parameter extraction method derived from this analysis. The analysis enables differentiation between the contributions of the diode’s intrinsic part and its packaging. To perform the analysis, this work presents measurements using a single port with RF probes on a printed circuit board (PCB). The complete diode characterization process—from the design and the electrical modeling of the test fixture to the extraction of the intrinsic diode model parameters—is detailed. The measurement setup facilitates an intuitive evaluation of the packaging’s impact on the diode’s performance in terms of S-parameters and impedance. The results show that the packaging effect is independent of the bias; consequently, the influence of the package causes the diode to maintain unchanged behavior under different biases, indicating the diode has stopped exhibiting rectifying behavior. The results also illustrate that, in a diode with well-designed packaging, the packaging does not significantly affect the diode’s performance. Conversely, a poorly designed package can substantially degrade the device’s overall behavior.

The rest of the paper is organized as follows. Section 2 details the experimental setup, the design of the de-embedding structures, the diode behavior analysis and the parameter extraction method, while Section 3 shows the extraction of diode package parameters and the results of modeling both the unpackaged and packaged diode. Section 4 discusses the results and addresses key considerations regarding diode measurement. Finally, Section 5 provides the conclusions derived from this work. Appendix A and Appendix B present the electrical models of the de-embedding structures and the unpackaged diode, respectively.

2. Materials and Methods

2.1. Materials

Figure 2a, Figure 2b, Figure 2c and Figure 2d show the measurement setup, and top views of the open structure, the short structure, and the diode soldered onto the test structure, respectively. The measured diode was a PIN diode, CLA4608-085LF. The de-embedding structures were designed using Ansys High-Frequency Structure Simulator (HFSS), while their electrical models were implemented in Advanced Design System (ADS). The structures were fabricated on a Rogers RO3010 substrate with a dielectric permittivity of 10.2, a loss tangent of 0.0022, and thickness of 1.28 mm. The substrate is clad with electrodeposited copper foil of 1/2 oz (18 μm) with roughness of 0.4 μm on the outer surface and 2.0 μm on the dielectric-contacting surface. The structures were fabricated using an LPKF ProtoLaser S4 in collaboration with the PCB prototyping laboratory at CIATEQ Guadalajara. Measurements were performed with an Agilent E8361A PNA Network Analyzer (Agilent Technologies, Santa Clara, CA, USA) and 150 μm Picoprobe RF probes (FormFactor, Inc., Livermore, CA, USA). The test structures were fabricated, and the diode was soldered onto an open structure. Measurements were performed on both the structures and the diode.

Figure 2. (a) RF device measurement station, and top views of (b) the open structure, (c) the short structure, and (d) the open structure with the diode soldered on it.

To measure the diode using Ground-Signal-Ground (GSG) probe tips, coplanar waveguide (CPW) open and short structures were designed and manufactured. The dimensions that define the impedance of the CPW structure are the width of the central conductor, the gap between the central conductor and the lateral ground planes, and the dielectric height. Using the equations presented in [16] and optimizing by simulation, the open structure (Figure 3a) was designed to maintain a 50 ohm impedance from the beginning of the structure (the probe contact point) to the point where the anode of the diode is connected. Beyond this point, the ground planes were extended and merged, forming the contact for the cathode of the diode. The short structure was implemented by adding a narrow strip that connected the signal line to the ground planes. Figure 3b shows the short structure and its dimensions, while Figure 3c shows the way the diode is connected. An electrical model was proposed for these structures; detailed information is presented in Appendix A.

Figure 3. Top view of the de-embedding structures: (a) open—showing the placement of the RF probe tips; (b) short—showing the dimensions of the structure; and (c) a diode mounted on the open structure.

2.2. Analysis of the Diode’s Small-Signal Behavior Across Crucial Bias Points

Figure 4a–c illustrate the diode’s current vs. voltage (I–V) characteristic curve, the one-port measurement configuration, and the S₁₁ parameters obtained from measurements at three different bias points. Under reverse bias, the diode ideally behaves as an open circuit, while under forward bias, it behaves as an ideal short circuit. At an intermediate bias point, the diode exhibits an impedance close to that of the measurement port (50 Ω). Figure 4a illustrates the position of these operating points on the diode’s I–V characteristic curve. The measured S₁₁ parameter at the three bias conditions using a single-port setup (Figure 4b) are presented in Figure 4c.

Figure 4. (a) I–V characteristic curve of the diode, (b) single-port measurement configuration, and (c) diode S₁₁ parameters at different bias points (green line: open-circuit condition; black line: short-circuit condition; blue dashed line: impedance close to 50 Ω).

As expected, when the diode behaves as either a short or an open circuit, nearly all the incident energy is reflected to the port, resulting in S₁₁ values close to 0 decibels (dB). Conversely, when the diode’s impedance approaches that of the port, most of the energy is transferred to the diode rather than reflected, leading to a decrease in the S₁₁ parameter, which drops below −10 dB. The variation in the diode’s behavior across different bias points confirms its rectifying operation.

If the S-parameter response remains unchanged with bias, the diode is no longer rectifying. The diode exhibits bias-dependent behavior up to approximately 10 GHz (the manufacturer specifies an operating range up to 6 GHz); however, above 20 GHz, rectification completely ceases; the three lines in the graph exhibit almost the same behavior.

The real and imaginary components of the impedance are shown in Figure 5a,b. The real part of the impedance is different from 50 Ω for the diode operating under open and short-circuit conditions. Conversely, when the diode bias brings its impedance closer to that of the measurement port, the real part of impedance approaches 50 Ω. As observed from the S₁₁ response (Figure 4c) the diode’s behavior at the three bias points becomes practically the same beyond 20 GHz, with a pronounced peak in the real part of the impedance. Since the behavior no longer varies with bias, the diode has stopped rectifying. In the imaginary part, a resonance is observed for all bias conditions above 20 GHz. The peak in the real part of the impedance and the resonance in the imaginary part are parasitic effects of the diode’s packaging, which causes the diode to exhibit a similar behavior across all bias points. The slight shift in the peak and resonance frequencies at the bias points is due to the influence of the diode’s intrinsic region. Although it could be inferred that this effect limits the diode’s rectification frequency, it will be true for some cases, but a more detailed analysis is required to fully confirm this.

Figure 5. (a) Real part and (b) imaginary part of the diode impedance at the three bias conditions. The green line indicates the open-circuit condition, the black line represents the short-circuit condition, and the blue dashed line corresponds to an impedance approximately equal to 50 Ω.

The resonance can be modeled, its electrical parameters obtained, and its influence can be removed from the measured data to isolate the unpackaged diode behavior, allowing a detailed analysis of the impact of a poorly designed package—where the dominant packaging effect occurs below the intrinsic operating frequency—as presented in the Section 4.

2.3. The Two-Step Parameter Extraction Method

The electrical models shown in Figure 6a,b were used as the basis for parameter extraction. The model’s accuracy is validated in the Section 3, while the analysis of the model is presented in the Section 4. Ideally, the intrinsic part of the diode behaves as an open circuit under reverse bias and as a short circuit under forward bias; therefore, the circuit in Figure 6a can be approximated by the diode model in Figure 6b for forward bias. The diode in short-circuit at forward bias (DSFB) is a bias point in which the diode behaves as a short circuit under forward bias, and it can be selected at a voltage higher than the knee voltage, making sure the device can withstand the potential difference without being damaged. This value can be determined either by the manufacturer or from laboratory measurements.

Figure 6. Electrical model of the diode used in this work, (a) with intrinsic part (The intrinsic diode region is represented as Int box.) and (b) approximation on forward bias.

The model for the diode’s package is derived through a two-step process by measuring S-parameters at the DSFB point and converting them to impedance ($Z_{DSFB}$) and admittance ($Y_{DSFB}$). Under forward bias, $C_{pp}$, $L_p$, and $L_f$ are determined from the diode’s $Im\left(Z_{DSFB}\right)$ (Step 1), while $R_s$ is extracted from its $Re\left(Y_{DSFB}\right)$ (Step 2).

2.3.1. Step 1, Obtaining $C_{pp}$, $L_p$, and $L_f$

Figure 6b illustrates the diode model in forward bias. The impedance behavior of the diode in forward bias ($Z_{DSFB}$) as a function of frequency is given by

$$Z_{DSFB}={\displaystyle \frac{\left(Rs+j\mathsf{\omega }{L}_f\right)\cdot \frac{1}{j\mathsf{\omega }{C}_{pp}}}{\left(Rs+j\mathsf{\omega }{L}_f\right)+\frac{1}{j\mathsf{\omega }{C}_{pp}}}}+j\mathsf{\omega }{L}_p$$

(1)

where $L_p$ corresponds to the sum of $L_{p1}$ and $L_{p2}$, since $L_{p1}$ and $L_{p2}$ are connected in series. The imaginary part of the equation can be written as

$$Im(Z_{DSFB})={\displaystyle \frac{-\frac{L_f}{C_{pp}}\left(\omega L_f-\frac{1}{\omega C_{pp}}\right)-\frac{R_s^2}{\omega C_{pp}}}{R_s^2+{\left(\omega L_f-\frac{1}{\omega C_{pp}}\right)}^2}}+\mathsf{\omega }{L}_p$$

(2)

From (2), it can be observed that $R_s$ has a significant impact at the resonance frequency, diminishing as the frequency deviates from resonance. Furthermore, the resonance frequency is solely determined by the contribution of $L_f$ and $C_p$, and it is independent of $R_s$. $Im\left(Z_{DSFB}\right)$ can be approximated by neglecting $R_s$ in Equation (2) to:

$$jIm(Z_{DSFB})\approx j\mathsf{\omega }{L}_f||{\displaystyle \frac{1}{j\mathsf{\omega }{C}_{pp}}}+j\mathsf{\omega }{L}_p$$

(3)

The diode reactance $Im\left(Z_{DSFB}\right)$ can be an be rewritten by dividing both terms by $\mathsf{\omega }$:

$${\displaystyle \frac{Im\left(Z_{DSFB}\right)}{\mathsf{\omega }}}={\displaystyle \frac{1}{\frac{1}{L_f}-{\mathsf{\omega }}^2{C}_{pp}}}+L_p$$

(4)

From (4), an equation with three variables is obtained. By selecting three different frequencies, a system of three equations with three variables is obtained.

The lowest frequency value is selected so that ${\mathsf{\omega }}^2{C}_{pp}$ ≪ ${1/L}_f$, allowing the approximation ${\mathsf{\omega }}^2{C}_{pp}\approx 0$, resulting in:

$${\displaystyle \frac{Im\left(Z_{DSFB}\right)}{\omega }}\approx L_f+L_p$$

(5)

The highest frequency value is selected at the maximum impedance point (the resonance frequency), which occurs when ${1/L}_f-{\omega }^2{C}_{pp}= 0$:

$${\mathsf{\omega }}_0={\displaystyle \frac{1}{\sqrt{L_f{C}_{pp}}}}$$

(6)

The intermediate frequency is selected at a point between the lowest and highest frequency and is evaluated using (4).

2.3.2. Obtaining $R_s$

As in [10], $R_s$ is obtained from $Real\left(Y_{DSFB}\right)$ in forward bias when $\mathsf{\omega }$ → 0

$$R_s\approx {\displaystyle \frac{1}{Real\left(Y_{DSFB}\right)}}$$

(7)

3. Results

Measurements of the diode were performed from reverse bias (−5 V) to forward bias (1.22 V). Parameter extraction was performed at 1.22 V, which is considered the DSFB point. This value was selected based on manufacturer data and laboratory measurements. The manufacturer specifies that the diode can withstand 100 mA. Laboratory measurements showed that this current was reached at a bias of 1.22 V. Figure 7 shows the experimental I–V curve of the diode.

Figure 7. Measured I–V curve of the diode showing the conduction regions determined by its RF behavior, as proposed in this work. Blue solid line in linear scale (left axis) and blue dashed line in logarithmic scale (right axis). In the logarithmic scale for negative currents (when V < 0), the absolute value is used for plotting. In the non-conduction region, the diode behaves as an open circuit; in the full-conduction region, the diode acts as a short circuit; in the semi-conduction region, the diode’s impedance nears the measurement port impedance (50 ohms).

Diode Packaging Parameter Extraction

The method proposed in Section 2 was implemented to model the diode’s package. The diode was biased at 1.22 V, and the parameters were determined from the graph in Figure 8. The extraction used point A for (5), point B for (4), and point C for (6), making a system of three equations with three unknowns (extraction A-B-C).

Figure 8. $Im\left(Z_{DSFB}\right)/\omega$ of the diode measurement (at 1.22 V). Points A, B, and C are used for parameter extraction (extraction A-B-C). Point D (red line) is used for further analysis of the method (extraction A-B-D).

To demonstrate the impact of using Equation (6) without reaching the resonance frequency, a second extraction was carried out. The second extraction used point A for (5) and points B and D for (4) at two different frequencies as two different equations, setting another system of three equations with three unknowns (extraction A-B-D).

The extracted parameters are presented in Table 1. The imaginary part of the impedance, obtained from measurements at DSFB, along with the electrical model from Figure 6b using the values obtained from both parameter extractions (A-B-C and A-B-D), is shown in Figure 9.

Table 1. Values obtained from the resonant extraction.

Parameters	Extraction A-B-C	Extraction A-B-D	Units
$C_{pp}$	0.162	0.178	pF
$L_p$	0.167	0.190	nH
$L_f$	0.252	0.229	nH
$R_s$	0.542	0.542	Ohm

Figure 9. $Im\left(Z_{DSFB}\right)$ from diode measurements (at 1.22 V) and the model shown in Figure 2b with extraction A-B-C and A-B-D.

As expected, the A-B-C extraction shows good correlation in $Im\left(Z_{DSFB}\right)$ (Figure 9) at frequencies below and above the resonance frequency. To further explore the method, the A-B-D extraction is implemented, showing a good correlation even at frequencies below the resonance. This indicates that the method can still be effectively applied when the test frequency is below resonance, yielding reliable results.

Packaged Diode vs. Unpakaged Diode

Removing the parasitic elements of the diode package was performed as in [6] and is shown in Figure 10, thus obtaining the unpackaged diode. Since it is a PIN diode, the intrinsic part can be represented by up to four electrical models [17,18,19,20], each corresponding to different bias regions of the diode.

Figure 10. Removal of packaging parasitic effects from the diode measurements to isolate the unpackaged diode [6].

Whereas other works use direct current (DC)-measured I–V curves as a reference to determine the diode’s operating regions, in this article, the operating regions are determined by its RF behavior. The operating regions are defined as follows: In the non-conduction region, the diode operates as an open circuit. The impedance across frequency will be higher compared to the port impedance, dominated by a large imaginary part. The corresponding DC values for this behavior range from −5 V to 0.3 V. In the semi-conduction region, the diode operates as a load matched to the port. The impedance across frequency will be close to the port impedance, dominated by a real part close to 50 ohms. The corresponding DC values for this behavior range from 0.4 V to 0.6 V. In the full-conduction region, the diode operates as a short circuit. The impedance across frequency will be close to zero (both real and imaginary parts). The corresponding DC values for this behavior range from 0.7 V to 1.22 V. The corresponding frequency range for the three regions extends up to 6–10 GHz. Figure 7 shows the diode’s operating regions, determined by its RF behavior but illustrated on the diode’s I–V curve. The models of the unpackaged diode for the different operating regions are presented in Appendix B.

The S₁₁ for the three operating regions of the unpackaged diode, obtained from both the model and measurements, are presented in Figure 11. Figure 11a corresponds to the bias values ranging from −5 V to 0.3 V, Figure 11b corresponds to the bias values between 0.4 V and 0.6 V and Figure 11c corresponds to the bias values from 0.7 V to 1.22 V. Good agreement between the measured data and the model is observed.

Figure 11. S₁₁ parameters of the (a) non-conducting, (b) semi-conducting and (c) full-conducting regions of the unpackaged diode.

After modeling the unpackaged diode, the package elements are added to complete the full diode model (packaged diode).

The S₁₁ for the three operating regions of the packaged diode, obtained from both the model and measurements, is presented in Figure 12. Figure 12a corresponds to the bias values ranging from −5 V to 0.3 V, Figure 12b corresponds to the bias values between 0.4 V and 0.6 V and Figure 12c corresponds to the bias values from 0.7 V to 1.22 V. Good agreement between the measured data and the model is observed.

Figure 12. S₁₁ parameters of the (a) non-conducting, (b) semi-conducting and (c) conducting regions of the packaged diode model.

4. Discussion

4.1. Analysis of the Effect of Packaging Parasitic Elements on Diode Performance

Figure 13 shows the diode behavior in terms of S-parameters (Figure 13a), the imaginary part of the impedance (Figure 13b), and the real part of the impedance (Figure 13c), at a bias of 0.5 V, under five conditions: the intrinsic diode (solid blue line); the packaged diode with the values extracted in Section 3 (dashed blue line, labeled as nominal); and the packaged diode with modified values of $L_f$, at 6 nH (dashed brown line), $L_p$ at 1 nH (dashed purple line), and $C_{pp}$ at 0.8 pF (dashed red line). 0.5 V bias is selected, as it enables a more intuitive interpretation of the diode’s behavior on S parameters. The first objective of the analysis is to compare the behavior of the intrinsic diode with that of the packaged diode (i.e., the intrinsic diode plus the packaging parasitics) and to understand why removing the parasitic elements does not result in a significant change in the S-parameters. The second objective is to evaluate the individual effect of each of the three packaging parasitic elements ($L_f$, $L_p$, and $C_{pp}$) by varying them separately to observe their impact on diode performance. Finally, the effect of $C_{pp}$ is analyzed in detail by evaluating its impact at 0.5 V, −5 V (diode off), and 1.22 V (diode conducting) to assess its influence across the diode’s three operating regions.

Figure 13. (a) S-parameters and (b) imaginary and (c) real part of the impedance of the diode at 0.5 V bias, on five different conditions: Intrinsic diode, nominal packaged diode, $L_f$, modified to 6 nH, $L_p$ modified to 1 nH and $C_{pp}$ modified to 0.8 pF.

4.1.1. Comparison Between Unpackaged and Packaged Diode

The S-parameter behavior of the intrinsic diode shown in Figure 13a, at frequencies below 6 GHz, exhibits good impedance matching to the port (with values below −10 dB). As frequency increases, the diode becomes mismatched, reaching values close to 0 dB. The packaged diode shows no significant change compared to the intrinsic diode in S parameters. The difference becomes evident when analyzing the impedance.

The real part of the intrinsic diode’s impedance (Figure 13c) stays close to 50 Ω below 6 GHz and decreases as frequency increases. In an ideal diode, the real part of the impedance would remain constant across frequency. In practice, however, the real part of the impedance decreases with increasing frequency. This behavior may result from design characteristics, material limitations, fabrication imperfections or junction capacitance. The imaginary part follows a straight line with a slight slope. The packaged diode shows similar behavior below 6 GHz; however, at 25.8 GHz, a resonance appears in the imaginary part (Figure 13b), along with a peak in the real part (Figure 13c). Both effects are centered at 25.8 GHz and are caused by the packaging parasitics.

From this analysis, it is determined that the diode behavior below 6 GHz is dominated by its intrinsic part, while at higher frequencies, it is dominated by the packaging. For the specific scenario analyzed, the packaging effects do not meaningfully impact the diode’s rectification performance, since the maximum operating frequency of the intrinsic part is lower than the frequency at which the packaging exhibits its dominant influence. This agrees with the information provided in the manufacturer’s datasheet. It is the expected behavior of a well-designed packaged diode, where parasitic elements do not significantly affect performance. Only a small variation is observed in the S-parameters (Figure 13a) at the frequencies where packaging effects start to dominate. It is important to emphasize, however, that this effect should be considered to accurately determine the actual impedance value.

When the packaging is not well designed and the parasitic effects (inductance and capacitance) are higher, the resonances in the impedance appear at lower frequencies, affecting the diode’s behavior where only intrinsic effects should be present. This case is analyzed below. It is important to emphasize that when the matching results from the impedance of the intrinsic part of the diode, it varies with bias. In contrast, when the matching results from the impedance of diode packaging, it appears at all bias points, interfering with the diode’s rectifying behavior.

4.1.2. Impact of an Increase in $L_f$ on Packaged Diode Behavior at 0.5 V

In this and the following analyses, the packaged diode with parasitic values extracted in the Section 3 is compared against packaged diodes with modified parasitic elements. From this point forward, the diode with extracted values will be referred to as the nominal diode.

In this case, $L_f$ is set to 6 nH. In the impedance plots (Figure 13b,c), the resonance shifts from 25.8 GHz (nominal diode) to 5.4 GHz, a frequency where intrinsic behavior should dominate. From the S-parameters (Figure 13a), the diode is matched at 973 MHz with −25 dB, but this changes to −2.2 dB at 3.48 GHz. This behavior occurs because the imaginary part of the impedance crosses zero (matching) and then increases rapidly (mismatch). The mismatch at 3.48 GHz indicates that the packaging has lowered the operating frequency, since this effect will appear at all bias points.

4.1.3. Impact of an Increase in $L_p$ on Packaged Diode Behavior at 0.5 V

In this analysis, $L_p$ is set to 1 nH. In the imaginary part of the impedance (Figure 13b), the resonance shifts upward compared to the nominal diode, while the real part (Figure 13c) shows no noticeable change. In the S-parameters, the diode is matched at 2.55 GHz with −13.7 dB, and at 9.1 GHz, the matching changes to −2.2 dB. This behavior occurs because the imaginary part of the impedance crosses zero (matching) and then increases (mismatch). The mismatch at 9.1 GHz indicates that the packaging has lowered the operating frequency, since this effect will appear at all bias points.

4.1.4. Impact of an Increase in $C_{pp}$ on Packaged Diode Behavior at 0.5 V

In this analysis, $C_{pp}$ is set to 0.8 pF. In impedance (Figure 13b,c), the resonance shifts to 15.88 GHz and its magnitude decreases, allowing the diode to match with the port. As a result, the S-parameters show this second resonance as a matching point (Figure 13a). This is a packaging effect and, although its impact is the opposite to the previous two cases, it also limits the diode’s operating frequency.

4.1.5. Impact of an Increase in $C_{pp}$ on Packaged Diode Behavior at −5 V, 0.5 V and 1.22 V

To demonstrate how $C_{pp}$ = 0.8 pF limits the operating frequency across all bias points, Figure 14 shows the S-parameters of packaged diodes at different bias conditions.

Figure 14. S-parameters of packaged diodes at different bias points and package conditions. The bias points considered are: −5 V nominal, −5 V with $C_{pp}$ = 0.8 pF, 1.22 V nominal, 1.22 V with $C_{pp}$ = 0.8 pF, and −0.5 V with $C_{pp}$ = 0.8 pF.

As in the previous section, the term nominal refers to the curves whose packaging parameters are those extracted and listed in Table 1. The bias points considered are: −5 V nominal, −5 V with $C_{pp}$ = 0.8 pF, 1.22 V nominal, 1.22 V with $C_{pp}$ = 0.8 pF, and −0.5 V with $C_{pp}$ = 0.8 pF (this last point was analyzed in the previous section).

As expected, the −5 V and 1.22 V nominal plots remain close to 0 dB, since they represent an open circuit and a short circuit, respectively. In the plots for −5 V, −0.5 V, and 1.22 V with $C_{pp}$ = 0.8 pF, a matching point appears at 16.8, 15.88, and 11.1 GHz. The frequency shift of these matchings is due to the combined effects of the diode’s intrinsic part and the packaging. Since the matchings appear across all bias points, the diode is not rectifying but instead acting as a partially matched load to the port, which is an undesired behavior. In the diode packaging, changes in inductance can be associated with the size of the pads and internal interconnections, while changes in capacitance may result from variations in the size and spacing of the contact pads.

In summary, the behavior of both the unpackaged diode and its packaging can be analyzed in terms of polarization and frequency. With respect to polarization, the impedance of the unpackaged diode will depend on the polarization, while the impedance of the diode package will remain independent of it. In terms of frequency, the unpackaged diode will exhibit its rectifying behavior up to a maximum frequency, whereas the diode package shows a frequency at which it has its greatest contribution. If the maximum operating frequency of the unpackaged diode is lower than the frequency at which the packaging exhibits its dominant influence, the packaging effects do not meaningfully affect the diode’s rectification performance. On the contrary, if the maximum operating frequency of the unpackaged diode is higher than the frequency at which the packaging exhibits its dominant influence, the packaging will considerably affect the diode’s rectification performance, reducing the maximum frequency at which the diode can rectify.

4.2. Expectations on Diode Measurements

Diode measurements can be analyzed by the S₁₁ parameter graph in dB, interpreting the Smith Chart, and comparing the impedance and admittance responses.

The expected S-parameter behavior under single-port measurements at various bias points is illustrated in Figure 11 and Figure 12. In the non-conducting region, the diode behaves as an open circuit (Figure 11a and Figure 12a), whereas in the conducting region, it acts as a short circuit (Figure 11c and Figure 12c). In both cases, the S₁₁ values are close to 0 dB. The most informative behavior, however, occurs during the transition between these two states. As the diode begins to conduct, its impedance gradually decreases, eventually approaching the 50 ohm impedance of the measurement port. At this point, proper impedance matching is achieved, enabling maximum RF power transfer to the diode. This condition is observed in Figure 11b and Figure 12b, where peak power transfer occurs at a bias of 0.5 V.

In addition to the S-parameters in dB, the magnitude and phase of the models should exhibit strong correlation. Figure 15 shows the magnitude and phase of the S-parameters for the packaged diode across the three operating regions.

Figure 15. S₁₁ parameter of the measurement and electrical model of the packaged diode at different bias points. (a) magnitude and (b) phase from −5 V to 0.3 V, (c) magnitude and (d) phase from 0.4 V to 0.6 V and, (e) magnitude and (f) phase from 0.7 V to 1.22 V.

The Smith Chart corresponding to a measurement at 0.4 V is presented in Figure 16. Figure 16a shows the raw data, Figure 16b illustrates the results after de-embedding the open and short structures, whereas Figure 16c displays the response after removing the packaging parasitics. A consistent match across these stages is expected to validate the de-embedding process and parasitic extraction.

Figure 16. Smith Chart of the diode at 0.4 V bias. The measured data are shown in blue, and the proposed model is shown in red. (a) Packaged diode with measurement structure, (b) packaged diode, and (c) unpackaged diode.

In Figure 16c (unpackage diode), it is observed that the impedance is entirely located at the bottom half of the Smith chart, indicating that it is dominated by capacitive reactance, which can be attributed to the junction capacitance. In Figure 16b (packaged diode), it is observed that part of the diode’s impedance has shifted to the upper part of the Smith chart, indicating that the packaging of the diode has introduced this inductive reactance, which can be attributed to the metallic pads and internal connections. Finally, in Figure 16a (raw diode), it is observed that part of the diode’s impedance has shifted to the lower half of the Smith chart again, indicating that the de-embedding structures introduce an additional capacitive reactance. This behavior can be attributed to the high permittivity of the de-embedding structures

Figure 17 presents the impedance and admittance curves of the diode, both with packaging and the intrinsic model only. To ensure that a proposed intrinsic electrical model accurately represents the physical device, the simulated impedance and admittance must match those obtained from measurement.

Figure 17. (a) $Real\left(Z\right)$, (b) $Im\left(Z\right)$, (c) $Real\left(Y\right)$, and (d) $Im\left(Y\right)$ of the packaged diode at 0.4 V bias. (e) $Real\left(Z\right)$, (f) $Im\left(Z\right)$, (g) $Real\left(Y\right)$, and (h) $Im\left(Y\right)$ of the intrinsic part of the diode at 0.4 V bias. The measured data are shown in blue, and the proposed model is shown in red.

In summary, S₁₁ parameters in dB help verify the correct diode operation across different bias points. The Smith Chart provides insight into the diode’s behavior as an open or short circuit and confirms consistency throughout the de-embedding and parasitic extraction stages. Finally, impedance and admittance analyses play a key role in validating the proposed models

4.3. Packaging Electrical Model

One of the most comprehensive models for diode packaging is presented in [10], with its schematic representation provided in Figure 18. The intrinsic region is represented by the Int box, and its electrical model varies depending on the diode type (PN junction, PIN, Schottky). The rest of parameters belong to the extrinsic part of the diode. Despite its apparent completeness, the model incorporates components that are not physically associated with the diode.

Figure 18. Electrical model of the diode based on [10]. The intrinsic diode region is represented as Int box. In [21], it is demonstrated that $C_{p1}$ and $C_{p2}$ are not part of the diode model.

The capacitors $C_{p1}$ and $C_{p2}$ of the π-networks represent parasitic capacitances between the contact pads and the ground planes. These components are not part of the diode but arise from the measurement setup itself. Specifically, in two-port configurations, whether microstrip or CPW, both the anode and the cathode are connected to the signal path, and $C_{p1}$ and $C_{p2}$ emerge as parasitic elements between the pads soldered to the signal trace and ground. The calculations of $C_{p1}$ and $C_{p2}$ have been addressed by [21], who demonstrated that the values of $C_{p1}$ and $C_{p2}$ vary significantly depending on the substrate used during characterization. Such variability confirms that these capacitances are not inherent to the diode package but are parasitic effects introduced by the two-port measurement setup. Moreover, this conclusion can be easily validated by implementing the model in a shunt configuration by grounding one of the terminals: in this setup, $C_{p1}$/2 (or $C_{p2}$/2) becomes immediately shorted and additionally, a parallel LC ($L_{p1}$ and $C_{p1}$/2) network is formed, further reinforcing the assertion that these elements originate from the measurement setup and not from the physical structure of the diode. Once this distinction is established, the π-network structures at both ends of the circuit can be simplified to two inductors, $L_{p1}$ and $L_{p2}$. These inductors are in series with the rest of the packaging model and can be combined into a single equivalent inductance, $L_p$. The capacitance of the diode’s internal connections has been analyzed using electromagnetic simulations and the design of specialized structures in [22,23]. It has been observed that its value is around a few fF, significantly lower than that of $C_{pp}$. Furthermore, the effects of $C_{fp}$, due to its small value, are noticeable in the THz range [23]. As a result, it may be disregarded, as evidenced by the graphs presented throughout this work, where the model used accurately replicates the packaged diode measurements.

4.4. Method Limitations

One of the requirements for applying the method is that resonances must be measurable, which requires high-frequency measurements. However, in the Section 3, a second parameter extraction (A-B-D extraction) is performed at a frequency lower than the resonance frequency, demonstrating a good correlation between the model and the measurement up to the frequency where the highest point was chosen for the extraction, as shown in Figure 9.

In [11], measurements of Schottky diodes of various sizes are performed in a single-port configuration up to a frequency of 325 GHz. In the impedance graphs presented, resonance can be observed, which demonstrates that the resonance is a generalized behavior present in different types of diodes and at higher frequencies. This indicates that the method presented throughout this work can be applied to different types of diodes and even to higher frequencies.

4.5. Future Research Directions

The next steps in the research are: first, to analyze the behavior of the diode’s linear and nonlinear elements under stress conditions, such as temperature and electromagnetic coupling; and second, to observe the diode’s operation within a system. Some approaches that are already starting to analyze ideas include those based on time-domain [24,25]. A time-domain approach is presented in [24], where the diode is analyzed as part of a rectifier circuit, where diode reverse conduction, temperature and load are included in the model. In [25], a time-domain state-space model is proposed for modeling rectifiers, using a combination of ordinary differential equations and a semi-discrete electromagnetic system to represent the interaction between the rectifier and the electromagnetic fields. The following investigations should be directed in that direction, establishing models of the device under stress conditions and proposing experiments that can reliably verify the models.

5. Conclusions

This work presented a simple and effective method for extracting the parasitic packaging parameters in diodes, demonstrating that the packaging can be modeled using three elements: the pad-to-pad capacitance ($C_{pp}$), the pad inductance ($L_p$), and the internal connection inductance ($L_f$). These parameters can be determined from the resonance observed in the diode’s reactance.

It was shown that in devices with a well-designed package, the packaging effects do not significantly impact the performance of the diode’s intrinsic part. In contrast, poorly designed packaging can limit its rectification operating frequency, by making the diode exhibit similar behavior across all bias points.

Furthermore, the combined analysis of DC and RF measurements allowed the identification of three operating regions of the diode based on its frequency response, which can be categorized into non-conduction, semi-conduction, and full conduction regions, each of which requires a distinct electrical model. Lastly, the importance of properly modeling the de-embedding structures, particularly the open structure, was highlighted, as its inductive and capacitive effects, related to the substrate’s high permittivity and physical dimensions, impact meaningfully at both low and high frequencies.