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Open AccessArticle

High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components

Faculty of Information Technology, Ton Duc Thang University, Ho Chi Minh City 758307, Vietnam
Department of Information and Communication Engineering, Inha University, Incheon 22212, Korea
Author to whom correspondence should be addressed.
Electronics 2020, 9(7), 1075;
Received: 17 May 2020 / Revised: 24 June 2020 / Accepted: 28 June 2020 / Published: 30 June 2020
(This article belongs to the Special Issue System-on-Chip (SoC) Design and Its Applications)
A high efficiency architecture for ring learning with errors (ring-LWE) cryptoprocessor using shared arithmetic components is presented in this paper. By applying a novel approach for sharing number theoretic transform (NTT) polynomial multiplier and polynomial adder in encryption and decryption operations, the total number of polynomial multipliers and polynomial adders used in the proposed ring-LWE cryptoprocessor are reduced. In addition, the processing time of NTT polynomial multiplier is speeded up by employing multiple-path delay feedback (MDF) architecture and deploying pipelined technique between all stages of NTT processes. As a result, the proposed architecture offers a great reduction in terms of the hardware complexity and computation latency compared with existing works. The implementation result for the proposed ring-LWE cryptoprocessor on Virtex-7 FPGA board using Xilinx VIVADO shows a significant decrease in the number of slices and LUTs compared with previous works. Moreover, the proposed ring-LWE cryptoprocessor offers higher throughput and efficiency than its predecessors.
Keywords: cryptoprocessor; pipelined; multiple-path delay feedback; ring-LWE; shared arithmetic components cryptoprocessor; pipelined; multiple-path delay feedback; ring-LWE; shared arithmetic components
MDPI and ACS Style

Nguyen Tan, T.; Thi Bao Nguyen, T.; Lee, H. High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components. Electronics 2020, 9, 1075.

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