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Open AccessFeature PaperArticle

A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications

Division of Electronic Engineering, Jeonbuk National University, Jollabuk-do 561-756, Korea
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Electronics 2020, 9(4), 562; https://doi.org/10.3390/electronics9040562
Received: 17 February 2020 / Revised: 19 March 2020 / Accepted: 25 March 2020 / Published: 27 March 2020
(This article belongs to the Special Issue CMOS Power Amplifier Design and Applications)
A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load Ropt, resulting in maximum output power with peak power added efficiency (PAE). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × VDD, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show Ropt of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (Psat) of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration. View Full-Text
Keywords: antenna impedance mismatch; breakdown; cascode inverter; CMOS; impedance coverage; power added efficiency; re-configurability; stacked power amplifier antenna impedance mismatch; breakdown; cascode inverter; CMOS; impedance coverage; power added efficiency; re-configurability; stacked power amplifier
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Kim, D.-M.; Kim, D.; Jeong, H.-G.; Im, D. A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications. Electronics 2020, 9, 562.

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