A Reconﬁgurable CMOS Inverter-based Stacked Power Ampliﬁer with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications

: A reconﬁgurable CMOS inverter-based stacked power ampliﬁer (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the speciﬁc power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor ﬁeld-e ﬀ ect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage ( V th ) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter ampliﬁer. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load R opt , resulting in maximum output power with peak power added e ﬃ ciency ( PAE ). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × V DD , and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconﬁgurable PA supports three operation modes: cascode inverter conﬁguration (CIC), double-stacked cascode inverter conﬁguration (DSCIC) and double-stacked inverter conﬁguration (DSIC). These show R opt of around 100, 50 and 25 Ω , respectively. In the simulation results, the proposed PA operating under the three conﬁgurations showed a saturated output power ( P sat ) of + 6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a P sat of + 4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a P sat of + 5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design signiﬁcantly extends impedance coverage, while maintaining an output power exceeding the speciﬁc power level, without sacriﬁcing power e ﬃ ciency using only hardware reconﬁguration.


Introduction
As wireless electronic devices continue to be miniaturized, and further support multi-functionality, antenna size reduction is required because most mobile platforms have a limited space for all of the necessary antennas. The small radiator size of a miniaturized antenna greatly reduces its bandwidth, and this leads to a high quality factor (Q-factor) for the antenna. RF/analog circuits to exploit many advantages of technology scaling. For these reasons, inverter-based PAs have been widely adopted for low power short-range wireless technologies. Figure 1a shows a schematic of a conventional three-stage inverter-based PA. The hardware configuration is very simple, because there are no inductors or transformers, and as a result, it is easily implemented in a low cost digital CMOS process The previous works of Paidimarri et al. [11], Kiumarsi et al. [12], and Van Langevelde et al. [13] presented the inverter-based, push-pull topologies for PA applications, but there was no study for compensating the antenna impedance mismatch effect with the same RF performances. The first and second stages are drive amplifiers (DAs) for boosting the weak input signal with sufficiently high gain and extremely low power consumption, and the last stage is the output stage for obtaining maximum output power under the given load condition. Instead of using a dc biasing method with a shunt feedback configuration, a replica biasing circuit is adopted to provide a stable dc operating point to the inverter stage, and to ensure a rail-to-rail output swing. By adjusting the channel width ratio between the NMOS and PMOS transistors, the dc operating point of the inverter stages is around half of V DD . Compared to a common-source topology with an inductor load, the output voltage swing of the inverter-based PA is reduced by almost half. As shown in Figure 1b, its output voltage swing is expressed as where V gs,N and V sg,P are the gate-to-source and source-to-gate dc bias voltages applied to the NMOS and PMOS transistors, and V th,N and V th,P are the threshold voltages of the NMOS and PMOS transistors. Typically, V gs,N and V sg,P are set to be equal to half of V DD to maximize the output voltage swing. From (1) and (2), it can be seen that it is desirable to increase the threshold voltage (V th ) of the MOSFET for the maximum output voltage swing. Modern deep-submicron CMOS technologies support multiple-V th MOSFETs to reduce leakage power by assigning a high V th to some transistors in non-critical paths. Therefore, for a simple hardware configuration, in the circuit design for the last stage of the inverter-based PA, high-V th MOSFETs are used instead of applying a body bias voltage to increase V th in regular-V th MOSFETs. Figure 2 shows the simulated output power, the PAE and the power contour of the three-stage inverter-based PA using regular-V th MOSFETs and high-V th MOSFETs under a 50 Ω load impedance condition. Both PAs were designed to consume the same static dc current of 2.3 mA. The saturated output power (P sat ) and peak PAE are +1.2 dBm and 32.6% for the PA with the regular-V th MOSFETs and +2.8 dBm and 41.4% for the PA with the high-V th MOSFETs. As predicted, using the high-V th MOSFETs increases the output voltage swing without any additional dc current, enhances P sat and peak PAE, and extends the impedance coverage while maintaining an output power of greater than 0 dBm. Electronics 2020, 9, 562 3 of 12 intensive and digital-oriented RF/analog circuits to exploit many advantages of technology scaling. For these reasons, inverter-based PAs have been widely adopted for low power short-range wireless technologies. Figure 1a shows a schematic of a conventional three-stage inverter-based PA. The hardware configuration is very simple, because there are no inductors or transformers, and as a result, it is easily implemented in a low cost digital CMOS process The previous works of Paidimarri et al. [11], Kiumarsi et al. [12], and Van Langevelde et al. [13] presented the inverter-based, push-pull topologies for PA applications, but there was no study for compensating the antenna impedance mismatch effect with the same RF performances. The first and second stages are drive amplifiers (DAs) for boosting the weak input signal with sufficiently high gain and extremely low power consumption, and the last stage is the output stage for obtaining maximum output power under the given load condition. Instead of using a dc biasing method with a shunt feedback configuration, a replica biasing circuit is adopted to provide a stable dc operating point to the inverter stage, and to ensure a rail-to-rail output swing. By adjusting the channel width ratio between the NMOS and PMOS transistors, the dc operating point of the inverter stages is around half of VDD. Compared to a common-source topology with an inductor load, the output voltage swing of the inverter-based PA is reduced by almost half. As shown in Figure 1b, its output voltage swing is expressed as where Vgs,N and Vsg,P are the gate-to-source and source-to-gate dc bias voltages applied to the NMOS and PMOS transistors, and Vth,N and Vth,P are the threshold voltages of the NMOS and PMOS transistors. Typically, Vgs,N and Vsg,P are set to be equal to half of VDD to maximize the output voltage swing. From (1) and (2), it can be seen that it is desirable to increase the threshold voltage (Vth) of the MOSFET for the maximum output voltage swing. Modern deep-submicron CMOS technologies support multiple-Vth MOSFETs to reduce leakage power by assigning a high Vth to some transistors in non-critical paths. Therefore, for a simple hardware configuration, in the circuit design for the last stage of the inverter-based PA, high-Vth MOSFETs are used instead of applying a body bias voltage to increase Vth in regular-Vth MOSFETs. Figure 2 shows the simulated output power, the PAE and the power contour of the three-stage inverter-based PA using regular-Vth MOSFETs and high-Vth MOSFETs under a 50 Ω load impedance condition. Both PAs were designed to consume the same static dc current of 2.3 mA. The saturated output power (Psat) and peak PAE are +1.2 dBm and 32.6% for the PA with the regular-Vth MOSFETs and +2.8 dBm and 41.4% for the PA with the high-Vth MOSFETs. As predicted, using the high-Vth MOSFETs increases the output voltage swing without any additional dc current, enhances Psat and peak PAE, and extends the impedance coverage while maintaining an output power of greater than 0 dBm.

Proposed Reconfigurable Cascode Inverter-based Stacked PA
The most efficient output power (Pout,eff) of a PA is determined by the optimum load impedance Ropt and maximum (zero-to-peak) output voltage swing vout,max. This relationship is given as Eq. (3) implies that the PA can extend the impedance coverage while maintaining an output power exceeding the specific power level by varying vout,max through hardware reconfiguration. Figure 3 shows the proposed reconfigurable cascode inverter-based stacked PA driven by a supply voltage of 2×VDD with three operation modes. The first and second stages are DA stages, while the last stage is a PA stage. In designing the DA, to alleviate the breakdown issues resulting from operating at a supply voltage of 2×VDD, two identical inverters are stacked in series, and a bypass capacitor is placed between them to short ac signals to ground at the operating frequency. For all stages, high-Vth MOSFETs are employed to enhance Psat and peak PAE. All transistors in the proposed reconfigurable PA are thin gate oxide MOSFETs for high frequency operation. The unit cell of the last PA stage is based on a cascode inverter, which is implemented by adding cascode transistors (MN2 and MP2) to the traditional inverter amplifier (MN1 and MP1). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2×VDD alone, and also decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the reconfigurable PA. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the value of vout,max in (3), and eventually change Ropt, yielding the maximum output power with peak PAE. The resistance value of RG (10 kΩ) is high enough to block ac signals, and only pass dc bias voltage. The capacitance value of CG, CO and CB are 2 pF, 10 pF and 10 pF, respectively, in this design. Similarly, their capacitance value is high enough to block dc bias voltage and only pass ac signals. It was verified through simulation that their side effects on the overall performance were negligible.

Proposed Reconfigurable Cascode Inverter-based Stacked PA
The most efficient output power (P out,eff ) of a PA is determined by the optimum load impedance R opt and maximum (zero-to-peak) output voltage swing v out,max . This relationship is given as Equation (3) implies that the PA can extend the impedance coverage while maintaining an output power exceeding the specific power level by varying v out,max through hardware reconfiguration. Figure 3 shows the proposed reconfigurable cascode inverter-based stacked PA driven by a supply voltage of 2 × V DD with three operation modes. The first and second stages are DA stages, while the last stage is a PA stage. In designing the DA, to alleviate the breakdown issues resulting from operating at a supply voltage of 2 × V DD , two identical inverters are stacked in series, and a bypass capacitor is placed between them to short ac signals to ground at the operating frequency. For all stages, high-V th MOSFETs are employed to enhance P sat and peak PAE. All transistors in the proposed reconfigurable PA are thin gate oxide MOSFETs for high frequency operation. The unit cell of the last PA stage is based on a cascode inverter, which is implemented by adding cascode transistors (M N2 and M P2 ) to the traditional inverter amplifier (M N1 and M P1 ). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × V DD alone, and also decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the reconfigurable PA. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the value of v out,max in (3), and eventually change R opt , yielding the maximum output power with peak PAE. The resistance value of R G (10 kΩ) is high enough to block ac signals, and only pass dc bias voltage. The capacitance value of C G , C O and C B are 2 pF, 10 pF and 10 pF, respectively, in this design. Similarly, their capacitance value is high enough to block dc bias voltage and only pass ac signals. It was verified through simulation that their side effects on the overall performance were negligible. In the cascode inverter configuration (on the far left in Figure 3), the middle spot between the two cascode inverters is directly connected to the physical ground through switch S1, and the upper cascode inverter, which is composed of transistors MN1, MN2, MP1 and MP2 operated in the saturation region, is only enabled. The output voltage swing in this mode is given as where Vgs,N1 (2) and Vsg,P1 (2) are the gate-to-source and source-to-gate dc bias voltages applied to MN1(MN2) and MP1(MP2), and Vth,N1 (2) and Vth,P1 (2) Figure 4 shows the loadpull simulation results of the proposed reconfigurable PA for the three modes. The simulated Ropt yielding a maximum output power of around +6 dBm is about 100 Ω for the cascode inverter configuration. This closely matches the calculated result. Because the upper cascode inverter is driven by a supply voltage of 2×VDD (greater than the nominal supply voltage VDD), it is important to ensure in the design that the transistor's drain-to-source voltage swing does not exceed the pre-specified value of its drain-to-source breakdown voltage (BVDS). This prevents the permanent damage and gradual degradation in device performance over time caused by gate-oxide breakdown and hot carrier degradation. Figure 5 presents the simulated output voltage waveform, source-to-drain voltage waveforms driven by MP1 and MP2 (vsd,P1 and vsd,P2), and drain-to-source voltage waveforms driven by MN2 and MN1 (vds,N2 and vds,N1) when the proposed PA in the cascode inverter configuration generates an output power of +3 dBm under a 100 Ω load impedance. In the cascode inverter configuration (on the far left in Figure 3), the middle spot between the two cascode inverters is directly connected to the physical ground through switch S 1 , and the upper cascode inverter, which is composed of transistors M N1 , M N2 , M P1 and M P2 operated in the saturation region, is only enabled. The output voltage swing in this mode is given as where V gs,N1 (2) and V sg,P1 (2) are the gate-to-source and source-to-gate dc bias voltages applied to M N1 (M N2 ) and M P1 (M P2 ), and V th,N1 (2) and V th,P1 (2) are the threshold voltages of M N1 (M N2 ) and M P1 (M P2 ). Assuming the overdrive voltage V dsN1,sat , V dsN2,sat , V sdP1,sat and V sdP2,sat are all 0.2 V, the nominal supply voltage V DD is 1.2 V, and a maximum output power of around +6 dBm is delivered to the load by the PA. The value of v out,max and R opt are calculated to be 0.8 V op and 80 Ω using Equation (3). Figure 4 shows the load-pull simulation results of the proposed reconfigurable PA for the three modes. The simulated R opt yielding a maximum output power of around +6 dBm is about 100 Ω for the cascode inverter configuration. This closely matches the calculated result. Because the upper cascode inverter is driven by a supply voltage of 2 × V DD (greater than the nominal supply voltage V DD ), it is important to ensure in the design that the transistor's drain-to-source voltage swing does not exceed the pre-specified value of its drain-to-source breakdown voltage (BV DS ). This prevents the permanent damage and gradual degradation in device performance over time caused by gate-oxide breakdown and hot carrier degradation. Figure 5 presents the simulated output voltage waveform, source-to-drain voltage waveforms driven by M P1 and M P2 (v sd,P1 and v sd,P2 ), and drain-to-source voltage waveforms driven by M N2 and M N1 (v ds,N2 and v ds,N1 ) when the proposed PA in the cascode inverter configuration generates an output power of +3 dBm under a 100 Ω load impedance.
Electronics 2020, 9, 562 6 of 12 It can be seen that the cascode transistors MP2 and MN2 share the burden of the over-voltage stress and mitigate the breakdown issues of the thin gate oxide MOSFETs. Because all source-to-drain and drain-to-source voltage swings do not exceed the BVDS of 1.2 V provided by the adopted process technology, and because this is ac stress instead of dc stress, the cascode inverter configuration of the proposed PA does not experience device breakdown.  In the double-stacked cascode inverter configuration, both the upper and lower cascode inverters are enabled. Switch S1 is open, the middle spot between the two cascode inverters is biased at half of the 2×VDD supply voltage, and this node is ac grounded through the large bypass capacitor It can be seen that the cascode transistors MP2 and MN2 share the burden of the over-voltage stress and mitigate the breakdown issues of the thin gate oxide MOSFETs. Because all source-to-drain and drain-to-source voltage swings do not exceed the BVDS of 1.2 V provided by the adopted process technology, and because this is ac stress instead of dc stress, the cascode inverter configuration of the proposed PA does not experience device breakdown.  In the double-stacked cascode inverter configuration, both the upper and lower cascode inverters are enabled. Switch S1 is open, the middle spot between the two cascode inverters is biased at half of the 2×VDD supply voltage, and this node is ac grounded through the large bypass capacitor It can be seen that the cascode transistors M P2 and M N2 share the burden of the over-voltage stress and mitigate the breakdown issues of the thin gate oxide MOSFETs. Because all source-to-drain and drain-to-source voltage swings do not exceed the BV DS of 1.2 V provided by the adopted process technology, and because this is ac stress instead of dc stress, the cascode inverter configuration of the proposed PA does not experience device breakdown.
In the double-stacked cascode inverter configuration, both the upper and lower cascode inverters are enabled. Switch S 1 is open, the middle spot between the two cascode inverters is biased at half of the 2 × V DD supply voltage, and this node is ac grounded through the large bypass capacitor C B . Ideally, this should yield almost the same maximum output power as the aforementioned cascode inverter configuration because the total output current is doubled by combining the two output currents from the upper and lower cascode inverters, while the final output voltage swing is reduced by half. This implies that the value of R opt , which yields the maximum output power from the double-stacked cascode inverter configuration, is lower than that of the cascode inverter configuration. As shown in Figure 4a,b, the double-stacked cascode inverter configuration provides a simulated R opt of around 50 Ω, which is approximately half the value of the simulated R opt of the cascode inverter configuration. Unfortunately, because the two output currents generated from the upper and lower cascode inverters are not completely identical due to mismatches, a slight degradation (1-2 dB) of the maximum output power is unavoidable.
The last mode of the proposed reconfigurable PA is the double-stacked inverter configuration of the circuit schematic on the far right in Figure 3. Unlike in the double-stacked cascode inverter configuration, all cascode transistors M P2 , M P4 , M N2 and M N4 operate in the linear region as switches by applying a gate-to-source (source-to-gate) voltage of V DD to the NMOS (PMOS) transistors M N2 and M N4 (M P2 and M P4 ), and completely turning on the MOSFETs. Because the cascode configuration typically provides a high output impedance with a slightly reduced output voltage swing, the output impedance of the double-stacked inverter configuration (DSIC) is lower than that of the double-stacked cascode inverter configuration (DSCIC) at an operating frequency of 2.4 GHz, as shown in Figure 6. For maximum power transfer, it is desirable to decrease the output impedance of the reconfigurable PA to shift the impedance coverage to the lower impedance region to maintain an output power exceeding the specific power level. As shown in Figure 4c, the double-stacked inverter configuration provides a simulated R opt of around 25 Ω, which is approximately half the value of the simulated R opt for the double-stacked cascode inverter configuration, and covers a low impedance of less than 5 Ω for an output power greater than 0 dBm. In addition, the maximum output power is increased by 1 dB in comparison with the double-stacked cascode inverter configuration, because there is no additional voltage headroom for the cascode transistors M P2 , M P4 , M N2 and M N4 . CB . Ideally, this should yield almost the same maximum output power as the aforementioned cascode inverter configuration because the total output current is doubled by combining the two output currents from the upper and lower cascode inverters, while the final output voltage swing is reduced by half. This implies that the value of Ropt, which yields the maximum output power from the doublestacked cascode inverter configuration, is lower than that of the cascode inverter configuration. As shown in Figure 4a,b, the double-stacked cascode inverter configuration provides a simulated Ropt of around 50 Ω, which is approximately half the value of the simulated Ropt of the cascode inverter configuration. Unfortunately, because the two output currents generated from the upper and lower cascode inverters are not completely identical due to mismatches, a slight degradation (1-2 dB) of the maximum output power is unavoidable. The last mode of the proposed reconfigurable PA is the double-stacked inverter configuration of the circuit schematic on the far right in Figure 3. Unlike in the double-stacked cascode inverter configuration, all cascode transistors MP2, MP4, MN2 and MN4 operate in the linear region as switches by applying a gate-to-source (source-to-gate) voltage of VDD to the NMOS (PMOS) transistors MN2 and MN4 (MP2 and MP4), and completely turning on the MOSFETs. Because the cascode configuration typically provides a high output impedance with a slightly reduced output voltage swing, the output impedance of the double-stacked inverter configuration (DSIC) is lower than that of the doublestacked cascode inverter configuration (DSCIC) at an operating frequency of 2.4 GHz, as shown in Figure 6. For maximum power transfer, it is desirable to decrease the output impedance of the reconfigurable PA to shift the impedance coverage to the lower impedance region to maintain an output power exceeding the specific power level. As shown in Figure 4c, the double-stacked inverter configuration provides a simulated Ropt of around 25 Ω, which is approximately half the value of the simulated Ropt for the double-stacked cascode inverter configuration, and covers a low impedance of less than 5 Ω for an output power greater than 0 dBm. In addition, the maximum output power is increased by 1 dB in comparison with the double-stacked cascode inverter configuration, because there is no additional voltage headroom for the cascode transistors MP2, MP4, MN2 and MN4.

Simulation Results
The proposed reconfigurable PA was designed using a 65-nm CMOS process. Because of a standalone circuit pattern, a simple input matching network composed of one series inductor and one shunt capacitor was placed in front of the first DA stage of the proposed PA. Figure 7 shows the simulated forward transmission coefficient (S21) and input reflection coefficient (S11) of the completed PA operated in the cascode inverter configuration (CIC), DSCIC and DSIC. Simulated value for S21 ranges from 30 dB to 35 dB, and the simulated value for S11 is lower than -10 dB at an operating

Simulation Results
The proposed reconfigurable PA was designed using a 65-nm CMOS process. Because of a standalone circuit pattern, a simple input matching network composed of one series inductor and one shunt capacitor was placed in front of the first DA stage of the proposed PA. Figure 7 shows the simulated forward transmission coefficient (S 21 ) and input reflection coefficient (S 11 ) of the completed PA operated in the cascode inverter configuration (CIC), DSCIC and DSIC. Simulated value for S 21 ranges from 30 dB to 35 dB, and the simulated value for S 11 is lower than −10 dB at an operating frequency of 2.4 GHz for all three configurations. Figure 8a presents the simulated P sat and PAE of the complete PA in each operation mode.
In the simulation results, the proposed PA operated in CIC, DSCIC and DSIC shows a Psat of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance, respectively. Figure 8b shows the simulated total impedance coverage of the proposed reconfigurable PA, while maintaining the output power of greater than +2, +3, +4 and +5 dBm. Compared to conventional inverter-based PAs, impedance coverage is significantly extended, while output power that exceeds the specific power level is maintained without sacrificing power efficiency using only hardware reconfiguration. The proposed PA can compensate for antenna impedance mismatch without any inductors or transformers, and can have the same effect as a TMN at the output stage.  dBm and a peak PAE of 41.1% under a 100 Ω load impedance, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance, respectively. Figure 8b shows the simulated total impedance coverage of the proposed reconfigurable PA, while maintaining the output power of greater than +2, +3, +4 and +5 dBm. Compared to conventional inverter-based PAs, impedance coverage is significantly extended, while output power that exceeds the specific power level is maintained without sacrificing power efficiency using only hardware reconfiguration. The proposed PA can compensate for antenna impedance mismatch without any inductors or transformers, and can have the same effect as a TMN at the output stage.  In the simulation results, the proposed PA operated in CIC, DSCIC and DSIC shows a P sat of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance, a P sat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance, and a P sat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance, respectively. Figure 8b shows the simulated total impedance coverage of the proposed reconfigurable PA, while maintaining the output power of greater than +2, +3, +4 and +5 dBm. Compared to conventional inverter-based PAs, impedance coverage is significantly extended, while output power that exceeds the specific power level is maintained without sacrificing power efficiency using only hardware reconfiguration. The proposed PA can compensate for antenna impedance mismatch without any inductors or transformers, and can have the same effect as a TMN at the output stage. Figure 9a,b show the simulated output voltage waveforms of the complete PA according to the change of circuit configuration under a 200 Ω load impedance and a 5 Ω load impedance, respectively. The RF sinusoidal signal with a power of −10 dBm was applied in order to achieve an output power close to P sat . As predicted, the CIC yields the highest output voltage swing among three configurations when the complete PA directly drives a load impedance greater than 100 Ω, and similarly the DSIC generates the highest output voltage swing among three configurations when it directly drives a Electronics 2020, 9, 562 9 of 11 load impedance less than 25 Ω. This implies that the proposed reconfigurable PA can change its operation mode automatically over the load impedance variation, by detecting the output voltage swing through a RF envelope detector, and selecting the operation mode to maximize the detector output voltage. Figure 10 shows the possible design for the fully integrated reconfigurable PA, including an automatic tuning circuit. Many researches of [14][15][16] reported an extremely low power RF envelope detector circuit in CMOS at 2.4 GHz frequency band, and most of them adopted the common source-based envelope detector circuit due to high RF-to-DC conversion characteristic. Because the common source-based envelope detectors provide relatively high input impedance, and their power consumption is around microwatt level or below, their effects on the overall RF performance of the proposed PA can be negligible.
Electronics 2020, 9, 562 9 of 12 Figure 9a,b show the simulated output voltage waveforms of the complete PA according to the change of circuit configuration under a 200 Ω load impedance and a 5 Ω load impedance, respectively. The RF sinusoidal signal with a power of -10 dBm was applied in order to achieve an output power close to Psat. As predicted, the CIC yields the highest output voltage swing among three configurations when the complete PA directly drives a load impedance greater than 100 Ω, and similarly the DSIC generates the highest output voltage swing among three configurations when it directly drives a load impedance less than 25 Ω. This implies that the proposed reconfigurable PA can change its operation mode automatically over the load impedance variation, by detecting the output voltage swing through a RF envelope detector, and selecting the operation mode to maximize the detector output voltage. Figure 10 shows the possible design for the fully integrated reconfigurable PA, including an automatic tuning circuit. Many researches of [14][15][16] reported an extremely low power RF envelope detector circuit in CMOS at 2.4 GHz frequency band, and most of them adopted the common source-based envelope detector circuit due to high RF-to-DC conversion characteristic. Because the common source-based envelope detectors provide relatively high input impedance, and their power consumption is around microwatt level or below, their effects on the overall RF performance of the proposed PA can be negligible.   Table 1 summarizes and compares the performances of the proposed reconfigurable PA with previously published reports of PAs for ultra-low power (ULP) radios. The simulated PAE at Psat of the proposed PA under all load conditions (100, 50 and 25 Ω) is higher than seen in previously reported PAs, and is achieved without the use of the on-chip matching network at the output stage. The proposed PA can minimize the degradation of the output power under the worst antenna impedance mismatch conditions, and will become a good candidate for miniaturized high-efficiency PAs for ULP short-range wireless communication systems.   Table 1 summarizes and compares the performances of the proposed reconfigurable PA with previously published reports of PAs for ultra-low power (ULP) radios. The simulated PAE at P sat of the proposed PA under all load conditions (100, 50 and 25 Ω) is higher than seen in previously reported PAs, and is achieved without the use of the on-chip matching network at the output stage. The proposed PA can minimize the degradation of the output power under the worst antenna impedance mismatch conditions, and will become a good candidate for miniaturized high-efficiency PAs for ULP short-range wireless communication systems.