Correction: Balasubramanian, P., et al. Hardware Optimized and Error Reduced Approximate Adder. Electronics 2019, 8, 1212

Balasubramanian, Padmanabhan; L. Maskell, Douglas

doi:10.3390/electronics9020317

Open AccessCorrection

Correction: Balasubramanian, P., et al. Hardware Optimized and Error Reduced Approximate Adder. Electronics 2019, 8, 1212

by

Padmanabhan Balasubramanian

^*

and

Douglas L. Maskell

School of Computer Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798, Singapore

^*

Author to whom correspondence should be addressed.

Electronics 2020, 9(2), 317; https://doi.org/10.3390/electronics9020317

Submission received: 7 February 2020 / Accepted: 8 February 2020 / Published: 12 February 2020

(This article belongs to the Section Circuit and Signal Processing)

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Authors make a change because the modification is required to ensure the accuracy of a result. An advertent typo appears in Table 3, corresponding to LOAWA, where the first value mentioned should be –3.75 (and not –0.375 as it appears now).

The authors wish to make the following corrections to their published paper. In summary, on page 11, Table 3 should be changed from

to the following correct version:

The authors would like to apologize for any inconvenience caused to the readers by these changes. The changes do not affect the scientific results reported in Tables 1 and 2 and Figures 2 and 3. The manuscript will be updated and the original will remain online on the article webpage, with a reference to this Correction.

Reference

Balasubramanian, P.; Maskell, D.L. Hardware Optimized and Error Reduced Approximate Adder. Electronics 2019, 8, 1212. [Google Scholar] [CrossRef] [Green Version]

Table 3. Error metrics of the approximate adders shown in Figure 1b–g. Average error (AE), mean average error (MAE), and root mean square error (RMSE) were calculated by considering a 4-bit and an 8-bit inaccurate sub-adder (i.e., K = 4 and K = 8) in the approximate adders. The generalized error range of the approximate adders using a K-bit inaccurate sub-adder is also specified.

Type of Adder	Error Characteristics
	AE		MAE		RMSE		Error Range
	K = 4	K = 8	K = 4	K = 8	K = 4	K = 8	Error Range
Accurate	Nil		Nil		Nil		Nil
LOA	0.25	0.25	2.875	47.875	4	64	– (2^K–1–1) to 2^K–1
LOAWA	–0.375	–63.75	3.75	63.75	5.477	90.33	– (2^K–1) to 0
APPROX5	0.5	0.5	4	64	4.637	73.9	– (2^K–1–1) to 2^K–1
HEAA	–1.75	–31.75	1.75	31.75	2.646	45.08	– (2^K–1–1) to 0
OLOCA	1	16	3.203	51.997	4.301	69.13	– (2^K–1–1) to (2^K–1+2^K–2–1)
HOERAA	–0.5	–8	1.938	31.996	2.550	41.31	– (2^K–1–1) to (2^K–1–1)

Table 3. Error metrics of the approximate adders shown in Figure 1b to 1g. Average error (AE), mean average error (MAE), and root mean square error (RMSE) were calculated by considering a 4-bit and an 8-bit inaccurate sub-adder (i.e., K = 4 and K = 8) in the approximate adders. The generalized error range of the approximate adders using a K-bit inaccurate sub-adder is also specified.

Type of Adder	Error Characteristics
	AE		MAE		RMSE		Error Range
	K = 4	K = 8	K = 4	K = 8	K = 4	K = 8	Error Range
Accurate	Nil		Nil		Nil		Nil
LOA	0.25	0.25	2.875	47.875	4	64	– (2^K–1–1) to 2^K–1
LOAWA	–3.75	–63.75	3.75	63.75	5.477	90.33	– (2^K–1) to 0
APPROX5	0.5	0.5	4	64	4.637	73.9	– (2^K–1–1) to 2^K–1
HEAA	–1.75	–31.75	1.75	31.75	2.646	45.08	– (2^K–1–1) to 0
OLOCA	1	16	3.203	51.997	4.301	69.13	– (2^K–1–1) to (2^K–1+2^K–2–1)
HOERAA	–0.5	–8	1.938	31.996	2.550	41.31	– (2^K–1–1) to (2^K–1–1)

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MDPI and ACS Style

Balasubramanian, P.; L. Maskell, D. Correction: Balasubramanian, P., et al. Hardware Optimized and Error Reduced Approximate Adder. Electronics 2019, 8, 1212. Electronics 2020, 9, 317. https://doi.org/10.3390/electronics9020317

AMA Style

Balasubramanian P, L. Maskell D. Correction: Balasubramanian, P., et al. Hardware Optimized and Error Reduced Approximate Adder. Electronics 2019, 8, 1212. Electronics. 2020; 9(2):317. https://doi.org/10.3390/electronics9020317

Chicago/Turabian Style

Balasubramanian, Padmanabhan, and Douglas L. Maskell. 2020. "Correction: Balasubramanian, P., et al. Hardware Optimized and Error Reduced Approximate Adder. Electronics 2019, 8, 1212" Electronics 9, no. 2: 317. https://doi.org/10.3390/electronics9020317

APA Style

Balasubramanian, P., & L. Maskell, D. (2020). Correction: Balasubramanian, P., et al. Hardware Optimized and Error Reduced Approximate Adder. Electronics 2019, 8, 1212. Electronics, 9(2), 317. https://doi.org/10.3390/electronics9020317

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Correction: Balasubramanian, P., et al. Hardware Optimized and Error Reduced Approximate Adder. Electronics 2019, 8, 1212

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