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High-Performance Time Server Core for FPGA System-on-Chip

Electronics Technology Department, E.T.S. Ingeniería Informática, University of Seville, Avda. Reina Mercedes s/n, 41012 Seville, Spain
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Electronics 2019, 8(5), 528; https://doi.org/10.3390/electronics8050528
Received: 11 April 2019 / Revised: 3 May 2019 / Accepted: 7 May 2019 / Published: 11 May 2019
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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Abstract

This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions. View Full-Text
Keywords: system-on-chip; digital integrated circuits; field programmable gate array; network time synchronization; network time protocol; hardware timestamping; Internet of Things system-on-chip; digital integrated circuits; field programmable gate array; network time synchronization; network time protocol; hardware timestamping; Internet of Things
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Viejo, J.; Juan-Chico, J.; Bellido, M.; Ruiz-de-Clavijo, P.; Guerrero, D.; Ostua, E.; Cano, G. High-Performance Time Server Core for FPGA System-on-Chip. Electronics 2019, 8, 528.

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