High-Performance Time Server Core for FPGA System-on-Chip
AbstractThis paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions. View Full-Text
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Viejo, J.; Juan-Chico, J.; Bellido, M.; Ruiz-de-Clavijo, P.; Guerrero, D.; Ostua, E.; Cano, G. High-Performance Time Server Core for FPGA System-on-Chip. Electronics 2019, 8, 528.
Viejo J, Juan-Chico J, Bellido M, Ruiz-de-Clavijo P, Guerrero D, Ostua E, Cano G. High-Performance Time Server Core for FPGA System-on-Chip. Electronics. 2019; 8(5):528.Chicago/Turabian Style
Viejo, Julian; Juan-Chico, Jorge; Bellido, Manuel J.; Ruiz-de-Clavijo, Paulino; Guerrero, David; Ostua, Enrique; Cano, German. 2019. "High-Performance Time Server Core for FPGA System-on-Chip." Electronics 8, no. 5: 528.
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