Viejo, J.;                     Juan-Chico, J.;                     Bellido, M.;                     Ruiz-de-Clavijo, P.;                     Guerrero, D.;                     Ostua, E.;                     Cano, G.    
        High-Performance Time Server Core for FPGA System-on-Chip. Electronics 2019, 8, 528.
    https://doi.org/10.3390/electronics8050528
    AMA Style
    
                                Viejo J,                                 Juan-Chico J,                                 Bellido M,                                 Ruiz-de-Clavijo P,                                 Guerrero D,                                 Ostua E,                                 Cano G.        
                High-Performance Time Server Core for FPGA System-on-Chip. Electronics. 2019; 8(5):528.
        https://doi.org/10.3390/electronics8050528
    
    Chicago/Turabian Style
    
                                Viejo, Julian,                                 Jorge Juan-Chico,                                 Manuel J. Bellido,                                 Paulino Ruiz-de-Clavijo,                                 David Guerrero,                                 Enrique Ostua,                                 and German Cano.        
                2019. "High-Performance Time Server Core for FPGA System-on-Chip" Electronics 8, no. 5: 528.
        https://doi.org/10.3390/electronics8050528
    
    APA Style
    
                                Viejo, J.,                                 Juan-Chico, J.,                                 Bellido, M.,                                 Ruiz-de-Clavijo, P.,                                 Guerrero, D.,                                 Ostua, E.,                                 & Cano, G.        
        
        (2019). High-Performance Time Server Core for FPGA System-on-Chip. Electronics, 8(5), 528.
        https://doi.org/10.3390/electronics8050528