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Electronics
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21 November 2019

Induction Motor Drives Fed by an NPC Inverter with Unbalanced DC-Link

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1
DIEI M. Scarano, University of Cassino and Southern Lazio, 03043 Cassino, Italy
2
DIETI, University of Naples Federico II, 80125 Naples, Italy
3
Center for Automotive Research, The Ohio State University, Columbus, OH 43212, USA
*
Author to whom correspondence should be addressed.
This article belongs to the Section Power Electronics

Abstract

Neutral Point Clamped (NPC) converters with n levels are traditionally controlled in such a way that the DC-link capacitors operate at 1/(n − 1) of the total DC-link voltage level. The voltage level across the DC-link capacitors has to be properly regulated by the capacitor unbalance control to contain the harmonic distortion of the converter output voltages. State-of-the-art modulation techniques address the problem of the DC-link voltage regulation for NPC inverters. However, they highly show reduced performance when unbalanced DC-link voltages are considered. In this paper, a novel Space Vector Modulation (SVM) is proposed for NPC converters with an unbalanced DC-link. At every modulation interval, the technique defines the optimal switching pattern by considering the actual unbalanced DC-link conditions. The proposed modulation allows improving the harmonic content of the NPC converter output voltage with respect to a traditional ML-SVM, when the same operating conditions are considered. As an extension, the proposed modulation technique will guarantee the same output voltage quality of a traditional ML-SVM with unbalanced DC-link, while improving the conversion efficiency thanks to a reduction of switching frequency.

1. Introduction

The widespread adoption of Voltage Source Inverters (VSIs) has pushed research forward in the development of new power converter topologies and modulation techniques, which take into account the non-linear behavior of power semiconductors and components with the aim of improving the performance of the whole power conversion system [1,2,3]. In medium- and high-power applications, Neutral Point Clamped (NPC) inverters [4] are prevailing over conventional two-level VSIs, thanks to their high performance, such as reduced stress on semiconductors, less switching losses, lower Electromagnetic Interference (EMI), and improved harmonic content thanks to the n levels of the output voltage waveform. A NPC inverter with n levels takes its name from the typical structure of the DC-link bus, composed by n 1 capacitors forming several Neutral Points (NPs). To maximize the performance of this architecture, the voltages of the n 1 capacitors must be controlled to be equal to 1/( n 1 ) of the total DC-link voltage.
The main issue for this kind of power converter is the low-frequency oscillation of the NPs’ voltage due to current paths that can involve them. The balancing of NPs voltages is usually achieved by adjusting the application duration of the redundant vectors when Space Vector Modulation (SVM) or carrier-based PWM (CBPWM) with the zero-sequence component injection are adopted [5,6,7,8,9,10,11]. However, these modulation techniques do not completely allow to overcome the problem of the voltage fluctuation of the NPs as described in [12]. In fact, some output voltage space vectors introduce an unbalanced between the capacitors’ voltages that cannot be compensated using the vectors redundancies, especially for high modulation indexes and low power factors, [5]. Therefore, low harmonic content of the output voltages can be guaranteed with a traditional multilevel SVM (ML-SVM) [13] or CBPWM if the capacitors’ voltages are balanced and have a low ripple. This is usually achieved increasing the switching frequency causing higher losses, especially in high power density applications with small DC-link capacitors, [2]. NPC topology is also gaining attention in some application fields characterized by the need of independently regulating several DC-link voltages. In photovoltaic (PV) generation systems, the Maximum Power Point Tracking (MPPT) algorithm can be independently implemented on series-connected PV strings with related DC-link capacitors with the aim of increasing the power extractions from the PV panels [14,15]. In these cases, the unbalanced DC-link reduces the performance of traditional SVM for NPC converter.
To address the distorted output voltage and current due to unbalanced DC-link, several modulation techniques have been developed for 3 levels (3L)-NPC converter based on CBPWM with appropriate zero-sequence component injection or modified SVM [16,17,18,19]. The SVM presented in [16] is based on a complex space vector diagram causing time-consuming calculation of the duty cycles. The approach of zero-sequence presents some complications for the generalization and the implementation of the modulation strategy [17]. New and interesting approaches are proposed in [18,19] aiming at implementing a fast-processing method to calculate the duty cycles on the basis of virtual output voltage space vectors.
The authors propose an analytic approach for the development of a novel SVM that has the aim to reduce the harmonic content of the output voltage of a 3L-NPC converter for a given unbalanced DC-link condition. The proposed SVM considers the time-variant voltage unbalance across the DC-link capacitors during the modulation period in order to calculate the duty cycles of the real output voltage space vector [20]. In detail, starting from a mathematical model of the 3L-NPC inverter with unbalanced DC-link, the proposed model-base solution allows calculating the vectors duration independently from the load parameters.
In this paper, performance analysis of the proposed modulation technique is presented for a 3L-NPC inverter feeding an induction motor. Section 2 reports the mathematical model of the NPC when an unbalanced DC-link is considered. Section 3 describes the proposed modulation technique, while Section 4 and Section 5 analyzes the validity of the proposed techniques through numerical and experimental results when compared to traditional SVM.

4. Numerical Results

To validate the proposed SVM technique, a numerical model of the three-phase 3L-NPC converter feeding a 1.1-kW induction motor has been developed in MATLAB-Simulink environment. The parameters of the electrical drive are shown in Table 2. The V/f motor control and the modulation technique have been modeled using a S-function to facilitate the experimental implementation on a DSP-based control unit. The sampling time and control delays of the experimental setup (Section 5) have been considered for the numerical implementation with the aim of achieving an accurate comparison between numerical and experimental results.
Table 2. Parameters of the electrical drive.
The capacitor unbalanced control is based on a hysteresis algorithm that selects the proper redundant vector [2] at every modulation interval T s in order of keeping the capacitors’ voltages within an desired Δ V . The proposed modulation technique based on Equation (22) is simulated considering a balanced capacitors’ voltages reference v C 1 * = v C 2 * = 200 V. Δ V , the switching frequency f sw , and load torque T l are respectively set to 5 % · V dc , 2 kHz, and 3.5 Nm. The performance of proposed SVM are compared with the ones of a traditional SVM proposed in [13] in terms of current Total Harmonic Distortion T H D i with the same unbalanced DC-link conditions, for different values of the modulation index ( m = 3 | v ^ | ( r ) / V dc , where | v ^ | ( r ) represents the peak value of the reference voltage space vector). Figure 4 and Figure 5 respectively show the motor currents for the traditional SVM and the proposed one when a low value of the modulation index is requested by the motor feeding algorithm (m = 0.27). In Figure 6, it is possible to notice how the DC-link capacitors’ voltage references are tracked by means of the DC-link balance control for both the modulation techniques. Under the same unbalanced DC-link condition, the traditional SVM cannot accurately synthesize the reference voltage space vector due to the unbalanced DC-link operation at the beginning and during every modulation period. Instead, the proposed SVM allows taking into account the unbalanced voltages by means of Equation (22), independently of the load condition. This leads to a considerable improvement in the quality of the motor currents. The proposed SVM strategy allows reducing T H D i with respect to the traditional modulation by 41.7% in the considered conditions. The performance improvement is also confirmed for a higher value of modulation index (m = 0.94). Current waveforms of the traditional and the proposed modulations are respectively depicted in Figure 7 and Figure 8. In this case, the reduction of the T H D i value is equal to 34.7%, when the same voltage ripple across the DC-link capacitors is imposed for the traditional and the proposed SVM as shown in the Figure 9. The reduction of T H D i for different values of the modulation index is reported in Figure 10. The proposed SVM allows improving the performance within the whole interval of the modulation index variation.
Figure 4. Numerical result: motor currents achieved with the traditional SVM, when m = 0.27, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 5. Numerical result: motor currents achieved with the proposed SVM based on Equation (22), when m = 0.27, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 6. Numerical result: capacitors voltages for the traditional SVM (upper trace) and proposed one (lower trace), when m = 0.27, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 7. Numerical result: motor currents achieved with the traditional SVM, when m = 0.94, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 8. Numerical result: motor currents achieved with the proposed SVM based on Equation (22), when m = 0.94, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 9. Numerical result: capacitors voltages for the traditional SVM (upper trace) and proposed one (lower trace), when m = 0.94, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 10. Reduction of the T H D i achieved by means of the proposed modulation technique with respect to the traditional for different values of the modulation index, m.

5. Experimental Results

A full-scale prototype of the 3L-NPC power converter has been designed and manufactured. Every leg of the converter is composed by IGBT module SEMIKRON® SK50MLI066. A picture of the power converter is shown in Figure 11. The experimental control unit consists of DS1006 processor board of a dSPACE® modular system and of an ALTERA FPGA Cyclone III. DS4003 digital I/O board interfaces the two units, which are synchronized by means of an interrupt signal generated by the FPGA board. The synchronizing signal has a period T s of 500 μs. In detail, the processor unit performs the motor control algorithm and works out the duration and the modulation patterns at every modulation period, which must be imposed in the next T s , according with the Equation (22) or with traditional SVM [13]. Starting from them, the FPGA unit generates the switching signals with proper dead-time, set equal to 4 μs. The DS2004 board is used to acquire the analog signals from DC-link voltage sensors. The test bench is completed by a 1.1-kW induction motor coupled to a dynamic controllable brake. The main parameters of the test bench are shown in Table 2. To compare the experimental and numerical results, the same tests proposed in Section 4 have been performed. Figure 12 shows the motor currents achieved with the traditional SVM considering the same voltage references of DC-link capacitors ( v C 1 * = v C 2 * = 200 V), m = 0.27 and the constant load torque T l = 3.5 Nm. Results achieved with the proposed modulation technique are shown in Figure 13. The improvement in terms of T H D i is comparable with the one achieved in the numerical analysis. The proposed SVM allows achieving a T H D i reduction of 39.2%. In detail, the T H D i decreases from to 11.3%, traditional SVM, up to 6.86% for the proposed solution. Figure 14 shows the capacitor voltage during the test. The experimental results for m = 0.94 are reported in Figure 15, Figure 16 and Figure 17. As it is possible to notice, the proposed modulation technique considerably improves the motor current quality for high values of the modulation index as well. In detail, a reduction of the T H D i equal to 27.7% is achieved with the proposed solution.
Figure 11. Picture of the three-level NPC inverter prototype.
Figure 12. Experimental result: motor currents achieved with the traditional SVM, when m = 0.27, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 13. Experimental result: motor currents achieved with the proposed SVM based on Equation (22), when m = 0.27, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 14. Experimental result: capacitors voltages for the traditional SVM (upper trace) and proposed one (lower trace), when m = 0.27, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 15. Experimental result: motor currents achieved with the traditional SVM, when m = 0.94, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 16. Experimental result: motor currents achieved with the proposed SVM based on Equation (22), when m = 0.94, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.
Figure 17. Experimental result: capacitors voltages for the traditional SVM (upper trace) and proposed one (lower trace), when m = 0.94, v C 1 * = v C 2 * = 200 V, and T l = 3.5 Nm.

6. Conclusions

In this paper, a new SVM modulation strategy for a 3L-NPC inverter feeding an induction motor is proposed. It allows improving performances of motor control in terms of reduction of the currents THD thanks to a correct evaluation of the real voltage evolution across DC-link capacitors during unbalanced conditions.The proposed modulation technique does not depend from the specific load parameters and it has a compact and simple formulation structure. This last feature allows achieving low computational cost in the practical implementation. Numerical and experimental results confirm the validity of the proposed SVM strategy in different operating conditions.

Author Contributions

All the authors have equally contributed to this work. Writing—original draft, U.A., C.A., M.D., M.D.M. and G.T.

Funding

This research received no external funding.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Abronzini, U.; Attaianese, C.; D’Arpino, M.; Monaco, M.D.; Tomasso, G. Steady-State Dead-Time Compensation in VSI. IEEE Trans. Ind. Electron. 2016, 63, 5858–5866. [Google Scholar] [CrossRef]
  2. Attaianese, C.; Monaco, M.D.; Tomasso, G. High Performance Digital Hysteresis Control for Single Source Cascaded Inverters. IEEE Trans. Ind. Inform. 2013, 9, 620–629. [Google Scholar] [CrossRef]
  3. Attaianese, C.; Monaco, M.D.; Tomasso, G. Power Control for Fuel-Cell-Supercapacitor Traction Drive. IEEE Trans. Veh. Technol. 2012, 61, 1961–1971. [Google Scholar] [CrossRef]
  4. Nabae, A.; Takahashi, I.; Akagi, H. A new neutral-point-clamped PWM inverter. IEEE Trans. Ind. Appl. 1981, IA-17, 518–523. [Google Scholar] [CrossRef]
  5. Celanovic, N.; Borojevic, D. A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters. In Proceedings of the APEC’99, Fourteenth Annual Applied Power Electronics Conference and Exposition, 1999 Conference Proceedings (Cat. No. 99CH36285), Dallas, TX, USA, 14–18 March 1999; Volume 1, pp. 535–541. [Google Scholar]
  6. Chen, W.; Sun, H.; Gu, X.; Xia, C. Synchronized space-vector PWM for three-level VSI with lower harmonic distortion and switching frequency. IEEE Trans. Power Electron. 2015, 31, 6428–6441. [Google Scholar] [CrossRef]
  7. Lyu, J.; Hu, W.; Wu, F.; Yao, K.; Wu, J. Three-level saddle space vector pulse width modulation strategy based on two-level space vector pulse width modulation for neutral-point-clamped three-level inverters. IET Power Electron. 2016, 9, 874–882. [Google Scholar] [CrossRef]
  8. Jiao, Y.; Lee, F.C.; Lu, S. Space vector modulation for three-level NPC converter with neutral point voltage balance and switching loss reduction. IEEE Trans. Power Electron. 2013, 29, 5579–5591. [Google Scholar] [CrossRef]
  9. Choudhury, A.; Pillay, P.; Williamson, S.S. Modified DC-Bus Voltage-Balancing Algorithm Based Three-Level Neutral-Point-Clamped IPMSM Drive for Electric Vehicle Applications. IEEE Trans. Ind. Electron. 2016, 63, 761–772. [Google Scholar] [CrossRef]
  10. Pou, J.; Zaragoza, J.; Ceballos, S.; Saeedifard, M.; Boroyevich, D. A carrier-based PWM strategy with zero-sequence voltage injection for a three-level neutral-point-clamped converter. IEEE Trans. Power Electron. 2010, 27, 642–651. [Google Scholar] [CrossRef]
  11. Zhang, Y.; Li, J.; Li, X.; Cao, Y.; Sumner, M.; Xia, C. A method for the suppression of fluctuations in the neutral-point potential of a three-level NPC inverter with a capacitor-voltage loop. IEEE Trans. Power Electron. 2016, 32, 825–836. [Google Scholar] [CrossRef]
  12. Busquets-Monge, S.; Bordonau, J.; Boroyevich, D.; Somavilla, S. The nearest three virtual space vector PWM—A modulation for the comprehensive neutral-point balancing in the three-level NPC inverter. IEEE Power Electron. Lett. 2004, 2, 11–15. [Google Scholar] [CrossRef]
  13. Celanovic, N.; Boroyevich, D. A fast space-vector modulation algorithm for multilevel three-phase converters. IEEE Trans. Ind. Appl. 2001, 37, 637–641. [Google Scholar] [CrossRef]
  14. Patrao, I.; Garcera, G.; Figueres, E.; Gonzalez-Medina, R. Grid-tie inverter topology with maximum power extraction from two photovoltaic arrays. IET Renew. Power Gener. 2014, 8, 638–648. [Google Scholar] [CrossRef]
  15. Andrade, A.S.; da Silva, E.R.C. DC-link control of a three-level NPC inverter fed by shaded photovoltaic system. In Proceedings of the IEEE 13th Brazilian Power Electronics Conference and 1st Southern Power Electronics Conference (COBEP/SPEC), Fortaleza, Brazil, 29 November–2 December 2015. [Google Scholar]
  16. Pou, J.; Boroyevich, D.; Pindado, R. New feedforward space-vector PWM method to obtain balanced AC output voltages in a three-level neutral-point-clamped converter. IEEE Trans. Ind. Electron. 2002, 49, 1026–1034. [Google Scholar] [CrossRef]
  17. Wu, X.; Xie, L.; Yin, J.; Ton, Y.; Yang, J. A three-level PV inverter with independent MPPT control for two sets of photovoltaic cells in series connection. Trans. China Electrotech. Soc. 2013, 28, 202–208. [Google Scholar]
  18. Wu, X.; Tan, G.; Ye, Z.; Yao, G.; Liu, Z.; Liu, G. Virtual-Space-Vector PWM for a Three-Level Neutral-Point-Clamped Inverter with Unbalanced DC-Links. IEEE Trans. Power Electron. 2018, 33, 2630–2642. [Google Scholar] [CrossRef]
  19. Ye, Z.; Xu, Y.; Wu, X.; Tan, G.; Deng, X.; Wang, Z. A Simplified PWM Strategy for a Neutral-Point-Clamped (NPC) Three-Level Converter with Unbalanced DC Links. IEEE Trans. Power Electron. 2016, 31, 3227–3238. [Google Scholar] [CrossRef]
  20. Abronzini, U.; Attaianese, C.; Di Monaco, M.; Tomasso, G.; D’Arpino, M. SVM of Three-Level NPC Inverter with Unbalanced DC-Link. In Proceedings of the 2018 IEEE Energy Conversion Congress and Exposition (ECCE), Portland, OR, USA, 23–27 September 2018; pp. 2215–2221. [Google Scholar] [CrossRef]
  21. Bose, B.K. Power Electronics and AC Drives; Prentice-Hall: Englewood Cliffs, NJ, USA, 1986; 416p. [Google Scholar]

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