Induction Motor Drives Fed by an NPC Inverter with Unbalanced DC-Link

Neutral Point Clamped (NPC) converters with n levels are traditionally controlled in such a way that the DC-link capacitors operate at 1/(n−1) of the total DC-link voltage level. The voltage level across the DC-link capacitors has to be properly regulated by the capacitor unbalance control to contain the harmonic distortion of the converter output voltages. State-of-the-art modulation techniques address the problem of the DC-link voltage regulation for NPC inverters. However, they highly show reduced performance when unbalanced DC-link voltages are considered. In this paper, a novel Space Vector Modulation (SVM) is proposed for NPC converters with an unbalanced DC-link. At every modulation interval, the technique defines the optimal switching pattern by considering the actual unbalanced DC-link conditions. The proposed modulation allows improving the harmonic content of the NPC converter output voltage with respect to a traditional ML-SVM, when the same operating conditions are considered. As an extension, the proposed modulation technique will guarantee the same output voltage quality of a traditional ML-SVM with unbalanced DC-link, while improving the conversion efficiency thanks to a reduction of switching frequency.


Introduction
The widespread adoption of Voltage Source Inverters (VSIs) has pushed research forward in the development of new power converter topologies and modulation techniques, which take into account the non-linear behavior of power semiconductors and components with the aim of improving the performance of the whole power conversion system [1][2][3]. In medium-and high-power applications, Neutral Point Clamped (NPC) inverters [4] are prevailing over conventional two-level VSIs, thanks to their high performance, such as reduced stress on semiconductors, less switching losses, lower Electromagnetic Interference (EMI), and improved harmonic content thanks to the n levels of the output voltage waveform. A NPC inverter with n levels takes its name from the typical structure of the DC-link bus, composed by n−1 capacitors forming several Neutral Points (NPs). To maximize the performance of this architecture, the voltages of the n−1 capacitors must be controlled to be equal to 1/(n−1) of the total DC-link voltage.
The main issue for this kind of power converter is the low-frequency oscillation of the NPs' voltage due to current paths that can involve them. The balancing of NPs voltages is usually achieved by adjusting the application duration of the redundant vectors when Space Vector Modulation (SVM) or carrier-based PWM (CBPWM) with the zero-sequence component injection are adopted [5][6][7][8][9][10][11]. However, these modulation techniques do not completely allow to overcome the problem of the voltage fluctuation of the NPs as described in [12]. In fact, some output voltage space vectors introduce an unbalanced between the capacitors' voltages that cannot be compensated using the vectors redundancies, especially for high modulation indexes and low power factors, [5]. Therefore, low harmonic content of the output voltages can be guaranteed with a traditional multilevel SVM (ML-SVM) [13] or CBPWM if the capacitors' voltages are balanced and have a low ripple. This is usually achieved increasing the switching frequency causing higher losses, especially in high power density applications with small DC-link capacitors, [2]. NPC topology is also gaining attention in some application fields characterized by the need of independently regulating several DC-link voltages. In photovoltaic (PV) generation systems, the Maximum Power Point Tracking (MPPT) algorithm can be independently implemented on series-connected PV strings with related DC-link capacitors with the aim of increasing the power extractions from the PV panels [14,15]. In these cases, the unbalanced DC-link reduces the performance of traditional SVM for NPC converter.
To address the distorted output voltage and current due to unbalanced DC-link, several modulation techniques have been developed for 3 levels (3L)-NPC converter based on CBPWM with appropriate zero-sequence component injection or modified SVM [16][17][18][19]. The SVM presented in [16] is based on a complex space vector diagram causing time-consuming calculation of the duty cycles. The approach of zero-sequence presents some complications for the generalization and the implementation of the modulation strategy [17]. New and interesting approaches are proposed in [18,19] aiming at implementing a fast-processing method to calculate the duty cycles on the basis of virtual output voltage space vectors.
The authors propose an analytic approach for the development of a novel SVM that has the aim to reduce the harmonic content of the output voltage of a 3L-NPC converter for a given unbalanced DC-link condition. The proposed SVM considers the time-variant voltage unbalance across the DC-link capacitors during the modulation period in order to calculate the duty cycles of the real output voltage space vector [20]. In detail, starting from a mathematical model of the 3L-NPC inverter with unbalanced DC-link, the proposed model-base solution allows calculating the vectors duration independently from the load parameters.
In this paper, performance analysis of the proposed modulation technique is presented for a 3L-NPC inverter feeding an induction motor. Section 2 reports the mathematical model of the NPC when an unbalanced DC-link is considered. Section 3 describes the proposed modulation technique, while Sections 4 and 5 analyzes the validity of the proposed techniques through numerical and experimental results when compared to traditional SVM. Figure 1 shows the electric circuit of a three-phase 3L-NPC inverter. The space vector of the inverter output voltage v is:

Model of the NPC Inverter with Unbalanced DC-Link
where j represents the unit imaginary number, v xo is the output voltage of the generic x-th leg with x ∈ {a, b, c}. Table 1 reports v xo for the three possible switching states of the x-th leg defined by means of the state variable δ x . S ix , with i ∈ {1, 2, 3, 4}, are Boolean quantities representing the state of the power switches of the x-th leg. For 3L-NPC inverter with unbalanced DC-link, the voltages across the capacitors are function of the voltage unbalance (∆V) between the capacitors as follows: Thus, the output voltage of the x-th leg can be expressed combining Table 1 and Equation (2): The expression of the space vector of the output voltage in unbalanced condition can be written by subsisting Equation (3) into Equation (1) as: For a generic switching pattern k, defined by the set {δ a , δ b , δ c }, the space vector v k of the inverter output voltages can be expressed as follows: where v * k represents the voltage space vector corresponding to balanced DC-link, while ∆V k is the unbalanced voltage corresponding to the switching pattern k, and where γ k is given by: Figure 2 shows the 19 output voltage space vectors of the 3L-NPC inverter in case of balanced DC-link [20]. They can be classified on the basis of their magnitude in zero |v The small vectors can be achieved using two different switching patterns. This redundancy are used to control the DC-link capacitor voltages. The unbalance DC-link condition affects just the small and medium vectors. With reference to the unbalanced condition of the Figure 3 (∆V = − 1 6 V dc ), medium vectors change their magnitude and phases because γ k is perpendicular to v k . These variations determine the displacement of the vectors along the perimeter of the 2 3 V dc hexagon towards one of the two adjacent large vectors depending on the sign of the voltage unbalance ∆V, as shown by the green vectors of Figure 3. Small vectors change only their magnitude because γ k has the same direction of v k . Therefore, the small vectors lose the redundancy in unbalanced DC-link condition becoming twelve distinct vectors, which are depicted in orange and blue in Figure 3.   The neutral point current i o can be calculated by the following equation:

Switching State Output Voltage
where i is the space vector of the inverter output current defined by: It is always true that: thus, the following relation can be yield: By considering the Equation (7), the following equation can be obtained: Therefore, the integration of Equation (10) allows determining the ∆V evolution during the switching pattern k as it will be shown in the following section.

SVM with Unbalanced DC-Link
Traditional SVM for 3L-NPC inverter is based on the hexagon of Figure 2 [13]. If voltage unbalance occurs between the DC-link capacitors, traditional SVM cannot guarantee that, within each modulation period, the space vector of the inverter output voltage matches the reference one. Furthermore, the waveforms of the output voltages have an increased harmonic content.
In this paper, this issue is addressed by means of a novel SVM technique that considers the "true" displacement of the voltage space vectors in unbalanced DC-link condition. Thus, it does not consider only the voltage unbalance at the beginning of the modulation period (∆V(0)), but the whole time evolution of ∆V(t) as function of the switching pattern k.
In order to evaluate the function ∆V k (t), corresponding to the voltage space vector v k , a RL symmetric load is assumed. Under this hypothesis, the inverter output current space vector i k can be calculated as following: Since v * k is constant during the modulation interval k, Equation (12) yields the following: (13) By substituting the current space vector expression into Equation (10), the following equation can be obtained: The derivation of the Equation (14) leads to the following second-order differential equation: By imposing the equivalence of integral terms of the Equations (14) and (15), it yields: The differential Equation (16) can be solved by defining the analytical expression of the function ∆V k (t) within the time interval in which the voltage space vector v * k is applied. Considering that for a medium and small vector |γ k | = 1, while for a large vector |γ k | = 0; the following relations can be yield: where If v (r) is the reference voltage space vector to be achieved during the modulation period T s by means of the SVM switching pattern k, h, i, it yields: (20) where the functions ∆V k (t), ∆V h (t), ∆V i (t) are evaluated by means of (17)- (19). In detail, the voltage unbalance is calculated by Equation (17) considering the value of |γ k | for every switching pattern.
To calculate the coefficients of Equations (18) and (19), the initial voltage and current conditions of every switching patter are imposed equal to the final values achieved at the end of the application of the previous switching patter. Once ∆V k (t), ∆V h (t), ∆V i (t) function have been determined, α k , α h , α i can be calculated by means of the Equation (20) and by imposing Equation (20) is a transcendental equation, and therefore its solution has to be found numerically by means of a root-find algorithm which could require high computational power, limiting the real world implementation of the proposed methodology. Approximating the exponential terms by the first-degree Maclaurin's polynomials, the following closed-form can be used to calculate the values of where ∆V k (0) represents the only needed initial condition, which is the measured voltage unbalance at the beginning of the first switching patter of the modulation period. It has to be underlined that the proposed closed-form solution is independent of the load parameters. Thus, in this paper it is proposed the application of this modulation technique to an electrical drive, in which the 3L-NPC feeds an induction motor controlled by the traditional open-loop V/f technique [21]. This choice is justified by the need of properly assessing the performance of the proposed and traditional modulation technique without the impact of the closed-loop control. As example, a Field Oriented Control (FOC) with traditional ML-SVM is controlling a 3L-NPC inverter feeding an induction machine. Due to the unbalanced DC-link voltages, the desired output voltage of the FOC cannot be respected by the SVM causing a torque/speed deviation. At the next sampling interval the the FOC's PI controllers will try to compensate the torque/speed error by defining a new reference voltage affected by the SVM error. Thus the reference voltage defined by the FOC will be affected by the performance of the modualtion technique and the parameters of the PI controllers. This effect will limit the capability of the authors to properly compare the performance of different modulation technique, thus a V/f control is selected.

Numerical Results
To validate the proposed SVM technique, a numerical model of the three-phase 3L-NPC converter feeding a 1.1-kW induction motor has been developed in MATLAB-Simulink environment. The parameters of the electrical drive are shown in Table 2. The V/f motor control and the modulation technique have been modeled using a S-function to facilitate the experimental implementation on a DSP-based control unit. The sampling time and control delays of the experimental setup (Section 5) have been considered for the numerical implementation with the aim of achieving an accurate comparison between numerical and experimental results.
The capacitor unbalanced control is based on a hysteresis algorithm that selects the proper redundant vector [2] at every modulation interval T s in order of keeping the capacitors' voltages within an desired ∆V. The proposed modulation technique based on Equation (22) is simulated considering a balanced capacitors' voltages reference v * C 1 = v * C 2 = 200 V. ∆V, the switching frequency f sw , and load torque T l are respectively set to 5% · V dc , 2 kHz, and 3.5 Nm. The performance of proposed SVM are compared with the ones of a traditional SVM proposed in [13] in terms of current Total Harmonic Distortion THD i with the same unbalanced DC-link conditions, for different values of the modulation index (m = √ 3|v| (r) /V dc , where |v| (r) represents the peak value of the reference voltage space vector). Figures 4 and 5 respectively show the motor currents for the traditional SVM and the proposed one when a low value of the modulation index is requested by the motor feeding algorithm (m = 0.27). In Figure 6, it is possible to notice how the DC-link capacitors' voltage references are tracked by means of the DC-link balance control for both the modulation techniques. Under the same unbalanced DC-link condition, the traditional SVM cannot accurately synthesize the reference voltage space vector due to the unbalanced DC-link operation at the beginning and during every modulation period. Instead, the proposed SVM allows taking into account the unbalanced voltages by means of Equation (22), independently of the load condition. This leads to a considerable improvement in the quality of the motor currents. The proposed SVM strategy allows reducing THD i with respect to the traditional modulation by 41.7% in the considered conditions. The performance improvement is also confirmed for a higher value of modulation index (m = 0.94). Current waveforms of the traditional and the proposed modulations are respectively depicted in Figures 7 and 8. In this case, the reduction of the THD i value is equal to 34.7%, when the same voltage ripple across the DC-link capacitors is imposed for the traditional and the proposed SVM as shown in the Figure 9. The reduction of THD i for different values of the modulation index is reported in Figure 10. The proposed SVM allows improving the performance within the whole interval of the modulation index variation.

Experimental Results
A full-scale prototype of the 3L-NPC power converter has been designed and manufactured. Every leg of the converter is composed by IGBT module SEMIKRON R SK50MLI066. A picture of the power converter is shown in Figure 11. The experimental control unit consists of DS1006 processor board of a dSPACE R modular system and of an ALTERA FPGA Cyclone III. DS4003 digital I/O board interfaces the two units, which are synchronized by means of an interrupt signal generated by the FPGA board. The synchronizing signal has a period T s of 500 µs. In detail, the processor unit performs the motor control algorithm and works out the duration and the modulation patterns at every modulation period, which must be imposed in the next T s , according with the Equation (22) or with traditional SVM [13]. Starting from them, the FPGA unit generates the switching signals with proper dead-time, set equal to 4 µs. The DS2004 board is used to acquire the analog signals from DC-link voltage sensors. The test bench is completed by a 1.1-kW induction motor coupled to a dynamic controllable brake. The main parameters of the test bench are shown in Table 2. To compare the experimental and numerical results, the same tests proposed in Section 4 have been performed. Figure 12 shows the motor currents achieved with the traditional SVM considering the same voltage references of DC-link capacitors (v * C 1 = v * C 2 = 200 V), m = 0.27 and the constant load torque T l = 3.5 Nm. Results achieved with the proposed modulation technique are shown in Figure 13. The improvement in terms of THD i is comparable with the one achieved in the numerical analysis. The proposed SVM allows achieving a THD i reduction of 39.2%. In detail, the THD i decreases from to 11.3%, traditional SVM, up to 6.86% for the proposed solution. Figure 14 shows the capacitor voltage during the test. The experimental results for m = 0.94 are reported in Figures 15-17. As it is possible to notice, the proposed modulation technique considerably improves the motor current quality for high values of the modulation index as well. In detail, a reduction of the THD i equal to 27.7% is achieved with the proposed solution.

Conclusions
In this paper, a new SVM modulation strategy for a 3L-NPC inverter feeding an induction motor is proposed. It allows improving performances of motor control in terms of reduction of the currents THD thanks to a correct evaluation of the real voltage evolution across DC-link capacitors during unbalanced conditions.The proposed modulation technique does not depend from the specific load parameters and it has a compact and simple formulation structure. This last feature allows achieving low computational cost in the practical implementation. Numerical and experimental results confirm the validity of the proposed SVM strategy in different operating conditions.

Conflicts of Interest:
The authors declare no conflict of interest.