# A New Rail-to-Rail Second Generation Voltage Conveyor

^{*}

## Abstract

**:**

## 1. Introduction

## 2. VCII Short Review

## 3. The Proposed RtR VCII

_{1}–M

_{7}and the current sources I

_{b1}–I

_{b3}. Transistor M

_{3}in the common-gate configuration is biased by a voltage that is regulated by the negative feedback loop established by M

_{1}–M

_{2}, providing the virtual ground at the Y terminal and further reducing its impedance. The voltage buffer implementation is based on a modified version of the standard class AB voltage follower (see Figure 3a,b) [23]. PMOS M

_{L1}–M

_{L2}and NMOS M

_{H1}–M

_{H2}differential pairs drive a switching circuit that, based on the reference voltages V

_{HIGH}and V

_{LOW}, activate the correct portion of the buffer that is the standard voltage follower M

_{n1}, M

_{n2}, M

_{p1}, M

_{p2}, or the RtR pair M

_{H7}and M

_{L7}. The working principle is explained in depth in [23].

_{8}and I

_{b3}fix the voltage at the drain of M

_{6}. Then, it is possible to choose the gate voltage of M

_{8}(V

_{bias}) to accurately tune the bias current of the Y and therefore the X terminals. Capacitors C

_{1}and C

_{2}are used to dampen the α parameter transfer function, ensuring the stability of the system. The impedances are derived using the small signal equivalent model depicted in Figure 5. The impedance at the Y terminal is given by:

_{4}–M

_{7}have the task of copying the input current (at Y) to the X terminal. Since the current flowing at Y is mirrored on the class AB-biased branch formed M

_{5}and M

_{7}, the voltage swing allowed at the X terminal is very wid, even for high currents. Precisely, it is given by:

_{k1}and R

_{k2}are equal to $\left(g{m}_{Mn2}Rd{s}_{Mn2}Rd{s}_{Mp3}//Rd{s}_{MH5}\right)$ and $\left(g{m}_{Mp2}Rd{s}_{Mp2}Rd{s}_{Mn3}//Rd{s}_{ML5}\right),$ respectively.

## 4. Simulation Results

_{HIGH}and V

_{LOW}at the differential amplifiers of the voltage buffer stage were set to +0.3 V and −0.35 V, respectively, while supply voltages were ±0.9 V. The voltage V

_{bias}was set to −0.3 V in order to ensure a 10 µA bias current through the Y and X branches. M

_{b}dimensions were regulated so as to have 10 µA flowing through M

_{p3}and M

_{n3}. In order to guarantee a high driving capability for the X node, the W/L ratio of M

_{4}–M

_{5}and M

_{6}–M

_{7}was set to 100 and 200, respectively.

_{in,pp_max}represents the maximum input peak-to-peak voltage that still allows it to achieve acceptable linearity levels and is extracted from the THD evaluations. The parameter, I, expressed in µA, introduces the FOM of the power consumption of the circuit, decoupling it from the actual supply voltage.

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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Transistor | Dimensions (W, L) |

M_{1}, M_{2}, M_{8} | 1.8 µm, 0.3 µm |

M_{3} | 2.4 µm, 0.3 µm |

M_{4}, M_{5}, M_{H7} | 30 µm, 0.3 µm |

M_{6}, M_{7}, M_{L7} | 60 µm, 0.3 µm |

M_{H1}, M_{H2} | 7.2 µm, 0.3 µm |

M_{H3}, M_{H4}, M_{H5}, M_{H6} | 3.6 µm, 0.3 µm |

M_{L1}, M_{L2} | 14.4 µm, 0.3 µm |

M_{L3}, M_{L4}, M_{L5}, M_{L6} | 2.85 µm, 0.9 µm |

M_{p1}, M_{p2} | 8.75 µm, 0.75 µm |

M_{n1}, M_{n2} | 2.85 µm, 0.75 µm |

M_{p3} | 4.5 µm, 0.75 µm |

M_{n3} | 1.35 µm, 0.75 µm |

M_{b} | 0.3 µm, 0.6 µm |

Parameter | Value |

I_{b1}, I_{b2}, I_{b3}, I_{b4}, I_{b5} | 5 µA |

V_{HIGH} | 300 mV |

V_{LOW} | −350 mV |

V_{bias} | −300 mV |

C_{1}, C_{2} | 250 fF |

Parameter | This Work | [14] | [16] | [17,25] | [15,18] |
---|---|---|---|---|---|

Technology | LFoundry 0.15 µm | AMS 0.35 µm | AMS 0.35 µm | TSMC 0.35 µm | AMS 0.35 µm |

Supply voltage | ±0.9 V | ±1.65 V | ±1.65 V | ±1.65 V | ±1.65 V |

Impedance at X node | 522 kΩ (@100 MHz) | 1.2 MΩ | 370 kΩ | 240 kΩ | 802 kΩ |

Impedance at Y node | 23 Ω (@100 MHz) | 6.7 Ω | 2 mΩ | 650 mΩ | 49 mΩ |

Impedance at Z node | 160 Ω (@100 MHz) | 0.7 Ω | 2 mΩ | 1.4 Ω | 79 mΩ |

α | −0.24 dB (@100 kHz) | −0.03 dB | −0.07 dB | 0.32 dB | −0.04 dB |

β | −0.03 dB (@100 kHz) | −0.1 dB | −0.115 dB | −0.04 dB | |

α bandwidth | 55 MHz (1 pF load at Z) | 217 MHz (unloaded) | 220 MHz (unloaded) | 74 MHz | 340 MHz (unloaded) |

β bandwidth | 165 MHz | 200 MHz | 22.4 MHz | 64 MHz | 14 MHz |

V_{Z} THD | 2.4% (−32.4 dB) (V_{X} = 1.6 V_{pp}; @1 MHz; 10 harm) | 0.068% (−63 dB) (V_{X} = 1 V_{pp}; @1 MHz; 10 harm) | 2.48% (V_{X} = 1 V_{pp}; @1 MHz; 10 harm) | 2.7% (V_{X} = 1 V_{pp}) | N.A. |

I_{X} THD | 1.1% (−39 dB) (I_{Y} = 1 mA_{pp}; @1 MHz; 10 harm) | 0.1% (−59 dB) (I_{Y} = 20 µA_{pp}; @1 MHz; 10 harm) | 3.36% (I_{Y} = 1 mA_{pp}; @1 MHz; 10 harm) | N.A. | N.A. |

Static Power Cons. | 120 µW | 330 µW | 320 μW | ≅5 mW | 700 μW |

figure of merit (FOM) | 85 | 330 | 320 | 4950 | 874 |

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## Share and Cite

**MDPI and ACS Style**

Barile, G.; Stornelli, V.; Ferri, G.; Safari, L.; D’Amico, E.
A New Rail-to-Rail Second Generation Voltage Conveyor. *Electronics* **2019**, *8*, 1292.
https://doi.org/10.3390/electronics8111292

**AMA Style**

Barile G, Stornelli V, Ferri G, Safari L, D’Amico E.
A New Rail-to-Rail Second Generation Voltage Conveyor. *Electronics*. 2019; 8(11):1292.
https://doi.org/10.3390/electronics8111292

**Chicago/Turabian Style**

Barile, Gianluca, Vincenzo Stornelli, Giuseppe Ferri, Leila Safari, and Emanuele D’Amico.
2019. "A New Rail-to-Rail Second Generation Voltage Conveyor" *Electronics* 8, no. 11: 1292.
https://doi.org/10.3390/electronics8111292