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Open AccessArticle

Hardware Support to Minimize the End-to-End Delay in Ethernet-Based Ring Networks

Electrical Engineering Graduate Program, Federal University of Minas Gerais, Belo Horizonte 31270-901, Brazil
CISTER, Instituto de Telecomunicações, FEUP-University of Porto, 4200-465 Porto, Portugal
Author to whom correspondence should be addressed.
Electronics 2019, 8(10), 1097;
Received: 29 August 2019 / Revised: 25 September 2019 / Accepted: 25 September 2019 / Published: 28 September 2019
(This article belongs to the Special Issue Emerging Trends in Industrial Communication)
Ethernet is a popular networking technology in factory automation and industrial embedded systems, frequently using a ring topology for improved fault-tolerance. As many applications demand ever shorter cycle times and a higher number of nodes, the popular ring endure to remain as a valid topology. In this work, we discuss the factors that determine the ring network delay and show how they affect the network cycle time. Since increasing the link capacity has limited reach, we explore a time-triggered protocol that brings the nodes forwarding delay near to the physical layer delay. Additionally, we propose hardware accelerators based on FPGA technology that minimise the packet reception delay from physical reception to delivery to an application handler, preserving Ethernet layers and being compatible with its standard. This paper explains the accelerators concept and implementation, presents measurements using standard Media Access Control implementations, and shows the solution effectiveness with experimental results. We achieved a delay, from physical reception to the triggering of a user-level handler, of 1.1 µs independent of the packet length. View Full-Text
Keywords: end-to-end delay; ethernet; hardware accelerator end-to-end delay; ethernet; hardware accelerator
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P. Corrêa, T.; Almeida, L. Hardware Support to Minimize the End-to-End Delay in Ethernet-Based Ring Networks. Electronics 2019, 8, 1097.

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