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Open AccessArticle

Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs

1
HCTLab Research Group, Universidad Autonoma de Madrid, 28049 Madrid, Spain
2
Facultad de Ciencias Exactas, Universidad Nacional del Centro de la Provincia de Buenos Aires, Tandil B7001BBO, Argentina
3
Faculty of Engineering, FASTA University, Mar del Plata B7600, Argentina
*
Author to whom correspondence should be addressed.
Electronics 2018, 7(10), 219; https://doi.org/10.3390/electronics7100219
Received: 7 September 2018 / Revised: 24 September 2018 / Accepted: 26 September 2018 / Published: 27 September 2018
(This article belongs to the Special Issue Applications of Power Electronics)
As the performance of digital devices is improving, Hardware-In-the-Loop (HIL) techniques are being increasingly used. HIL systems are frequently implemented using FPGAs (Field Programmable Gate Array) as they allow faster calculations and therefore smaller simulation steps. As the simulation step is reduced, the incremental values for the state variables are reduced proportionally, increasing the difference between the current value of the state variable and its increments. This difference can lead to numerical resolution issues when both magnitudes cannot be stored simultaneously in the state variable. FPGA-based HIL systems generally use 32-bit floating-point due to hardware and timing restrictions but they may suffer from these resolution problems. This paper explores the limits of 32-bit floating-point arithmetics in the context of hardware-in-the-loop systems, and how a larger format can be used to avoid resolution problems. The consequences in terms of hardware resources and running frequency are also explored. Although the conclusions reached in this work can be applied to any digital device, they can be directly used in the field of FPGAs, where the designer can easily use custom floating-point arithmetics. View Full-Text
Keywords: hardware-in-the-loop; floating-point; fixed-point; real-time emulation; field programmable gate array hardware-in-the-loop; floating-point; fixed-point; real-time emulation; field programmable gate array
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Sanchez, A.; Todorovich, E.; De Castro, A. Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs. Electronics 2018, 7, 219.

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