A Temperature-Independent Gate-Oxide Degradation Monitoring Method for Silicon Carbide Metal Oxide–Semiconductor Field-Effect Transistors Based on Turn-Off Ringing

Abstract

Gate-oxide degradation in silicon carbide (SiC) metal oxide–semiconductor field-effect transistors (MOSFETs) is a significant concern. Consequently, several methods have been developed to monitor the aging degree. In this article, a temperature-independent method for gate-oxide degradation monitoring is proposed by measuring the minimum turn-off circuit parasitic inductor voltage v_{cir_min} at a specific gate resistor and voltage. The temperature sensitivity of v_{cir_min} is analyzed based on a derived model. Adjustment of the turn-off gate voltage and resistance is proposed to mitigate the impact of temperature on v_{cir_min}. The devices under test are aged by high-temperature gate bias (HTGB) experiments and are tested in double-pulse tests (DPT). A 32 V bias for 42 h and 25–150 °C temperature results in changes of 6.55% and 0.103% in v_{cir_min}, respectively. The experimental results show that the proposed method is effective in maintaining temperature independence. Additionally, the effects of bus voltage, load current, and bond wire failure on v_{cir_min} are also tested and analyzed. The proposed method provides a valuable tool for accurately monitoring SiC MOSFET gate-oxide degradation in scenarios characterized by significant temperature fluctuations.

1. Introduction

SiC MOSFETs exhibit higher withstand temperatures, faster switching speeds, and lower on-resistance compared to conventional Si-based devices [1]. Consequently, their market share is rapidly increasing in sectors such as new energy generation, electric vehicles, and power supplies. However, due to the high interface state density and time-dependent dielectric breakdown (TDDB) of SiC MOSFETs, the gate-oxide reliability of SiC MOSFETs is one of the main obstacles to their large-scale marketization [2]. In particular, the threshold voltage (V_TH) drift, i.e., bias temperature instability (BTI), has been widely discussed [3]. Therefore, it is essential to monitor the gate-oxide degradation of SiC MOSFETs to ensure reliable performance in critical applications.

The variations in electrical parameters are the primary indicators of gate-oxide degradation. Several methods have been proposed to monitor gate-oxide degradation through either direct or indirect measurements of electrical parameters. The drift of V_TH is widely recognized as a direct reflection of BTI. However, measuring V_TH is both costly and challenging despite the fact that V_TH experiences significant drift as the gate-oxide degrades [4,5]. Furthermore, the high temperature sensitivity of V_TH complicates accurate monitoring during temperature fluctuations [6,7]. On-resistance (R_ON) and body diode voltage drop (V_SD) vary with the drift of V_TH as the gate oxide degrades [8,9]. A method for monitoring SiC MOSFET gate-oxide degradation based on R_ON in the saturated region is described in [9]. However, this method is only suitable for in situ monitoring, as it cannot eliminate disturbances caused by temperature variations. An alternative approach, which involves simultaneously measuring V_TH and R_ON and constructing feature-target functions to mathematically decouple temperature and aging, was proposed in [6]. Nevertheless, the challenges associated with V_TH measurement remain unresolved with this method. The degree of gate-oxide degradation is also reflected by the V_SD at 0 V gate voltage [10]. Similar to R_ON, V_SD, as a monitoring precursor, is still susceptible to temperature effects. Furthermore, measuring V_SD at 0 V gate voltage is relatively complex. The Miller voltage plateau (V_GP) and Miller plateau time (t_GP) exhibit a linear relationship with the logarithmic stress time during the gate-oxide degradation [11,12]. However, the rapid on/off switching of SiC MOSFETs and oscillations in the Miller plateau complicate the measurement of V_GP and t_GP. Additionally, due to the strong correlation between V_GP and V_TH, the influence of temperature cannot be disregarded.

The TDDB of the SiC MOSFET gate oxide layer under high temperature and high electric field stress leads to an increase in gate leakage current (I_gss) [13]. An early warning method for detecting SiC MOSFET gate-oxide degradation based on I_gss is presented in [14]. The I_gss exhibits very low temperature sensitivity at low gate voltages. However, it is not until the later stages of the gate’s lifespan that I_gss shows a significant increase, rendering it suitable only for fault warning purposes. Additionally, the mA level changes in I_gss also lead to measurement challenges. The junction capacitance at low drain-source voltage (v_DS) and low gate voltage (v_GS), which is another temperature-independent precursor for monitoring the gate-oxide degradation, is presented in [15]. However, challenging measurements at low v_DS and v_GS can still be addressed for junction capacitance used in degradation monitoring. An innovative method that converts the gate input capacitance (C_iss) magnitude to gate charge time is proposed in [16]. However, it is still challenging to measure time variations on the order of ns due to the changes in the order of pF in C_iss caused by gate-oxide degradation.

The gate-oxide degradation monitoring methods for SiC MOSFETs mentioned above either fail to decouple from temperature influences or present significant measurement challenges. Additionally, the intrusiveness to the system is also increased due to the necessity of interfacing with the monitoring object pins for measuring. Therefore, there is a pressing need to identify a method that is unaffected by temperature and allows for straightforward online measurements. Furthermore, it is essential to minimize the intrusiveness to the system. The current change rate (di/dt) is widely recognized as a temperature-sensitive electrical parameter in IGBT and MOSFET junction temperature (T_j) measurements due to its established measurement techniques and good linearity [17,18,19,20,21,22]. The change rate of drain-source current (di_DS/dt) during turn-on is proposed as a nearly temperature-independent precursor for monitoring the gate-oxide degradation of SiC MOSFETs [23]. However, many studies have demonstrated that turn-on di_DS/dt is closely related to T_j due to its correlation with the V_TH [20,24]. The positive temperature sensitivity of Coulomb-scattered carrier mobility (μ_C), which dominates the carrier effective mobility (μ) at low v_GS, has been discussed in [25,26]. For turn-off di_DS/dt, there exists an antagonism between the positive temperature sensitivity of μ_C and the negative temperature sensitivity of V_TH. Thus, turn-off di_DS/dt has the potential to serve as a monitoring precursor that eliminates the effects of temperature.

This article investigates the effects of gate-oxide degradation and temperature on the minimum turn-off di_DS/dt. The relationship between gate resistance (R_G), turn-off gate voltage (V_EE), and temperature sensitivity is analyzed. At appropriate values of R_G and V_EE, low temperature sensitivity is observed, along with a significantly greater degradation sensitivity compared to temperature sensitivity. In addition, the minimum turn-off di_DS/dt can be periodically measured through minimum circuit parasitic inductance voltage (v_{cir_min}), thereby minimizing the impact of monitoring on the system. The measurement difficulties can be reduced by using a peak detection circuit [18,22]. The effectiveness of the method for temperature-independent gate-oxide degradation monitoring of SiC MOSFETs is validated using the double-pulse test. The rest of the article is organized as follows. Section 2 explains the mechanisms by which the gate-oxide degradation and temperature affect v_{cir_min} and analyzes the roles of varying V_EE and R_G in mitigating temperature disturbances. In Section 3, the criteria for selecting V_EE and R_G are presented. The validity of the proposed method is verified using the double-pulse test. Additionally, the impact of various factors on the proposed method is discussed. Section 4 provides a universal analysis, along with a comparison to other precursors. Finally, the content of the article is concluded in Section 5.

2. Theoretical Basis of the Proposed Gate-Oxide Degradation Monitoring Method

2.1. The v_{cir_min} of SiC MOSFET at Turn-Off

In this section, the turn-off process of SiC MOSFET, which can be divided into four stages, is analyzed, and the v_{cir_min} is derived using fundamental device equations. The schematic circuit and turn-off process of SiC MOSFET are shown in Figure 1. L_S and L_cir are the source parasitic inductance and part circuit parasitic inductance, respectively. C_DC, C_GS, and C_GD are the bus capacitance, gate-source parasitic capacitance, and gate-drain parasitic capacitance, respectively.

When a turn-off signal is transmitted from the control system to the driver at t₀, the drive voltage switches from positive voltage (V_GH) to negative voltage (−V_EE). The charges stored in the gate input capacitance C_iss are released through the gate drive resistor R_G. The gate-source voltage (v_GS) can be expressed as

$$v_{\mathrm{GS}}(t)=V_{\mathrm{G}}\exp (-{\displaystyle \frac{t}{R_{\mathrm{G}}{C}_{\mathrm{iss}}}})-V_{\mathrm{EE}}-L_{\mathrm{S}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{DS}}(t)}{\mathrm{d}t}}$$

(1)

where

$$C_{\mathrm{iss}}\approx C_{\mathrm{GS}}+C_{\mathrm{GD}} V_{\mathrm{G}}=V_{\mathrm{GH}}+V_{\mathrm{EE}}$$

(2)

At t₁, the v_GS reaches the Miller plateau voltage (V_GP), which can be expressed as [11]

$$V_{\mathrm{GP}}=V_{\mathrm{TH}}+\sqrt{{\displaystyle \frac{2I_{\mathrm{L}}{L}_{\mathrm{CH}}}{\mu C_{\mathrm{OX}}{W}_{\mathrm{CH}}}}}$$

(3)

where L_CH is the channel length, W_CH is the channel width, μ is the carrier mobility of the channel, and C_OX is the gate oxide capacitance per unit area.

At t₃, the drain source (v_DS) reaches the bus voltage (V_DC). Then, the v_GS continues to drop, according to (1). At the same time, the channel begins to shut down, accompanied by a decrease in drain-source current (i_DS), in accordance with [24]

$$i_{\mathrm{DS}}(t)={\displaystyle \frac{B\mu }{2}}{(v_{\mathrm{GS}}(t)-V_{\mathrm{TH}})}^2$$

(4)

where B is expressed as

$$B={\displaystyle \frac{W_{\mathrm{CH}}{C}_{\mathrm{OX}}}{L_{\mathrm{CH}}}}$$

(5)

The drain-source current change rate (di_DS/dt) in this phase can be obtained by differentiating i_DS with respect to t.

$${\displaystyle \frac{\mathrm{d}{i}_{\mathrm{DS}}}{\mathrm{d}t}}=B\mu (v_{\mathrm{GS}}(t)-V_{\mathrm{TH}})\left[{\displaystyle \frac{-V_{\mathrm{G}}}{R_{\mathrm{G}}{C}_{\mathrm{iss}}}}\exp (-{\displaystyle \frac{t}{R_{\mathrm{G}}{C}_{\mathrm{iss}}}})\right.\left.-L_{\mathrm{S}}{\displaystyle \frac{{\mathrm{d}}^2{i}_{\mathrm{DS}}(t)}{{\mathrm{d}}^{2}t}}\right]$$

(6)

When di_DS/dt reaches the minimum value, d²i_DS/d²t = 0. Based on (1) and (6), the time derivative of di_DS/dt is given by

$${\displaystyle \frac{{\mathrm{d}}^2{i}_{\mathrm{DS}}(t)}{{\mathrm{d}}^{2}t}}=B\mu {\displaystyle \frac{-V_{\mathrm{G}}}{{(R_{\mathrm{G}}{C}_{\mathrm{iss}})}^2}}\exp (-{\displaystyle \frac{t}{R_{\mathrm{G}}{C}_{\mathrm{iss}}}})\times \left[-2V_{\mathrm{G}}\exp (-{\displaystyle \frac{t}{R_{\mathrm{G}}{C}_{\mathrm{iss}}}})+V_{\mathrm{EE}}+V_{\mathrm{TH}}+L_{\mathrm{S}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{DS}}(t)}{\mathrm{d}t}}\right]$$

(7)

At t₃, v_GS reaches V_TH, which causes the inversion layer to disappear and the i_DS to decrease to 0. At this time,

$$V_{\mathrm{G}}\exp (-{\displaystyle \frac{t_3}{R_{\mathrm{G}}{C}_{\mathrm{iss}}}})=V_{\mathrm{EE}}+V_{\mathrm{TH}}+L_{\mathrm{S}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{DS}}(t_3)}{\mathrm{d}t}}$$

(8)

Based on (6) and (8), the d²i_DS/d²t at t₃ can be rewritten as

$${\displaystyle \frac{{\mathrm{d}}^2{i}_{\mathrm{DS}}(t_3)}{{\mathrm{d}}^2{t}_3}}={\displaystyle \frac{B\mu V_{\mathrm{G}}}{{(R_{\mathrm{G}}{C}_{\mathrm{iss}})}^2}}\exp (-{\displaystyle \frac{t_3}{R_{\mathrm{G}}{C}_{\mathrm{iss}}}})\left(V_{\mathrm{EE}}+V_{\mathrm{TH}}\right)$$

(9)

The d²i_DS/d²t > 0 at t₃ based on (9). According to (7), in the interval t₂-t₃, the d²i_DS/d²t decreases monotonically. Therefore, d²i_DS/d²t > 0 in the interval t₂-t₃ means the di_DS/dt continues to increase. Consequently, the value of the di_DS/dt will reach its minimum (di_DS/dt)_min at t₂. The (di_DS/dt)_min can be expressed based on (1), (3), and (6) as follows:

$${\left({\displaystyle \frac{\mathrm{d}{i}_{\mathrm{DS}}}{\mathrm{d}t}}\right)}_{\min }=-{\displaystyle \frac{2I_{\mathrm{L}}+\sqrt{2{BI}_{\mathrm{L}}\mu }(V_{\mathrm{TH}}+V_{\mathrm{EE}})}{L_{\mathrm{S}}\sqrt{2{BI}_{\mathrm{L}}\mu }+R_{\mathrm{G}}{C}_{\mathrm{iss}}}}$$

(10)

Furthermore, (10) can be obtained by establishing and solving the Kirchhoff voltage equations for the gate loop and power loop [27].

The circuit parasitic inductor voltage v_cir can be expressed as follows:

$$v_{\mathrm{cir}}=L_{\mathrm{cir}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{DS}}}{\mathrm{d}t}}$$

(11)

The minimum circuit parasitic inductance voltage v_{cir_min} corresponding to (di_DS/dt)_min can be expressed as follows:

$$v_{\mathrm{cir}\_\min }=-{\displaystyle \frac{2L_{\mathrm{cir}}{I}_{\mathrm{L}}+L_{\mathrm{cir}}\sqrt{2{BI}_{\mathrm{L}}\mu }(V_{\mathrm{TH}}+V_{\mathrm{EE}})}{L_{\mathrm{S}}\sqrt{2{BI}_{\mathrm{L}}\mu }+R_{\mathrm{G}}{C}_{\mathrm{iss}}}}$$

(12)

Following the t₃, the v_GS continues to decrease until it reaches the −V_EE at t₄.

2.2. Effects of Gate-Oxide Degradation and Temperature on v_{cir_min}

According to (12), the v_{cir_min} is a function of the V_TH. Therefore, the v_{cir_min} will exhibit a trend similar to V_TH as the gate oxide degrades. The V_TH can be expressed as follows:

$$V_{\mathrm{TH}}={\varphi }_{\mathrm{ms}}-{\displaystyle \frac{Q_{\mathrm{trap}}}{C_{\mathrm{OX}}}}+2{\psi }_{\mathrm{B}}+{\displaystyle \frac{\sqrt{4q{\epsilon }_{\mathrm{SiC}}{N}_{\mathrm{A}}{\psi }_{\mathrm{B}}}}{C_{\mathrm{OX}}}}$$

(13)

where q is the electron charge constant, ε_SiC is the dielectric constant of SiC, N_A is the doping concentration in the p-type well, Q_trap is charge captured by traps per unit area, ψ_B is the Fermi potential, and ϕ_ms is the work function difference of the interface.

When the gate of SiC MOSFETs is stressed, carriers are injected into the near-interface traps and oxide traps through quantum tunneling. The accumulation of Q_trap will lead to the BTI [2]. Specifically, the accumulation of captured negative charges would cause a positive shift in the V_TH, which is called positive bias temperature instability (PBTI). Conversely, the accumulation of positive charges results in a negative shift, i.e., NBTI [16]. As negative charges captured accumulate, the v_{cir_min} would decrease with accumulation time, and the accumulation of positive charges leads to an increase in v_{cir_min}. In summary, the v_{cir_min}, which varies with gate-oxide degradation, can be used as an effective monitoring precursor.

The effect of temperature on v_{cir_min} needs to be further investigated to achieve temperature independence. According to (12), it is mainly V_TH and μ in v_{cir_min} that vary with temperature. The influence of temperature can be evaluated by taking the derivatives of (12) with respect to T_j:

$${\displaystyle \frac{\mathrm{d}{v}_{\mathrm{cir}\_\min }}{\mathrm{d}{T}_{\mathrm{j}}}}={\displaystyle \frac{L_{\mathrm{cir}}\sqrt{{BI}_{\mathrm{L}}}}{{(L_{\mathrm{S}}\sqrt{2{BI}_{\mathrm{L}}\mu }+R_{\mathrm{G}}{C}_{\mathrm{iss}})}^2}} \left[{\displaystyle \frac{2I_{\mathrm{L}}{L}_{\mathrm{S}}-R_{\mathrm{G}}{C}_{\mathrm{iss}}(V_{\mathrm{TH}}+V_{\mathrm{EE}})}{\sqrt{2\mu }}}{\displaystyle \frac{\mathrm{d}\mu }{\mathrm{d}{T}_{\mathrm{j}}}}\right.-\left.\left(2L_{\mathrm{S}}\mu \sqrt{{BI}_{\mathrm{L}}}+R_{\mathrm{G}}{C}_{\mathrm{iss}}\sqrt{2\mu }\right){\displaystyle \frac{\mathrm{d}{V}_{\mathrm{TH}}}{\mathrm{d}{T}_{\mathrm{j}}}}\right]$$

(14)

The temperature sensitivity of V_TH depends mainly on ψ_B, which can be expressed as [6]:

$${\psi }_{\mathrm{B}}={\displaystyle \frac{k{T}_{\mathrm{j}}}{q}}\ln {\displaystyle \frac{N_{\mathrm{A}}}{n_{\mathrm{i}}}}={\displaystyle \frac{k{T}_{\mathrm{j}}}{q}}\ln {\displaystyle \frac{N_{\mathrm{A}}}{N_{\mathrm{C}}}}+{\displaystyle \frac{E_{\mathrm{C}}-E_{\mathrm{Fi}}}{q}}$$

(15)

where N_C is the conduction state density, E_C is the conduction energy, E_Fi is the intrinsic Fermi level, and k is the Boltzmann constant. The effect of T_j on the V_TH can be described as [28]:

$${\displaystyle \frac{\mathrm{d}{V}_{\mathrm{TH}}}{\mathrm{d}{T}_{\mathrm{j}}}}={\displaystyle \frac{\mathrm{d}{\psi }_{\mathrm{B}}}{\mathrm{d}{T}_{\mathrm{j}}}}(2+{\displaystyle \frac{1}{C_{\mathrm{OX}}}}\sqrt{{\displaystyle \frac{{\epsilon }_{\mathrm{SiC}}q{N}_{\mathrm{A}}}{{\psi }_{\mathrm{B}}}}})$$

(16)

$${\displaystyle \frac{\mathrm{d}{\psi }_{\mathrm{B}}}{\mathrm{d}{T}_{\mathrm{j}}}}=-{\displaystyle \frac{k}{q}}\ln ({\displaystyle \frac{N_{\mathrm{C}}}{N_{\mathrm{A}}}})$$

(17)

In N-channel SiC MOSFETs, the N_C is significantly larger than the N_A, resulting in a negative temperature coefficient for the V_TH, which has been extensively demonstrated in numerous studies [7].

On the other hand, the inversion layer exhibits a multitude of scattering mechanisms. The Coulomb scattering plays a dominant role in the μ during the switching of SiC MOSFET when the gate voltage is low [23,26]. Therefore, in the turn-off process, the μ can be considered as follows:

$$\mu \approx {\mu }_C$$

(18)

where μ_C is the Coulomb-scattered carrier mobility.

The temperature modeling of μ_C can be expressed as [28]:

$${\mu }_{\mathrm{C}}=N{(T_j)}^{\alpha }{\displaystyle \frac{{(Q_{\mathrm{inv}})}^{\beta }}{Q_{\mathrm{trap}}}}$$

(19)

where Q_inv is the inversion charge, N is the model fitting parameter, α is the temperature coefficient, and β is the empirical coefficient. In the case of 4H-SiC, the values of α and β are typically set to 1.

The effect of T_j on the μ can be described as follows:

$${\displaystyle \frac{\mathrm{d}\mu }{\mathrm{d}{T}_{\mathrm{j}}}}=N{\displaystyle \frac{Q_{\mathrm{inv}}}{Q_{\mathrm{trap}}}}={\displaystyle \frac{\mu }{T_{\mathrm{j}}}}$$

(20)

Based on (16) and (20), Equation (14) can be rewritten as

$$\begin{array}{l}{\displaystyle \frac{\mathrm{d}{v}_{\mathrm{cir}\_\min }}{\mathrm{d}{T}_{\mathrm{j}}}}={\displaystyle \frac{L_{\mathrm{cir}}\sqrt{{BI}_{\mathrm{L}}\mu }}{{(L_{\mathrm{S}}\sqrt{2{BI}_{\mathrm{L}}\mu }+R_{\mathrm{G}}{C}_{\mathrm{iss}})}^2}} \left[\left(\sqrt{2}\lambda C_{\mathrm{iss}}-{\displaystyle \frac{C_{\mathrm{iss}}(V_{\mathrm{TH}}+V_{\mathrm{EE}})}{\sqrt{2}{T}_{\mathrm{j}}}}\right)\times R_{\mathrm{G}}\right.+\left.{\displaystyle \frac{2I_{\mathrm{L}}{L}_{\mathrm{S}}}{\sqrt{2}{T}_{\mathrm{j}}}}+2\lambda L_{\mathrm{S}}\sqrt{{BI}_{\mathrm{L}}\mu }\right]\\ =\delta \left[f(V_{\mathrm{EE}})\times R_{\mathrm{G}}+\gamma \right]\end{array}$$

(21)

where

$$\delta ={\displaystyle \frac{L_{\mathrm{cir}}\sqrt{{BI}_{\mathrm{L}}\mu }}{{(L_{\mathrm{S}}\sqrt{2{BI}_{\mathrm{L}}\mu }+R_{\mathrm{G}}{C}_{\mathrm{iss}})}^2}}$$

(22)

$$f(V_{\mathrm{EE}})=\sqrt{2}\lambda C_{\mathrm{iss}}-{\displaystyle \frac{C_{\mathrm{iss}}(V_{\mathrm{TH}}+V_{\mathrm{EE}})}{\sqrt{2}{T}_{\mathrm{j}}}}$$

(23)

$$\gamma ={\displaystyle \frac{2I_{\mathrm{L}}{L}_{\mathrm{S}}}{\sqrt{2}{T}_{\mathrm{j}}}}+2\lambda L_{\mathrm{S}}\sqrt{{BI}_{\mathrm{L}}\mu }$$

(24)

$$\lambda =\left(2+{\displaystyle \frac{1}{C_{\mathrm{OX}}}}\sqrt{{\displaystyle \frac{{\epsilon }_{\mathrm{SiC}}q{N}_{\mathrm{A}}}{{\psi }_{\mathrm{B}}}}}\right){\displaystyle \frac{k}{q}}\ln \left({\displaystyle \frac{N_{\mathrm{C}}}{N_{\mathrm{A}}}}\right)$$

(25)

According to (21), it can be found that the polarity of dv_{cir_min}/dT_j is related to the R_G and V_EE. R_G and V_EE are not typically designed specifically to monitor gate-oxide degradation. However, due to the long-term nature of gate-oxide degradation, the degradation monitoring does not need to be continuous during SiC MOSFET operation but only requires sampling with long time intervals [16]. Therefore, it is only necessary to switch to the R_{G_M} and V_{EE_M} required for monitoring at sampling, and the advent of intelligent drives could facilitate this approach [29]. To eliminate temperature disturbances, there are

$${\displaystyle \frac{\mathrm{d}{v}_{\mathrm{cir}\_\min }}{\mathrm{d}{T}_{\mathrm{j}}}}=0$$

(26)

According to (22)–(24), there are

$$\begin{array}{ccc}\delta >0& \gamma >0& f(V_{\mathrm{EE}})>0 \mathrm{or}\end{array}<0$$

(27)

In accordance with (21), the sufficiently necessary condition to satisfy (26) is

$$\left\{\begin{array}{c}f(V_{\mathrm{EE}})<0 \\ -f(V_{\mathrm{EE}})\times R_{\mathrm{G}}=\gamma \end{array}\right.$$

(28)

From (23), it can be inferred that the condition f(V_EE) < 0 is

$$V_{\mathrm{EE}\_\mathrm{M}}>2\lambda T_{\mathrm{j}}-V_{\mathrm{TH}}$$

(29)

When the V_{EE_M} is deterministic, there always exists a specific R_G (i.e., R_{G_M}) that satisfies −f(V_{EE_M})·R_{G_M} = γ. Therefore, there will always be V_{EE_M} and R_{G_M} to ensure dv_{cir_min}/dT_j = 0. In conclusion, when the optimal values of V_{EE_M} and R_{G_M} have been selected, the v_{cir_min} can be used as a temperature-independent parameter to monitor the gate-oxide degradation of SiC MOSFET.

3. Experimental Validation and Analysis

To verify the validity of the proposed method, a discrete SiC MOSFET with a non-Kelvin package (C3M0040120D, 1200 V, 40 mΩ) from CREE has been selected as the device under test (DUT). The v_{cir_min} of the DUT is tested using DPT, which is recognized as an effective method for accurately reproducing the transient behavior of the DUT under the specified voltage and current conditions. The v_{cir_min} is measured with a passive probe with a 500 M bandwidth, as shown in Figure 2. The sampling interface for v_cir is positioned between the ends of the path from the source to the negative side of the C_DC. The DPT experimental platform is shown in Figure 2. The experimental parameters for the DPT and the specifications of the DUT are shown in

Table 1. Experimental parameters.

Parameter	Value	Parameter	Value
VDC	600 V	VGH	15 V
Iload	20 A	Lload	700 μH
Rated voltage	1200 V	Rated current	66 A
Max VGH/VEE	19/−8 V	Ref VGH/VEE	15/−4 V

. The L_cir is about 50 nH, which is achieved by finite element simulation. A di_DS/dt of 0.2–0.5 A/ns can produce a measurable induction voltage of 10–25 V, demonstrating the feasibility of measuring (di_DS/dt)_min by circuit parasitic inductance.

3.1. The Selection of V_{EE_M} and R_{G_M}

The fact that there are two parameters to be determined makes this monitoring method complicated. However, according to (29), the V_{EE_M} as large as possible can meet the monitoring requirements due to the variability among different types of SiC MOSFETs. Furthermore, according to (23) and (28), a smaller V_{EE_M} will be accompanied by a larger R_{G_M}, which could result in |v_{cir_min}| being too small, thereby increasing the difficulty of sampling. Conversely, an excessively large V_{EE_M} may cause the SiC MOSFET gate to break down, while an overly large v_{cir_min} can lead to drain-source overvoltage exceeding design specifications. Therefore, adhering to the maximum negative gate voltage recommended in the datasheet is a prudent choice for V_{EE_M}.

The selection of R_{G_M} should be made after the V_{EE_M} has been established. Computing R_{G_M} directly via (28) is challenging because some parameters cannot be accurately determined. Therefore, it is more sensible to ascertain R_{G_M} by testing the dv_{cir_min}/dT_j value with different R_G. The V_{EE_M} of the DUT is set to 8 V, and the temperature range for the experiment is established between 25 °C and 150 °C. The case temperature (T_c) of the DUT is regulated by adjusting the output power of the heating plate through a PID controller. To ensure that T_j is approximately equal to T_c during testing, a heating interval of 5 min is selected. Figure 3 shows the mean of dv_{cir_min}/dT_j in the range of 25 °C to 150 °C as a function of R_G. As shown in Figure 3, the dv_{cir_min}/dT_j changes from positive to negative at R_G = 24 Ω. Therefore, to eliminate the effect of temperature, the R_{G_M} of this DUT is set to 24 Ω.

3.2. Validation of the Proposed Method

To verify that v_{cir_min} varies with the gate-oxide degradation of SiC MOSFET at V_{EE_M} and R_{G_M}, the degradation of DUT’s gate oxide is accelerated. Subsequently, v_{cir_min} is tested at various degrees of degradation. Several accelerated aging methods can be employed for SiC MOSFETs [2,3,4,5]. By applying constant extreme stress to the gate under high-temperature conditions, the HTGBtest can rapidly reproduce the gate-oxide degradation of SiC MOSFETs. To reduce the experimental duration, a gate voltage of 32 V is applied while the drain of the DUT is shorted to the source. The DUT is maintained at a temperature of 150 °C on a thermostat during the HTGB test. The existing literature has demonstrated that the cumulative trap-capture charge of SiC MOSFETs increases logarithmically with time [12]. Consequently, a gradually increasing test interval is selected. After each HTGB interruption, the DUT must be preconditioned to eliminate the influence of transient changes. The precondition is carried out by applying a negative bias (−15 V) of 5 s and a positive bias (15 V) of 5 s to the gate electrode [30]. Subsequently, the V_TH is measured after a delay of 1 h to assess the degree of degradation. The test sequence is shown in Figure 4.

To eliminate serendipity, two DUTs (DUT1 and DUT2) from the same batch are evaluated under identical conditions. The V_TH variations over the HTGB test cumulative time and temperature (25–150 °C) are shown in Figure 5, where the results of the DUT2 are shifted forward 1 h for a better presentation, and the interval represented by the blue dotted line indicates the variation of V_TH within the temperature range of 25 °C to 150 °C at a given HTGB time. The gate-oxide degradation of the DUT is evidenced by the observed drift of V_TH in Figure 5. The quantitative V_TH data show that the cumulative HTGB time of 42 h at 32 V gate bias results in a positive V_TH shift of 48.88% for DUT1 and 54.38% for DUT2.

The v_cir of the DUT2 at different temperatures (25 °C, 70 °C, 110 °C, and 150 °C) are tested in both healthy state and after being stressed for 42 h, and the results are shown in Figure 6. From Figure 6, the v_{cir_min} at different temperatures remains nearly constant in both states, indicating that the dv_{cir_min}/dT_j at V_{EE_M} = 8 V and R_{G_M} = 24 Ω is approximately zero and proving the correctness of the theoretical analysis. The variation of v_cir of DUT1 with HTGB time for V_{EE_M} = 8 V and R_{G_M} = 24 Ω is shown in Figure 7a. A noticeable decrease in v_{cir_min} is observed during the HTGB test, indicating that the reduction in v_{cir_min} can effectively reflect the degree of the gate-oxide degradation of the DUT. The temperature-induced change of v_{cir_min} from a healthy state to the DUT stressed for 42 h is tested and displayed in Figure 7b, where the results of the DUT2 are shifted forward 0.5 h for a better presentation. The 42 h HTGB time resulted in a 6.55% reduction in v_{cir_min} for DUT1 and a 7.09% reduction for DUT2. The change in v_{cir_min} due to temperature is less than 0.103% throughout the HTGB test. The temperature-induced changes in v_{cir_min} during the HTGB test are significantly smaller than those caused by the gate-oxide degradation of DUT. Therefore, it can be concluded that temperature interference is nearly negligible when using v_{cir_min} at specific R_G and V_EE to monitor the gate-oxide degradation of SiC MOSFET.

3.3. Affecting Factors of v_{cir_min}

Bus voltage (V_DC) fluctuations and load current (I_load) variations may occur in the converter. Therefore, it is essential to evaluate the influence of the V_DC and I_load on the v_{cir_min} at V_{EE_M} and R_{G_M}. Figure 8a,b show the v_{cir_min} of a C3M0040120D measured at different V_DC and I_load, respectively. According to Figure 8, an increase of 4.70% of v_{cir_min} is observed when V_DC is reduced from 600 V to 400 V, while an increase of 19.5% of v_{cir_min} is observed when I_load is reduced from 25 A to 15 A. Compared to the 7% reduction in v_{cir_min} caused by the 42 h HTGB time, the changes in v_{cir_min} due to the variations of V_DC and I_load cannot be ignored. Therefore, it is suggested that the proposed degradation monitoring precursor in this paper should be measured at a fixed V_DC and I_load.

Bond wire failure is also one of the most prominent ways in which power devices degrade [31,32]. As shown in Figure 9, SiC MOSFETs in the TO 247-3 package have gate bond wires and source bond wires. The source bond wires are typically the most susceptible to damage, as the current flowing through the source bond wires is significantly higher than that in the gate bond wire. Failure of the source bond wires will lead to changes in bond wires’ parasitic resistance and inductance [22]. In TO 247-3 package SiC MOSFET, the bond wires’ parasitic resistance and inductance are in L_S. According to (10), the value of v_{cir_min} will vary with L_S. Therefore, it is essential to assess the impact of bond wire failure on the v_{cir_min}.

The v_{cir_min} of DUT (C3M0040120D) with different degrees of bond wire failure is tested by wire-cutting experiments. As shown in Figure 9, three root source bond wires are observed in C3M0040120D. The v_{cir_min} under healthy state, one wire (b₁) cut, and two wires (b₁, b₂) cut is tested separately and displayed in Figure 10. The v_{cir_min} in one-wire-cut and two-wire-cut states decreased by 1.75% and 4.75%, respectively, compared to the v_{cir_min} in the healthy state. Therefore, bond wire failure can cause non-negligible interference with the v_{cir_min} used for the gate-oxide degradation monitoring of the TO 247-3 package.

As a result, calibration is required if v_{cir_min} continues to be used to monitor the gate-oxide degradation of the TO 247-3 package after bond wires failure.

Fortunately, SiC MOSFETs with the Kelvin package are becoming increasingly popular due to better dynamic performance. For this type of package, the bond wires’ parasitic inductance is not in L_S, meaning that the bond wires’ failure will not affect the v_{cir_min}. Therefore, v_{cir_min} used to monitor the gate-oxide degradation of SiC MOSFETs in packages with Kelvin source will not be influenced by bond wires failure.

Due to the parasitic parameters, undershoot or overshoot is caused by di_DS/dt in the V_DC and v_DS as the SiC MOSFET turns on or off. Snubbers, which are applied to suppress voltage overshoot, would also have an effect on the proposed precursor v_{cir_min} [33]. However, when the buffer is applied, the conclusion that the DC BUS undershoot can still be used to measure junction temperature is presented in [20]. Therefore, it is believed that the application of snubbers does not invalidate the ability of di_DS/dt to measure junction temperature or monitor gate-oxide degradation. Otherwise, the parasitic parameters do not vary with temperature or gate-oxide degradation. Thus, the proposed monitoring method can be applied to various circuit designs.

4. Discussion

4.1. Universality Analysis

To verify the universality of the proposed method to SiC MOSFETs, the v_{cir_min} is tested in two other types of SiC MOSFET (DUT3: C3M0032120D, 1200 V, 32 mΩ and DUT4: C3M0021120D, 1200 V, 21 mΩ). Both DUTs have a −8 V gate voltage limit in the datasheet, so the V_{EE_M} is still set to 8 V. The test results for DUT3 and DUT4 are presented in Figure 11 and Figure 12, respectively. The quantitative results are summarized in

Table 2. Experimental parameter test results of DUT3 and DUT4.

Parameter	Value	Parameter	Value
VEE_M (V)	8	VEE_M (V)	8
RG_M (Ω)	20	RG_M (Ω)	8.2
ΔVTH/VTH_healthy	63.01%	ΔVTH/VTH_healthy	91.27%
Δvcir_min/vcir_min_healthy	6.64%	Δvcir_min/vcir_min_healthy	13.38%
Δvcir_min/vcir_min_25 °C	0.114%	Δvcir_min/vcir_min_25 °C	0.089%

.

According to Figure 11a and Figure 12a, both DUT3 and DUT4 have R_{G_M,} which makes dv_{cir_min}/dT_j = 0 at V_{EE_M} = 8 V. Different R_{G_M} of DUT3 and DUT4 is observed due to device variability. According to Figure 11c and Figure 12c, the downward trend with HTGB time is shown in the v_{cir_min} of both SiC MOSFETs at V_{EE_M} and R_{G_M}, similar to DUT1 and DUT2. The variation of v_cir of DUT3 and DUT4 with temperature, in healthy and degradation (32 h) states, is shown in Figure 13 and Figure 14, respectively. At different HTGB times, the changes in v_{cir_min} due to temperature (25–150 °C) are much smaller than those due to gate-oxide degradation, as shown in Figure 11d and Figure 12d. At 32 h HTGB time, the Δv_{cir_min} of DUT3 and DUT4 due to temperature is 1.72% and 0.66%, respectively, of Δv_{cir_min} due to degradation. Therefore, it can be concluded that the proposed method for monitoring gate-oxide degradation, which is independent of temperature, can be applied to various types of SiC MOSFETs.

4.2. Comparison with Other Precursors

Some existing degradation monitoring precursors are measured and compared with the proposed method, and the results are shown in

Table 3. Comparison with different methods.

Test Condition	Monitoring Precursors	Degradation Value	Temperature Value	Degradation Sensitivity	ζ	VDC	Iload	Bond Wires Failure	Test Interface
${\displaystyle \frac{150 °\mathrm{C}, 32 \mathrm{V} \mathrm{for} 42 \mathrm{h}}{25–150 °\mathrm{C}}}$	vcir_min	1.302 V	0.019 V	7.09%	68.8	yes	yes	yes for non-Kelvin no for Kelvin	BUS
	VTH (5 mA)	1.501 V	0.251 V	54.38%	5.99	no	no	no	G, S
	RON (20 A, 15 V)	7.4 mΩ	19.5 mΩ	13.8%	0.39	no	yes	yes	D, S
	VSD (20 A, −4 V)	0.198 V	0.450 V	4.22%	0.44	no	yes	yes	D, S
	Igss (15 V)	200 pA	<40 pA	<500 pA	×	no	no	no	G

. To illustrate the extent to which the monitoring precursors are influenced by temperature, we define a change ratio (ζ) of degradation to temperature, which can be calculated by

$$\zeta ={\displaystyle \frac{\Delta x_{\mathrm{degradation}}}{\Delta x_{\mathrm{temperature}}}}$$

(30)

where Δx_degradation and Δx_temperature are the changes in monitoring precursors due to degradation and temperature, respectively. A larger ζ presents a smaller effect of temperature on the monitoring of the gate-oxide degradation. It can be assumed that the effect of temperature can be neglected if ζ is greater than 10.

As can be seen in Table 3, a significant advantage of the proposed method is its ability to exclude temperature interferences, which is readily observable compared to other existing methods. Furthermore, this proposed method does not require the pins of the devices as the test interface, ensuring minimal invasiveness to the system.

Additionally, the peak detector circuit can simplify the measurement of the proposed method significantly. Other di_DS/dt measurement methods, such as PCB Rogowski Coil [23] and differential voltage probe [20], can also be used to meet different system designs. Therefore, the proposed method is particularly appealing for systems that experience significant temperature fluctuations or have a completed power part design. Additionally, the existing use of V_DC and I_load sensors can ensure consistent testing conditions under different degradation states.

5. Conclusions

In this paper, a temperature-independent gate-oxide degradation monitoring method for SiC MOSFETs based on the minimum turn-off circuit parasitic inductor voltage v_{cir_min} at a specific gate drive resistor and negative gate voltage is proposed. The relationship between the temperature sensitivity dv_{cir_min}/dT_j and the R_G, V_EE is analyzed. It is found that v_{cir_min} can serve as an easily measurable precursor for monitoring the gate-oxide degradation of SiC MOSFETs without temperature interference under suitable R_G and V_EE. The rationale for selecting R_G and V_EE for different SiC MOSFETs is presented. The effectiveness of the proposed method for monitoring gate-oxide degradation is validated using the double-pulse test. Experimental results demonstrate that the v_{cir_min} decreases by at least 6.55% under a threshold voltage drift of 48.88%, with a maximum variation of only 0.103% across a temperature range of 25–150 °C.

According to the experimental results, the variations in bus voltage and load current can influence the proposed monitoring method, so it is suggested that consistency of test conditions should be required. In addition, the experimental results indicate that the proposed monitoring precursor is affected by bond wire failure in non-Kelvin packages but remains unaffected in Kelvin packages.

Moreover, the universality of the proposed method for SiC MOSFETs has been verified. Through comparing with existing monitoring methods, the approach presented in this article demonstrates several advantages, including being temperature-independent, non-invasive, and easy to measure.

Only the offline test results of the proposed method are presented in this article due to time constraints. The proposed precursor sampling method needs to be designed, and its online implementation needs further research. In addition, more SiC MOSFETs from different makers need to be tested to refine the universality analysis. These studies will continue in future research.