Total Ionizing Dose Effects in Advanced 28 nm Charge Trapping 3D NAND Flash Memory

Abstract

The impacts of total ionizing dose (TID) were investigated in 28 nm 3D charge trapping (CT) NAND Flash memories. This study focused on the variations in the raw bit error rate (RBER) of irradiated flash across different operational modes and bias states. It was observed that the data pattern stored in Flash influences the bit error count after irradiation. The experimental findings demonstrated a dose-dependent relationship with standby current, read operation current, and threshold voltage shifts. Additionally, TID was found to affect the time required for erasure and programming operations. These results were then bench-marked against similar NAND Flash devices, revealing superior resistance to TID effects.

1. Introduction

With the development of storage technology, a large number of new types of memory have been developed [1]. NAND Flash memories represent one of the most rapidly evolving sectors in the semiconductor market. As a type of non-volatile storage, NAND Flash memory can be electronically erased and reprogrammed. Over the last decade, developments in planar NAND Flash cells have progressed swiftly, approaching their scaling limits [2]. To accommodate the demand for higher capacities, the industry has transitioned from planar to 3D NAND technologies, necessitating advanced technological innovations [3,4]. Three-dimensional NAND emerges as a promising solution for large-scale data storage in future memory systems. Extensive research into 3D NAND has led to the proposal of various memory architectures, including BiCS [5], TCAT [6], DC-SF [7], and SMArT [8]. While the adoption of 3D structures enhances storage density and generally improves reliability—owing to the increased electron storage capacity compared to planar configurations—it also poses new challenges associated with the polysilicon channel and floating body effects [9].

The current mainstream 3D NAND Flash structure is a vertical-channel structure where memory cells are located at the intersection between vertical pillars and horizontal word lines [10]. Three-dimensional NAND Flash can be divided into two categories according to the different storage layer materials: floating gate (FG) and charge trapping (CT). The charge storage layer material of FG flash is polysilicon, which is isolated from adjacent cells through a dielectric layer. CT 3D NAND Flash is an emerging flash memory structure; the storage layer material of charge trapping flash is silicon nitride (SiN), which stores charge through a trap inside the material. In addition, since charge trapping technology supports higher pillars, it allows for denser storage.

With the continuous advancement of technology, a variety of 3D NAND Flash memories have been commercialized, leading to an increase in the number of layers from the initial 32 to the current 128 or even higher [11]. Three-dimensional NAND Flash faces several reliability challenges in ionizing radiation environments. Ionizing radiation affects the threshold voltage of memory cells, leading to bit flip events [11,12,13]. Radiation introduces defective states in the oxide layers of memory cells, reducing their reliability in terms of durability and data retention [14,15,16]. Additionally, TID affects the standby current and the time required for read, write, and erase operations [17,18,19]. Annealing time also plays a crucial role in memory performance [17]. However, the above studies on radiation effects mainly focus on FG flash. There are few studies on CT flash; only Bagatin et al. published a study on the TID effect of X-ray on CT flash [10].

This article assesses the performance of a 128-layer CT 3D NAND Flash memory exposed to Co-60 sources in different operating modes. Memory operating in Single-Level Cell (SLC) mode and Triple-Level Cell (TLC) mode exhibits varying degrees of TID resistance. Moreover, different bias states demonstrate varied resistance to radiation. Performance parameters such as standby current, RBER, operating current, threshold voltage, and multi-bit flipping were evaluated under various operating conditions in both TLC and SLC modes to thoroughly assess the TID resistance of this 128-layer CT 3D NAND Flash memory. This work will explore the worst bias of CT 3D NAND Flash operating in space and provide guidance for space applications of the device.

The remainder of this article is structured as follows: Section 2 introduces the technical specifications of the 3D NAND Flash discussed in this study and the experimental design details. Section 3 presents and analyzes the findings on RBER, standby and read currents, threshold voltage, and the performance timing after radiation. Section 4 concludes the article.

2. Devices and Experimental Details

The schematic diagram of the 3D NAND Flash memory array is depicted in Figure 1a, where the word lines (WLs) are illustrated by green layers, the bit lines by red lines at the top, and the polysilicon channels by purple pillars. The circuit configuration of a NAND Flash memory block is presented in Figure 1b. Each memory comprises multiple flash blocks; within each block are numerous flash pages, each containing multiple flash cells.

Commercial 28 nm 3D CT NAND Flash memory chips were evaluated in this study. These flash memory chips underwent irradiation with Co-60 sources to assess their TID response, with a dose rate of 20 rad (Si)/s. Doses were recorded as absorbed dose in silicon. The devices under test received the following dose increments: 0 krad (Si), 10 krad (Si), 20 krad (Si), 30 krad (Si), and 40 krad (Si). Various factors influencing the test outcomes, such as dose, operating mode, data patterns, bias states, and annealing time, were meticulously considered. All measurements and irradiation procedures were carried out at room temperature. To discern the potential effects of non-total ionizing doses, reference devices were simultaneously evaluated alongside the irradiated specimens.

3. Results and Discussions

This section delineates the impact of radiation on NAND Flash memory performance, focusing on the raw bit error rate (RBER). The raw bit error rate refers to the bit error rate of flash memory without error correction code. In this work, we read data from the irradiated chip byte by btye and compared the collected data with the original data pattern to calculate the raw bit error rate. The following formula is used to compute the RBER:

$$\mathrm{RBER}={\displaystyle \frac{\mathrm{Total}\mathrm{bit}\mathrm{error}\mathrm{counts}\mathrm{in}\mathrm{a}\mathrm{page}}{\mathrm{Total}\mathrm{number}\mathrm{of}\mathrm{bits}\mathrm{in}\mathrm{the}\mathrm{page}}}\times 100\%$$

(1)

A. Raw Bit Error Rate

The RBER was assessed following TID irradiation, examining memory function under various operating modes, bias states, and data patterns.

Figure 2 illustrates the correlation between the RBER and dose under different operating modes and bias states. The analysis reveals that TLC mode exhibits a higher sensitivity to total dose effects. Initially, no bit errors were detected in TLC mode at a dose of 0 krad (Si). However, at a total dose of 10 krad (Si), bit errors began to manifest, with the rate of errors accelerating as the dose increased. In contrast, SLC mode demonstrated minimal bit errors, which remained significantly lower than those in TLC mode, even as the dose escalated. Compared with SLC mode, TLC mode has a greater threshold voltage distribution due to the extra programming state, which lead to the noise margin correctly identifying the cell states being smaller than in SLC mode. When the TID effect causes the programming state’s threshold voltage to shift, the flash operating in TLC mode will have more errors, resulting in an increase in the RBER.

The effect of radiation on memory also varies with bias states. Figure 3 displays the RBER–dose relationship under different bias states in both TLC and SLC modes. A comparison of the magnitudes in Figure 3a,b underscores the greater susceptibility of TLC mode to TID, aligning with the observations in Figure 2. Figure 3 illustrates that, irrespective of the operating mode, memory under the read-only state is most vulnerable to TID effects. Conversely, the erase–program–read cycle state exhibits the strongest resistance to TID effects. Compared with the static state, since the data of memory in the dynamic erase–program–read state are constantly updated, the corresponding RBER always displays initial error counts and has the lowest number of errors. However, the dynamic erase–program–read state will apply the maximum voltage in all of three bias states to the high voltage charge pump, and the combined action of repeated program/erase cycles and TID effect will lead to a lot of defects in the oxide layer. This means that the dynamic erase–program–read state has the lowest TID tolerance and fails when the radiation dose exceeds 30krad. The read-only bias state also repeatedly applies a voltage to the gate, and the charge is more likely to leak out of the charge trap layer compared to the static state. So, the memory in the read-only bias state has the highest RBER.

Further examination was conducted on the TID effects across three different data patterns (patterns = 00, AA, and FF). Figure 4 illustrates the bit error count for four scenarios. The radiation tolerance of Flash memory is influenced by the stored data pattern, with the 00 pattern being the most vulnerable to radiation and the FF pattern exhibiting almost no susceptibility to TID.

Comparative analysis with similar memory technologies revealed that 3D NAND’s performance, as reported in [20], indicates an RBER of approximately 0.1 in Multi-Level Cell (MLC) mode under read-only operation at a radiation dose of 40 krad (Si). In contrast, the RBER in SLC mode at the same radiation dose is 1e-5. Our findings demonstrate that at a radiation dose of 40 krad (Si), the RBER in TLC mode is 1 × 10⁻², and in SLC mode, it is 2 × 10⁻⁶, with both figures presenting an improvement over the results in [20]. Moreover, compared to the findings in [12,21], this memory exhibits superior bit error rate performance.

B. Standby current and read current

Figure 5a reveals an increase in the standby current of 3D NAND Flash memory post-irradiation across different operating modes. The TLC mode, particularly in read-only mode, displays the most pronounced increase in standby current, especially when the radiation dose exceeds 20 krad (Si).

Due to the out-of-tolerance standby current of flash memory after irradiation, we carried out an annealing test to study the effect of annealing time on the standby current of flash memory. In our work, the irradiated chips were placed at room temperature for two weeks and the standby current was measured every two days. The relationship between standby current and annealing time post-40 krad (Si) radiation is depicted in Figure 5b for the memory under TLC mode and read-only state. The figure demonstrates that as the annealing time extends, the standby current gradually diminishes and then stabilizes. When the annealing time exceeds 10 days, the standby current of the flash memory returns to the initial level. The TID effect introduces a large number of traps in the tunneling oxide layer of the memory, which strengthens the trap-assisted tunneling (TAT) mechanism. When the TID-induced trap state in the oxide was removed by the annealing test, the standby current of the memory decreased. Our findings can provide guidance for the optimal annealing time of CT 3D NAND Flash operating in radiation environments. Considering the time, cost, and memory annealing characteristics, we suggest that the optimal annealing time of the device is 7 days.

The cyclic read operation generates a consistent read current, the magnitude of which is recorded. Figure 6 presents the read current in relation to the dose, highlighting an increase in read current proportional to the dose. At a total dose of 40 krad (Si), the read current surges by approximately 1 mA, which means that this memory remains stable and reliable during the TID effect.

This memory exhibits robust TID resistance, especially in terms of standby current. When the chip is exposed to a radiation dose of less than 40 krad (Si), the change in standby current across all operational modes is below 15 uA, with an amplitude change under 25%, significantly lower than the figures reported in [12,17,18] under comparable conditions. At a dose of 40 krad (Si), the read current escalates from 6 mA to 7 mA, a variation that is less pronounced than that documented in [18]. Alterations in standby current are attributed to the formation of parasitic transistors and the shift in threshold voltage triggered by radiation [22].

C. Threshold voltage

We obtained the threshold voltage of memory by moving the reference voltage. In this work, Gamma irradiation was performed on the device with all pins grounded, and under SLC mode, the chips were irradiated up to 100 krad (Si). The relationship between the number of bit errors and the increment in bit errors of the memory and the reference voltage are shown in Figure 7; the latter can reflect the threshold voltage distribution of the memory cell. Figure 7a,b demonstrate a decline in the positive threshold voltage for pattern = 00 as the dose escalates. The threshold voltage distribution of the memory cell is Gaussian and the peak value decreases compared to before irradiation. Conversely, Figure 7c,d reveal that the negative threshold voltage for pattern = FF remains largely unaffected by TID.

Figure 8 showcases the failure thresholds of Flash memory across various operating modes (TLC/SLC) and bias states under TID effects. The bias states include read-only, static state, and dynamic erase–program–read cycles. Functional failure is identified when multiple pages are operated upon, and at least one page’s read-back data are entirely incorrect, rendering the data irrecoverable. The dynamic erase–program–read state exhibits the lowest failure threshold, highlighting its vulnerability to TID effects.

The experimental results reveal that for pattern = 00, the corresponding positive threshold voltage diminishes with increasing TID, aligning with prior research [23,24]. However, for pattern = FF, the results diverge. This study observes minimal impact from radiation, contradicting the existing literature where pattern = FF is also susceptible to TID [22]. The variation in threshold voltage is attributable to the change in charge in the charge trapping layer of the memory cell, with TID leading to charge loss [22,24,25].

D. Type of Bit Flip

Figure 9 shows the number of bit flips of CT 3D NAND Flash operating in TLC mode at different doses. In the case of radiation resulting in the loss of the same amount of charge, SLC mode will only appear with 0 becomes 1 bit flip, while for TLC mode, due to the characteristics of its programming state, both 0 becomes 1 and 1 becomes 0 can occur, i.e., there will be one or more flips when reading. For pattern = AA, as the dose increases, the frequency of flips also rises, predominantly manifesting as 1-bit flips without exceeding a 5-bit threshold, attributed to the exclusive occurrence of 0 becomes 1 flips. Conversely, in the context of pattern = 00, 1-bit flips are more prevalent at doses below 30 krad (Si), but higher doses lead to a predominance of multi-bit flipping. When the number of multi-bit flip bits exceeds 4 bits, this means that two adjacent cells are faulty.

The exclusive observation of 0 becomes 1 flips in this study contrasts with the findings reported in [26]. The incidence of bit errors in TLC mode exceeded that in SLC mode, aligning with the conclusions of [25]. Bit flipping is primarily caused by the loss of electrons from the memory cell’s charge trapping layer, a process exacerbated by radiation. This radiation damage leads to electron depletion and the emergence of uncompensated positive charges in the oxide layer, which facilitate the flipping of bits together.

E. Erase Block and Program Page Timing

Figure 10a,b demonstrate that the time required to erase a block decreases with the increasing dose in both SLC and TLC modes. Figure 10c shows an increase in program page time in TLC mode for doses exceeding 20 krad (Si). Figure 10d indicates that Flash operation in SLC mode remains unaffected by total dose effects below 30 krad (Si). However, when this threshold is exceeded, the program time operating in a static state will be reduced. Figure 10a–c highlight that the memory operating in a cyclic read state is the most vulnerable to radiation exposure.

Previous research [19] examined the TID effect on erase time, finding a decrease in erase time with increasing dose, aligning with our observations. Ref. [27] reported an escalation in program times with dose increases, a result echoed in our experiments where the program times at a 40 krad dose nearly doubled, exceeding the findings of [27]. This discrepancy is attributed to ionizing radiation not only inducing charge loss but also generating defect states at the interface, thereby altering the physical properties of both functional and defective cells. This alteration leads to variations in both erase and program times. Additionally, ionizing radiation impacts the peripheral circuits of 3D NAND memory [19]. In conjunction with other experimental outcomes, the variation in erase and program times can be attributed to the influence of TID on the peripheral circuits.

Overall, when compared to prior studies, this chip exhibits superior performance in terms of the RBER, standby current, and read current, showing minimal impact from TID radiation and presenting clear advantages. However, it does not demonstrate a distinct advantage in terms of positive threshold voltage shifts, block erase times, and page program times. Additionally, the negative threshold voltage remains largely unaffected by TID. Thus, the experimental findings confirm the memory’s robust TID resistance.

4. Conclusions

In our work, the impact of TID effects caused by Gamma rays on the performance of a 28nm 3D CT NAND Flash memory, operating in both TLC and SLC modes, was meticulously analyzed. The experimental data reveal that the RBER, standby current, and read operation current escalate with increasing doses, paralleled by a rise in the number of bit flips. This indicates that the severity of the TID effect intensifies with higher doses, adversely affecting memory performance. The threshold voltage’s decline with dose escalation is a critical factor contributing to the increase in the RBER. Moreover, threshold voltage shifts influence both erase and program times. Additionally, annealing time impacts performance, with some functionalities not reverting to pre-irradiation levels after annealing. Our work identifies the worst operating modes and bias states of a 28 nm 3D CT NAND Flash memory, which can provide guidance for spatial applications of this product. In the absence of capacity requirements, the optimal operating mode of this flash memory is SLC mode.