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3 December 2025

Impact of OFF-State Stress on Dynamic RON of On-Wafer 100 V p-GaN HEMTs, Studied by Emulating Monolithically Integrated Half-Bridge Operation

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1
Department of Engineering “Enzo Ferrari”, University of Modena and Reggio Emilia, 41121 Modena, Italy
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STMicroelectronics, 95121 Catania, Italy
3
Department of Sciences and Methods for Engineering, EN&TECH, University of Modena and Reggio Emilia, 41121 Modena, Italy
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Author to whom correspondence should be addressed.
Electronics2025, 14(23), 4756;https://doi.org/10.3390/electronics14234756
This article belongs to the Section Semiconductor Devices
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Abstract

This paper presents the electrical characterization of the on-resistance (RON) of on-wafer 100 V p-GaN power High-Electron-Mobility Transistors (HEMTs). This study assesses device degradation in the context of a monolithically integrated half-bridge circuit, considering both Low-Side (LS) and High-Side (HS) configurations. Since on-wafer samples have been characterized, a custom experimental setup was developed to emulate stress conditions experienced by the devices in the half-bridge circuit. A periodic signal (T = 10 µs, TON = 2 µs) switching from the OFF to the ON state was applied for a cumulative duration of 1000 s. Different OFF-state stress conditions were applied by varying the gate-source OFF voltage (VGS,OFF) between 0 V and −10 V. The on-resistance exhibited a positive drift over time for devices in either the LS or the HS configuration, with the latter showing a more pronounced degradation. Measurements at higher temperatures (up to 90 °C) were carried out to characterize the dynamics of the physical mechanism behind the degradation effects. We identified hole emission from C-related acceptor traps in the buffer as the main mechanism for the observed degradation, which is present in both the HS and the LS configurations. The additional degradation observed in the HS case was attributed to the back-gating effect, stemming from the non-null body-to-source voltage. Furthermore, we found that a more negative VGS,OFF further increases RON degradation, likely related to the higher electric field near the gate contact, which enhances hole emission from C-related acceptor traps.

1. Introduction

Gallium Nitride (GaN) High-Electron-Mobility Transistor (HEMT) is leading the next generation of power switches due to its high frequency and high power capability [1]. More specifically, GaN-on-Si is a particularly interesting platform thanks to its potential for monolithic integration [2]. Despite already being commercialized, GaN-on-Si power devices are still far from reaching their maximum theoretical performance due to, amongst other things, trapping effects occurring during device operation [3]. So far, device-level characterization has been extensively conducted, allowing for a deep understanding of how the trapping mechanisms work in this type of device [4,5,6,7,8,9,10,11,12,13,14]. However, trap dynamics characterization under realistic circuit operating conditions is far less investigated. For example, in monolithically integrated half-bridge circuits, the High side (HS) and Low Side (LS) devices experience different degradation levels in terms of both on-resistance (RON) and threshold voltage (VTH), due to the non-null source-to-body voltage present in HS devices [15,16]. The goal of this paper is to analyze the effect of OFF-state stress on the device performance from the trapping point of view. We find that the core mechanism causing the dispersion of device performance is the hole emission from C-related acceptor traps inside the buffer layer. This mechanism is common for both HS and LS. The additional degradation experienced by the HS device is explained as being due to a purely electrostatic phenomenon due to the so-called back-gating effect. This conclusion is further confirmed by the fact that the time constants and the activation energies (EAs) extracted from the HS and LS transient are essentially the same. Moreover, we find that the negative OFF-state gate voltage enhances the degradation caused by the high drain voltage, and this effect can be explained with the accumulation of negative charges in the AlGaN barrier, which deplete the 2-DEG (two-dimensional electron gas), thus increasing the magnitude of the observed dispersion [17,18].
The paper is organized as follows. In Section 2, the custom experimental setup and the Device Under Test (DUT) are presented. In Section 3, the experimental results are presented, along with a discussion about the physical interpretation of the findings. Section 4 draws the conclusions.

2. Experimental Setup

Figure 1 shows the cross-section of the DUT, which is a 100 V p-GaN HEMT. LG is lower than 1 µm and LGD is lower than 3 µm, allowing a relatively low voltage range of operation (for comparison, the 650 V p-GaN technology typically involves an LGD longer than 15 µm). As customary for GaN power HEMTs, the buffer is C-doped to obtain a semi-insulating layer with a C concentration between 5 × 1018 and 5 × 1019. The p-GaN region in the gate stack is used to deplete 2-DEG under the gate at VGS = 0 V and thus achieve normally off operation, i.e., VTH > 0 V. The circuit employed for the electrical characterization is shown in Figure 2. The drain voltage is supplied by a pair of isolated DC/DC converters that can generate a 50 V isolated voltage. The bulk of the device is connected either to the ground or to the negative terminal of VD to emulate, respectively, the LS and HS configurations. The only difference between LS and HS is the source-to-body voltage, which is 0 V for the LS, while in HS, a non-null VSB is present. This mimics the additional voltage stress experienced by the High-Side device of an integrated half-bridge structure. To improve the Digital Store Oscilloscope (DSO) resolution, we use the clamping circuit shown in Figure 2b. The clamping circuit allows VDS to be measured in its rise as long as VDS < VZ. When VDS reaches the level set by the Zener diode (~4 V), diodes D1 and D2 start to conduct and prevent VDS from rising further. Effectively, the circuit clamps the maximum level of VDS measured by the DSO [19]. This circuit is required only to improve the resolution of the voltage signal measured by the DSO, while the DUT experiences the full 50 V signal as set by the DC/DC converters.
Figure 1. Schematic view of the cross-section of the DUT. The p-GaN under the gate creates an effective ‘p-i-n’ junction towards the source, which depletes the 2DEG at VGS = 0 V and thus allows a normally off operation (i.e., VT > 0 V). The gate–drain distance is such that the 100 V range operation can be withstood, and the carbon concentration in the buffer layer is between 5 × 1018 and 5 × 1019 to obtain a semi-insulating layer.
Figure 2. The measuring board (a) used for the measurement, VD, is provided by means of DC/DC isolated converters. The switch is connected either to the ground (LS) or to the negative pin of the VD (HS). The clamping circuit (b) is used to block the rise in the VDS for a more precise measure with the DSO. We calculate the real VDS,ON with the voltages VA and VB ( V D S , O N = 2 × V A − V B ). In panel (c), a picture of the measurement setup used in this paper is shown for reference.
The typical DC output (ID-VDS) and transfer (ID,IG-VGS) characteristic are shown in Figure 3. From these curves, we can extract the threshold voltage and the static on-resistance, which are, respectively, VTH ≈ 2 V and RON ≈ 20 Ω. More details on the contact resistance and the device structure can be found in [20].
Figure 3. Typical output (a) and transfer (b) DC characteristics of the DUT. From these measurements, we can extract the static value of the on-resistance (RON ≈ 20 Ω) and the threshold voltage (VTH ≈ 2 V), respectively.
The gate of the DUT is driven with a pulsed signal from a waveform generator that switches the device between VGS,ON (6 V) and VGS,OFF (0; −2; −5; −8; −10 V). The drain voltage applied to the device is VDS = 50 V during the OFF state and ~200 mV during the ON state. VDS,OFF has been chosen as 50 V to ensure a test condition comparable with the real application of GaN HEMTs (e.g., 48 V DC/DC converter). The switching period is T = 10 µs with TON = 2 µs. The RON measure is performed by extracting the current during the ON state. The total time taken by the experiment is 1000 s. Before the beginning of each measurement, the DUT is biased in the ON state with low VDS (~200 mV) and VSB = 0 V for 100 s to guarantee a common stress-free initial condition for both the LS and HS configurations. Figure 4 shows the first period of the stress cycle to illustrate the setup.
Figure 4. The first waveform of the stress period. In LS (b), the VDS switch between high and low according to the value of the VGS and the VSB is always zero, regardless of the device condition. In HS (a), the VDS behaves like in LS, but the VSB goes high during the TON, giving an additional stress component.

3. Experimental Results

Figure 5 shows the normalized dynamic on-resistance (RON/RON,0) for VGS,OFF varying from 0 V to −10 V for both LS and HS. RON,0 is taken as the measurement of the first stress pulse. The baseplate temperature for this experiment was set to 60 °C. We can see that for both HS and LS configurations, increasing the negative VGS,OFF causes an increased magnitude of degradation. More specifically, degradation increases from ~20% at 0 V to ~55% at −10 V (LS) and from ~65% at 0 V to ~120% at −10 V (HS). Interestingly, we find that while the OFF-state gate voltage has a significant effect on the magnitude of degradation, it does not appear to have significant effect on the time constant of the transient. This is discussed further when presenting the data at different temperatures.
Figure 5. The transient for different VGS,OFF in LS (a) and HS (b). A higher OFF-state gate voltage (in absolute value) increases the degradation from the device. While the OFF-state gate voltage has a strong effect on the magnitude of the degradation, it appears to have no significant effect on the time constant of the transient.
Stress measurements have been carried out at different temperatures (60 °C to 90 °C with ΔT = 10 °C) for each of the VGS,OFF (from 0 V to −10 V). Figure 6 shows the transients under the different conditions for the LS device. As can be seen, for VGS,OFF = 0 V, the maximum degradation increases from ~17% at 60 °C to 28% at 90 °C. It is noticeable that the increasing temperature not only has the effect of increasing the amplitude of the dynamic on-resistance but also to accelerates it. Figure 7 shows the results of the characterization on the HS device. Similar considerations as those observed for the LS device can be drawn, with the main difference being the increased degradation of the HS device. The degradation at VGS,OFF = 0 V increases from ~65% (at 60 °C) to ~80% (at 90 °C). The temperature accelerates the transient in a manner similar to what occurs in the LS configuration. Figure 8 shows the Arrhenius plot constructed by using the time constants (τ) extracted from the temperature transients, and the exact values of the τs can be found in Table 1 and Table 2. It can be seen how the extract τs for HS and LS at each VGS,OFF are essentially the same, indicating that the main mechanism responsible for the degradation is the same, specifically hole emission from the CN state in the buffer. In Figure 9, the dynamic has been normalized between 0 and 1 to highlight the independence of the time constant from the conditions (LS or HS) and the OFF-state gate voltage applied. As observed in our previous works [4,21], hole emission increases the negative charge due to ionized acceptor traps in the buffer, thus reducing the 2-DEG concentration. The activation energy extracted (0.53 eV) is slightly lower to the one normally extracted for the C-related acceptor traps inside the buffer layer, i.e., 0.9 eV above the valence band [22,23,24,25,26]. However, it might be possible that field enhancement mechanisms such as the Poole–Frenkel effect, which cause a lowering of the energy barrier for carrier emission at high VDS voltages, explain the lower EAs extracted from the data [22,27,28].
Figure 6. Temperature transient for VGS,OFF varying from 0 to −10 (a–e) for LS configuration. We can observe that regardless of the OFF-state gate voltage applied, the increasing temperature enhances the magnitude of the degradation and accelerates it.
Figure 7. Temperature transient for VGS,OFF varying from 0 to −10 (a–e) for HS configuration. We can observe that regardless of the OFF-state gate voltage applied, the increasing temperature enhances the magnitude of the degradation and accelerates it.
Figure 8. Arrhenius plot extracted from the time constant (τ) of the transient at different temperatures and VGS,OFF. We can see that both LS (a) and HS (b) are comparable in terms of τ and activation energy. This means that the root cause for the degradation in both cases is the same (i.e., CN states inside buffer layer).
Table 1. Time constant for LS measurements.
Table 2. Time constant for HS measurements.
Figure 9. Dynamic on-resistance normalized between 0 and 1 for a baseplate temperature of 60 °C. This graph clearly shows the independence of the dynamic from the condition (LS and HS) and from the OFF-state gate voltage.
The increased magnitude of the degradation in HS can be attributed to the back-gating effect, which is present when the substrate and the source are at a different potential [29]. Under this condition, the 2-DEG is more depleted compared to the condition where VSB = 0 due to the higher relative shift between EC and EF. Moreover, the negative substrate potential promotes the hole emission from CN states, resulting in a larger amplitude of the RON dynamic. Nevertheless, the dynamics governed by the trapping process are the same for both LS and HS devices [16,22,30,31].
Concerning the increase in degradation magnitude observed when a negative VGS,OFF is applied, this could be attributed to the enhancing of the vertical electric field under the gate during the OFF state. The band bending induced by the field enhances the hole emission from the C-related acceptor traps located inside the buffer layer. As a consequence, a higher number of holes are emitted from such traps; this results in a buffer layer that becomes even more negatively charged with respect to the condition with VGS,OFF = 0, resulting in a stronger depletion of the 2DEG and thus a higher amplitude of the dynamic on-resistance. In Figure 10a, a sketch of the energy band illustrates this point.
Figure 10. Sketch of the energy band in OFF-state when the VGS is lower than 0 (a). When the negative VGS is applied, the vertical field applied promotes the hole emission from the C-related acceptor traps inside the buffer, which are attracted by the negative potential applied to the gate contact. In panel (b), the equilibrium condition is shown as a reference.

4. Conclusions

In this paper, we have characterized the dynamic on-resistance of on-wafer 100 V p-GaN HEMTs by means of a custom measurement setup able to replicate Low- and High-Side biasing conditions of devices to be employed in monolithically integrated half-bridge circuits. In particular, this setup allows for considering the non-null source-to-body voltage experienced by the HS device during operation. The root cause for RON degradation in both LS and HS is found to be the hole emission from CN states inside the buffer layer, as confirmed by the extracted activation energies, which are compatible with C-related acceptor traps. The additional degradation experienced by the device in HS (with respect to the LS case) is due to the negative bias applied between the substrate and the source, which causes an electrostatic back-gating effect. Finally, it was found that increasing the magnitude of the negative gate voltage applied during OFF-state stress further increases dynamic RON, in both LS and HS cases. This was attributed to the higher electric field near the gate contact, which enhances hole emission from C-related acceptor traps, thus leading to a larger dynamic RON variation.

Author Contributions

Conceptualization, L.M. and A.C.; Methodology, L.M. and A.C.; Software, L.M.; Validation, L.M.; Formal analysis, L.M.; Investigation, L.M. and N.Z.; Resources, L.M. and A.C.; Data curation, L.M.; Writing—original draft, L.M.; Writing—review & editing, N.Z., M.C., G.C., G.G., F.I., G.V. and A.C.; Visualization, L.M.; Supervision, N.Z. and A.C.; Project administration, A.C.; Funding acquisition, A.C. All authors have read and agreed to the published version of the manuscript.

Funding

This work has been funded by the European Union–NextGenerationEU, within the framework of the National Recovery and Resilience Plan (NRRP), Mission 4 Component 2 Investment 1.4-Call for tender n. 3138/2021 modified by the Directorial Decree n. 3175/2021 of the Italian Ministry of University and Research (MUR), Project Code CN00000023, Concession Decree n. 0001033 adopted by the Italian Ministry of University and Research (MUR) on 17 June 2022, CUP E93C22001070001, Project title “Sustainable Mobility Center (CNMS)”.

Data Availability Statement

Data are contained within the article.

Acknowledgments

The views and opinions expressed are those of the authors only and do not necessarily reflect those of the European Union or the European Commission. Neither the European Union nor the European Commission can be held responsible for them.

Conflicts of Interest

Authors Marcello Cioni, Giacomo Cappellini, Giovanni Giorgino and Ferdinando Iucolano were employed by the company STMicroelectronics. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

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