Research and Analysis of an LLCL-Type Active Power Filter with Control Delay Compensation Mechanism

Abstract

This paper presents a control delay compensation method for an LLCL-type active power filter (APF), aimed at improving performance in digital control systems. The proposed strategy is directly integrated into the inner-loop current controller, requiring no additional compensation modules, predictor structures, or capacitor current feedback, which simplifies the control structure and increases flexibility. The method uses real-time internal state responses of the controller to actively compensate for the phase lag caused by digital control delay, effectively maintaining current control accuracy and overall system dynamic stability. Simulation studies based on a 5.5 kW APF system are conducted to verify the effectiveness of the approach. The results show improved current tracking accuracy, stable dynamic behavior under various load conditions. The simulation-based results indicate the potential of the proposed method for improving control accuracy and stability in digitally controlled APF systems. Moreover, very few studies have addressed control delay compensation specifically for LLCL-based APF systems, making this work a valuable contribution to the field.

1. Introduction

With the increasing use of nonlinear loads—such as computers, inverters, and various electronic devices—power quality issues in modern power systems have become more critical. These loads cause voltage and current waveform distortions, leading to harmonic pollution and excessive reactive power, which reduce system stability and efficiency. Harmonics can result in equipment overheating, mechanical vibrations, and premature aging, while reactive power increases energy losses in transmission lines and transformers, raising operational costs and causing unnecessary energy waste. Such problems not only affect the performance of the power grid but also pose risks to sensitive devices and overall system reliability. Therefore, mitigating power quality problems caused by nonlinear loads has emerged as an important and ongoing research focus in the field of power engineering [1]. To address the aforementioned challenges, researchers have proposed a variety of strategies aimed at improving power quality, among which APFs have attracted considerable attention due to their superior compensation capabilities and real-time dynamic response performance [2,3]. APFs are capable of actively injecting compensating currents to eliminate harmonic components while simultaneously providing reactive power compensation, thereby stabilizing voltage and current waveforms within the power grid. Compared with conventional passive filters, APFs offer enhanced adaptability and precise control, allowing them to promptly adjust in response to varying load conditions and maintain efficient operation under complex and dynamic grid environments. Current research on APF primarily focuses on the design of control strategies and the optimization of system architectures. High-performance and fast control algorithms can significantly improve the response speed and compensation accuracy of the filters, enabling them to react in real time to load fluctuations. Meanwhile, optimizing the hardware architecture of the filters contributes to overall system stability and enhances energy utilization efficiency. Furthermore, by improving the reactive power compensation capability, APF can effectively reduce energy losses within the system, thus achieving higher energy efficiency. With the rapid development and large-scale integration of renewable energy technologies, such as solar and wind power, power systems are increasingly exposed to uncertainties and power quality challenges, including intermittent generation and frequent voltage fluctuations. These conditions further emphasize the necessity for advanced APF solutions capable of maintaining grid stability and ensuring high-quality power delivery under increasingly variable operating conditions. APFs have been extensively studied as effective solutions for improving power quality, due to their ability to actively compensate harmonic currents and reactive power in real time. Among the various APF configurations, the Shunt Active Power Filter (SAPF) [4,5,6] has emerged as one of the most widely adopted implementations. Unlike general APF, SAPF are connected in parallel with the power system, making them particularly suitable for mitigating current harmonics and providing reactive power compensation in dynamic and nonlinear load conditions. This specific configuration enables SAPF to respond instantaneously to load variations and maintain high compensation accuracy, which is especially important in power systems with a high penetration of renewable energy sources. Consequently, integrating SAPF into modern power networks not only enhances system stability and reliability but also facilitates the efficient utilization of renewable energy, contributing to the development of cleaner, smarter, and more sustainable power grids.

In the control of APFs, the increasing complexity of control algorithms, combined with the delays introduced by the sampling-and-hold process and pulse-width modulation (PWM), often drives the overall system closer to instability due to phase lag, and in severe cases may even result in divergence. To address this critical issue, numerous delay compensation strategies have been successively proposed in the literature, aiming to mitigate the adverse impact of control delays on system stability and dynamic performance. These compensation techniques not only help maintain robust operation under high switching frequencies and rapidly changing load conditions but also improve the accuracy of harmonic mitigation and reactive power compensation, thereby ensuring the reliable functioning of APF systems in modern power networks. First, Xin et al. [7] proposed a grid current feedback control strategy that integrates a Second-Order Generalized Integrator (SOGI) in order to enhance the stability of grid-connected systems employing LCL filters. In this method, the SOGI structure is utilized to compensate for digital control delays, thereby improving both the immediacy and robustness of current feedback. However, the control performance of this approach strongly depends on the accurate setting of the grid fundamental frequency; any deviation in frequency, or the absence of integration with a phase-locked loop (PLL), will significantly degrade the compensation effect. Moreover, since the SOGI framework incorporates dual integrators and multipliers, it imposes a relatively high computational burden on DSP hardware resources. Practical implementations must also carefully consider issues such as integrator drift, noise interference, and numerical stability, all of which may affect overall system reliability. Ding et al. [8] addressed the challenges of weak grid conditions by proposing a delay compensation strategy that combines a Proportional Complex-Integral (PCI) controller with a second-order low-pass filter. The primary objective of this method is to extend the compensation frequency range, thereby enhancing the robustness of system control under fluctuating grid parameters. Although the PCI controller exhibits excellent delay compensation capability, its design process requires highly precise tuning of complex parameters and relies heavily on the accuracy of the system’s dynamic model. Furthermore, the implementation of this approach involves complex-valued computations and increased hardware resource consumption, which may limit its applicability and flexibility in embedded systems or platforms with constrained computational resources. Another study [9] proposed a delay compensation approach within the Finite Control Set Model Predictive Control (FCS-MPC) framework by incorporating a time-prediction mechanism to offset one control period of digital delay. This strategy can significantly enhance prediction accuracy and improve control response speed. However, its implementation requires high-order differential models and Lagrange extrapolation algorithms, which considerably increase the overall computational complexity. In addition, the method is highly coupled with the switching vector optimization algorithm, posing challenges both to the computational capacity of the controller and to the stability of the system. Lin et al. [10] proposed a dual-sampling real-time computation method that effectively mitigates the impact of digital control delays on the performance of LCL-filter-based grid-connected inverters, demonstrating strong delay compensation capability. However, several practical challenges may arise in applications. First, the dual-sampling mechanism substantially increases the computational burden on the digital controller and imposes stricter requirements on timing synchronization and interrupt handling, particularly under high switching frequency conditions. Furthermore, this method necessitates two current measurements within a single control period; if the associated measurement filters or hardware design are not adequately optimized, noise interference may be exacerbated, potentially compromising the stability and reliability of the control system.

To overcome these limitations, this study proposes a control delay compensation method embedded directly within the inner-loop current controller. The mechanism is fully integrated into the controller architecture, eliminating the need for separate compensating modules or predictive structures, and without relying on additional feedback signals such as capacitor currents. This integration improves system compactness. By actively counteracting phase and gain errors induced by digital control delays through real-time controller state response, the method effectively maintains current control accuracy and overall dynamic stability. Simulation results validate that the proposed approach not only provides effective compensation but also ensures stable operation and precise control, demonstrating strong potential for practical applications, particularly in the LLCL-type APF system developed in this work. The comparison table of previous works and the proposed method is shown in

Table 1. Comparison table.

Method	Theoretical Foundation	Computational Complexity	Hardware Requirements
SOGI [7]	Utilizes a SOGI to compensate digital delay in the current feedback. Performance is sensitive to frequency deviation or PLL absence.	Requires dual integrators and multipliers, imposing a relatively high DSP burden.	Needs accurate PLL synchronization; sensitive to integrator drift, noise, and numerical stability.
PCI [8]	Proportional PCI controller with a second-order low-pass filter to extend compensation frequency range.	Involves complex-valued computations and precise parameter tuning.	Relies on an accurate dynamic model; increased hardware consumption may limit use in embedded systems.
FCS-MPC [9]	FCS-MPC with time-prediction to offset one control period of delay.	Requires high-order differential models and Lagrange extrapolation, leading to high complexity.	Strongly coupled with switching vector optimization; requires high controller capacity and stability consideration.
Dual-sampling [10]	Real-time dual-sampling strategy to mitigate delay effects in LCL inverters.	Substantially increases computational burden and strict synchronization requirements.	Needs two current measurements per control period; sensitive to measurement noise and filter/hardware design.
Proposed method	Inner-loop delay compensation applied directly; no additional predictors or complex controllers needed.	Low complexity; avoids complex-valued or predictive algorithms.	No extra sensors required; reduces cost and improves fault tolerance.

. The following section systematically presents the proposed control delay compensation method. First, the theoretical foundation and design architecture are introduced, providing a detailed explanation of the control principle and highlighting how the method effectively overcomes common delays in digital control systems while enhancing overall control accuracy. To the best of our knowledge, studies on control delay compensation strategies in LLCL-type APF systems are still lacking, and this work seeks to provide an initial contribution to address this gap. Subsequently, system stability is evaluated through mathematical modeling and frequency-domain analysis, investigating the influence of the compensation strategy on system stability to ensure robust and reliable performance under various operating conditions. Finally, the proposed method is validated through comprehensive simulations conducted in Matlab/Simulink on a 5.5 kW system under multiple scenarios and load-switching conditions, including transient responses and abrupt load changes. These results demonstrate the compensation effectiveness and dynamic performance of the method. In particular, the main contributions are listed as follows:

• The proposed control achieves effective delay compensation without requiring additional sensors or predictive controllers.
• Only the inner-loop compensation is used, resulting in lower cost and higher fault tolerance.
• For LLCL-type APFs, this work provides a novel perspective that fills a research gap in the existing literature.

2. Materials and Methods

2.1. Architecture of LLCL-Type Active Power Filter

As shown in Figure 1, the system architecture mainly consists of two primary components: (1) a rectifier and (2) an APF. The system input voltage V_g serves as the main power source for the entire system. The rectifier is responsible for converting the AC voltage into DC voltage to supply the DC load R_o. However, the nonlinear characteristics of the rectification process introduce significant harmonic distortion, causing the current waveform to deviate considerably from the ideal sinusoidal shape. This not only degrades power quality but also results in a substantial increase in the total harmonic distortion (THD) of the current. To effectively suppress the harmonic pollution generated by the rectifier and to significantly improve the current THD of the overall system, an APF is integrated into the power network. This APF is implemented using an LLCL-type full-bridge topology. The APF is capable of real-time monitoring of the grid current signals, and through the use of high-precision current sensors, it accurately extracts the non-ideal components embedded in the load current i_L with particular emphasis on the low-order harmonic components. The system is capable of identifying the frequency and phase information of the target harmonics. Based on this analysis, the APF actively generates a set of compensating currents i_g that possess the same frequency but an opposite phase to the harmonics to be mitigated. These compensation currents are then injected into the grid in real time, ensuring an effective cancelation of the undesired harmonic components. As a result of this compensation mechanism, the grid-side current i_a can closely approximate an ideal sinusoidal waveform, thereby improving current quality and significantly reducing the THD. Through this approach, the system not only suppresses current distortion induced by rectifiers and other nonlinear loads, but also alleviates equipment interference and thermal losses caused by harmonics, ultimately enhancing grid operational stability and improving overall energy utilization efficiency.

To enhance the suppression capability of the APF against high-order harmonics, this study specifically addresses the harmonics generated during the inverter switching process (Q₁~Q₄), with particular attention to the high-frequency harmonics occurring around the switching frequency of 20 kHz. To achieve this objective, the output stage of the APF inverter adopts an LLCL filter topology. Compared with the conventional LCL filter, the LLCL configuration introduces an additional small series inductor L_c in the capacitor branch of the LCL structure, thereby improving the high-frequency attenuation characteristics and enabling effective suppression of specific higher-order harmonics. The presence of this additional inductor significantly increases the impedance around the switching frequency, reinforcing the attenuation of high-frequency switching harmonics. Consequently, the THD in the output current is effectively reduced, resulting in improved grid current quality. Furthermore, the LLCL filter demonstrates a steeper frequency attenuation slope compared to traditional LC and LCL structures. This property allows the use of smaller inductance L_c and capacitance C values for the passive components while still maintaining excellent high-order harmonic suppression. Such advantages not only reduce the physical size of the filter components but also contribute to a more compact circuit layout and higher overall system efficiency. Under the same filtering requirements, the LLCL topology achieves superior high-frequency harmonic suppression with smaller passive elements, offering improved power density and space utilization. Considering both filtering performance and overall system design requirements, the LLCL filter exhibits superior characteristics compared to LC or LCL filters, and is therefore adopted as the filtering topology in this study.

As shown in Figure 2, the control block diagram of the APF in this study can be divided into three main sections: the LLCL filter transfer function G_LLCL(s), the controller transfer function G_c(s), and the conversion from the inverter switching duty cycle d to the output voltage v_t. First, the LLCL filter transfer function G_LLCL(s) is established based on the equivalent linear circuit, which includes the inverter-side inductor L_i, grid-side inductor L_g, filter capacitor C, and series inductor L_c. This transfer function reflects the current–voltage dynamic characteristics of the filter system in the frequency domain and is expressed as follows:

$$G_{\mathit{LLCL}}\left(s \right)={\displaystyle \frac{i_i}{v_t}}={\displaystyle \frac{s^2{(L}_c+L_g)C+1}{s^3\left[L_i{L}_{g}C+\left(L_i+L_g\right)L_{c}C\right]+s\left(L_i+L_g\right)}}$$

(1)

This transfer function describes the dynamic response from the inverter-side current i_i to the inverter output voltage v_t, serving as a fundamental basis for both controller design and stability analysis. Subsequently, the design of the controller G_c(s) focuses on enhancing the stability and responsiveness of the current-feedback loop, ensuring that the output current can accurately track the reference compensation current. The controller is implemented based on a proportional–integral structure, expressed as follows:

$$G_C\left(s\right)=K_P+{\displaystyle \frac{K_I}{s}}$$

(2)

Next, the inverter modulation mechanism generates the corresponding output voltage v_t through the control of the duty cycle d. Since a bipolar PWM switching scheme is employed in this system, the relationship between d and v_t can be expressed as follows:

$$v_t=(2d-1)V_{\mathit{dc}}$$

(3)

By integrating the three aforementioned blocks, the APF control block diagram illustrates the complete control process: the reference current input i_i,ref and the feedback current i_i are first subtracted, and the resulting error is processed by the controller to generate the reference modulation signal v_t*. This signal is subsequently applied to the inverter, which, together with the LLCL filter, produces the desired compensating current i_g. This comprehensive control framework not only defines the operational flow of the system but also provides a solid foundation for the design and stability analysis of the control delay compensation method proposed in the subsequent sections. In this study, the duty cycle d is derived from Equation (3), where the inverter output voltage v_t is replaced with the reference modulation signal v_t* to implement the closed-loop control strategy. The duty cycle d is expressed as follows:

$$d={\displaystyle \frac{1}{2}}+{\displaystyle \frac{{v_t}^{*}}{{2V}_{\mathit{dc}}}}$$

(4)

To mitigate unexpected voltage harmonic disturbances on the grid side and to enhance overall compensation performance and control stability, a feedforward compensation mechanism based on the capacitor voltage v_c is incorporated into the duty cycle d control strategy. This approach actively counteracts the impact of grid-side disturbances on the output voltage control. Consequently, Equation (4) is revised as follows:

$$d={\displaystyle \frac{1}{2}}+{\displaystyle \frac{v_c}{{2V}_{\mathit{dc}}}}+{\displaystyle \frac{{v_t}^{*}}{{2V}_{\mathit{dc}}}}$$

(5)

In Equation (5), v_t* represents the ideal inverter output voltage command, which can be further expressed as the product of the current control error and the controller transfer function G_c(s)(i_i,ref − i_i), where i_i,ref denotes the desired reference compensation current, and i_i is the actual feedback current measured on the inverter side. This relationship indicates that the controller generates the corresponding inverter voltage command v_t* based on the real-time current error, driving the inverter to produce an accurate compensating current and thereby achieving effective harmonic suppression. Accordingly, Equation (5) can be expanded as follows:

$$d={\displaystyle \frac{1}{2}}+{\displaystyle \frac{v_c}{{2V}_{\mathit{dc}}}}+{\displaystyle \frac{G_c\left(s\right)(i_{i,\mathrm{ref}}- i_i)}{{2V}_{\mathit{dc}}}}$$

(6)

In the following subsection, the duty cycle d expression derived in this subsection serves as the basis for further introducing a control delay compensation mechanism, aiming to enhance system stability and dynamic response performance under a digital control environment. To clearly illustrate the design of the compensation strategy, the control block diagram will be redrawn to incorporate the transfer function representing the control delay, thereby providing a more comprehensive depiction of the delay effects on the system’s dynamic behavior. Subsequently, based on the updated control block diagram, the control delay compensation mechanism will be applied to counteract the adverse impacts of control delay on the system.

2.2. Control Delay Compensation Mechanism

In this subsection, based on the control block diagram presented in the previous chapter, two updated control block diagrams will be illustrated. The first diagram incorporates the digital control delay transfer function, explicitly reflecting the significant impact of control delay on phase and gain margins. The second diagram further includes the control delay compensator, enabling a comparison of the system structure before and after compensation and highlighting the role of the compensator within the overall control loop. Through this comparison, the effectiveness of the control delay compensation mechanism in enhancing control accuracy and system stability can be systematically demonstrated. Figure 3 illustrates the control block diagram incorporating the effects of control delay. In this diagram, the delay transfer function is positioned after the duty cycle d to explicitly reflect the delay introduced by sampling and PWM in digital control systems on the dynamic response. The inherent digital control delay can be approximated as 1.5 control periods, including one sampling-period computation delay and an additional half sampling-period delay introduced by the PWM process. The proposed delay compensator effectively compensates delays up to 1.5 control periods, corresponding to the switching period of the system. Within this range, the compensator successfully mitigates the phase lag introduced by control delays, ensuring that the closed-loop system maintains stability and accurate current tracking under all considered operating conditions. Beyond 1.5 control periods, the compensation gradually becomes less effective, and the phase margin decreases, defining the practical operational limit of the compensator. The control delay function G_d(s) is expressed as follows:

$$G_d\left(s\right)=e^{-1.5s{T}_s}$$

(7)

To further analyze the specific impact of control delay on system stability, the control block diagram shown in Figure 3 is equivalently simplified and transformed into the frequency-domain analysis model depicted in Figure 4. In this model, G_PWM(s) is equivalently represented as follows:

$$G_{\mathit{PWM}}\left(s\right)={\displaystyle \frac{1}{{2V}_{\mathit{dc}}}}·2·V_{\mathit{dc}}= 1$$

(8)

Based on the system transfer function corresponding to Figure 4, the complete open-loop transfer function G_OL(s) can be derived, as expressed in Equation (9):

$$G_{\mathrm{OL}}\left(s\right)=G_c\left(s\right)G_{\mathit{PWM}}\left(s\right)G_d\left(s\right)G_{\mathit{LLCL}}\left(s\right)$$

(9)

To explicitly represent the effects of control delay in the frequency domain, a second-order `Pade approximation is applied to the control delay transfer function, enabling its conversion into a rational function form, as shown in Equation (10):

$$G_d\left(s\right)\approx {\displaystyle \frac{1-\frac{s{T}_s}{2} + \frac{{\left(s{T}_s\right)}^2}{12}}{1 + \frac{s{T}_s}{2} + \frac{{\left(s{T}_s\right)}^2}{12}}}$$

(10)

Subsequently, based on Equation (9), the open-loop transfer function Bode plot is depicted in Figure 5. It can be observed that the system’s phase margin (PM) exhibits negative values (−70.6°), indicating that the current control architecture, without any compensation, operates within an unstable region. This instability could lead to control system divergence or even complete loss of stability. Therefore, it is essential to introduce a control delay compensation mechanism to enhance the overall system stability.

To address the issue of negative PM observed in the Bode plot, Figure 6 illustrates the control block diagram incorporating the proposed delay compensation mechanism. This mechanism introduces a negative feedback path at the controller output, where the feedback signal is scaled by a fixed gain G_comp(s) before being subtracted from the original error signal at the controller input. Such a structure effectively adjusts the system’s phase characteristics and gain response, thereby enhancing the overall stability. Based on this compensation framework, the control block diagram can be further simplified, as shown in Figure 7, from which the modified open-loop transfer function is derived, as expressed in Equation (11).

$$G_{\mathit{OL},\mathit{mod}}\left(s\right)={\displaystyle \frac{G_c\left(s\right)}{1+G_{\mathit{comp}}\left(s\right)G_c\left(s\right)}}{G}_{\mathit{PWM} }\left(s\right) G_d\left(s\right)G_{\mathit{LLCL}}\left(s\right)$$

(11)

Subsequently, based on Equation (11), the open-loop transfer function incorporating the delay compensation mechanism is plotted in the Bode diagram, as shown in Figure 8a. The pole-zero location diagram is shown in Figure 8b. The results clearly indicate that, with the introduction of the proposed compensation strategy, the system PM is significantly improved to a positive range (57.4°). This improvement effectively eliminates the instability risk associated with negative phase margins, thereby ensuring the stable operation of the overall control system. Moreover, Figure 8b exhibits seven poles and six zeros. After appropriate controller design, nearly all poles are stably located in the left-half plane. Although some zeros are positioned in the right-half plane, they do not affect the closed-loop stability. It is worth highlighting the contrast between Figure 5 and Figure 8a. As shown in Figure 5, the system without delay compensation exhibits a negative phase margin, indicating an inherently unstable operating condition. This instability arises from the phase lag introduced by digital control delays, which severely degrades the dynamic performance. In contrast, Figure 8a demonstrates that, after applying the proposed compensation mechanism, the phase margin shifts to a positive region with sufficient stability margin. This clear improvement verifies the effectiveness of the compensation strategy in counteracting delay-induced distortions and ensuring robust current control performance in the APF system.

2.3. Multiple Resonance and Stability Issues in LLCL-Type System

In this subsection, the multiple resonance and stability issues in the LLCL-type system is discussed. The transfer function of the LLCL-type system is derived in Equation (12).

$${\displaystyle \frac{i_g}{V_t}}={\displaystyle \frac{s^2{L}_{c}C+1}{s^3\left[L_i{L}_{g}C+\left(L_i+L_g\right)L_{c}C\right]+s\left(L_i+L_g\right)}}$$

(12)

From Equation (12), two resonance points can be identified, as expressed in Equations (13) and (14), which are shown below

$$f_{\mathit{res}1}={\displaystyle \frac{1}{2\mathsf{\pi }}}\sqrt{{\displaystyle \frac{L_i+L_g}{L_i{L}_{g}C+\left(L_i+L_g\right)L_{c}C}}},$$

(13)

$$f_{\mathit{res}2}={\displaystyle \frac{1}{2\mathsf{\pi }\sqrt{L_{c}C}}}.$$

(14)

Because the parameters L_c and C primarily determine the high-frequency resonant point responsible for harmonic attenuation (20 kHz), as shown in Equation (14), they are not modified to preserve the designed high-frequency filtering performance. Therefore, the parameter variation analysis focuses on L_i and L_g, which dominate the low-frequency resonant point as indicated in Equation (13). The Bode plots in Figure 9 show that under nominal conditions and parameter deviations of −20%, −10%, and +10%, the system maintains stable phase margins. However, when L_i and L_g increase by +20%, the phase margin drops to −58.1°, indicating instability. This occurs because the phase at the second 0 dB gain crossover falls below −180°, resulting in a loss of stability. These results demonstrate that the proposed system remains stable within a reasonable parameter variation range and confirm that the inner-loop control strategy can maintain stability without requiring capacitor current feedback or virtual damping. Nevertheless, the analysis also reveals a certain sensitivity to parameter deviations, suggesting that accurate component design is essential to ensure robust operation.

3. Results and Discussion

In this study, the feasibility and performance of the proposed APF system with a control delay compensation mechanism are verified through system-level simulations using Matlab/Simulink R2024b. A complete system model is constructed on the Simulink platform, integrating the rectifier, APF main circuit, controller, and control delay compensation mechanism, in order to emulate the operation behavior under realistic power conditions. Subsequently, simulation tests70 are carried out to evaluate the system performance in terms of stability, dynamic response characteristics, and harmonic suppression capability under various operating scenarios. Finally, by comparing the voltage and current waveforms as well as the THD variations before and after introducing the compensation mechanism, the effectiveness of the proposed strategy in improving system stability and control performance is systematically discussed. The parameters of the simulated circuit are summarized in

Table 2. Main parameters of the simulated circuit.

Parameter Name	Symbol	Value
Output power	Pout	5.5 kW
Grid voltage	Vg	110 Vrms
Grid current	ia	50 Arms
DC-bus voltage	Vdc	350 V
Switching frequency	fs	20 kHz
Output Voltage	Vo	≈115 V
Output Capacitance	Co	1000 μF
Output Inductance	Lo	2500 μH
Load resistor	Ro	2.4 Ω
Filter Capacitance	C	25 μF
Inverter-side inductance	Li	0.85 mH
Grid-side inductance	Lg	27 μH
Filter inductance	Lc	2.5 μH
P gain	Kp	12
I gain	KI	10
Compensation gain	Gcomp	0.08

.

Subsequently, system-level simulations are conducted to verify the overall performance and stability under different operating conditions. Four simulation scenarios are considered, as shown in

Table 3. Simulation scenarios.

Scenario	Description	Purpose
1	Rectifier only (no APF)	Baseline case to observe harmonic distortion without compensation
2	APF without digital control delay	Evaluate the effectiveness of the designed APF under ideal conditions
3	APF with digital control delay	Assess the negative impacts of delay on stability and dynamic response
4	APF with proposed delay compensation	Validate the effectiveness of the compensation strategy in restoring stability and improving performance

.

3.1. Scenario 1-Rectifier Only (No APF)

Figure 10 illustrates the simulation waveforms of the original power system without the integration of the APF. As shown, the grid voltage V_g maintains a stable and symmetric sinusoidal waveform, with a peak value of approximately ±155 V, corresponding to an RMS value of about 110 V, which complies with the system design specifications. However, since no harmonic compensation mechanism is implemented, the grid current i_a is entirely identical to the load current i_L. Its waveform is significantly affected by the nonlinear rectifier-type load, resulting in pronounced peak distortions and low-order harmonic components. Compared with the ideal pure sinusoidal reference, clear deviations are observed, indicating that the system suffers from considerable current THD problems under the condition without filtering.

Figure 11 presents the frequency-domain analysis of the grid current using the fast Fourier transform (FFT) tool. The results indicate that the fundamental component (60 Hz) reaches a maximum value of 76.71 A, while the THD is as high as 25.84%. This clearly demonstrates that the grid current contains a substantial amount of low-order harmonic components, causing the waveform to deviate severely from the ideal sinusoidal shape. Such a distorted current not only elevates the overall THD of the power grid but may also pose operational instability risks to other electrical equipment. To address this issue, subsequent simulations introduce the APF for real-time compensation control in order to verify its effectiveness in improving grid current quality and suppressing harmonic disturbances.

3.2. Scenario 2-APF Without Digital Control Delay

Figure 12 illustrates the voltage and current waveform responses of the overall power system after the introduction of the APF. In the present system configuration, the load current i_L generated by the nonlinear load contains a significant amount of low-order harmonics, which, if directly supplied by the grid without compensation, would reduce the power factor and adversely affect power quality. To effectively suppress such nonlinear currents, the APF with an LLCL filter structure is introduced, which can generate a compensation current i_g in real time. The compensation current exhibits the same frequency but opposite phase as the harmonic components of i_L, thereby canceling the harmonics and effectively purifying the input current waveform. As a result, the grid current i_a closely approximates an ideal sinusoidal waveform, significantly enhancing both current quality and power factor of the system.

Figure 13 presents the spectral analysis of the grid current i_a after the introduction of the APF. Following compensation, the THD of i_a significantly decreases from 25.84% to 3.41%. This result demonstrates that the designed compensation current i_g effectively suppresses the low-order harmonic components generated by the nonlinear load, markedly improving the spectral characteristics of the input current. Consequently, the proposed APF control strategy exhibits excellent harmonic mitigation capability, providing a substantial enhancement in both power quality and overall system stability.

3.3. Scenario 3-APF with Digital Control Delay

Figure 14 illustrates the time-domain responses of voltages and currents when the system considers the effect of control delay. As shown, the grid voltage v_g remains an ideal sinusoidal waveform, indicating that the input is unaffected by the delay. The load current i_L also maintains stable oscillation amplitude. However, both the grid current i_a and the compensation current i_g exhibit noticeable divergent behavior, with amplitudes rapidly increasing over time, potentially leading to system instability or collapse. This unstable phenomenon is primarily attributed to the introduction of control delay in the digital control system, which effectively adds extra phase lag in the current feedback path. The delay significantly reduces the system’s PM, causing the poles of the open-loop transfer function to move toward the right half-plane and even cross the imaginary axis, resulting in an unstable closed-loop system. These simulation results clearly demonstrate the severe impact of control delay on system stability and underscore the necessity of a delay compensation mechanism. As the resulting grid current THD becomes extremely large in this scenario, it loses physical significance; therefore, the system stability is evaluated primarily through the time-domain responses, providing a more meaningful assessment of performance under extreme conditions.

3.4. Scenario 4-APF with Proposed Delay Compensation

Figure 15 illustrates the current waveforms when the APF system incorporates the proposed control delay compensation strategy. It can be observed that the grid voltage V_g remains stable and undistorted, indicating that the power network side is unaffected by the control adjustments. Compared to the uncompensated case, the compensated grid current i_a clearly restores a sinusoidal waveform that is in phase with the grid voltage, successfully achieving power factor correction and demonstrating the effective harmonic suppression of the compensation mechanism. Moreover, the compensation current i_g exhibits a stable and convergent behavior without any divergence, showing that the compensator possesses robust dynamic regulation capability, capable of promptly counteracting the harmonics and non-ideal components in the load current i_L. Overall, these results verify that the proposed control delay compensation strategy significantly enhances the system’s stability and current quality.

Figure 16 presents the frequency spectrum of the grid current i_a after implementing the control delay compensation mechanism in the APF system. The FFT analysis shows a significant improvement in THD, which decreases to 4.99%, indicating that the delay compensation strategy effectively mitigates instability caused by control delays. The simulation results demonstrate that the compensated current THD is under 5%, verifying the high feasibility and practicality of the proposed compensation mechanism in improving current quality.

Unlike previous studies based on conventional LCL filters, our work employs an LLCL-type filter as the system foundation, which introduces additional resonance points and significantly increases control complexity. The proposed delay compensation method robustly ensures stable operation of this more challenging LLCL system, effectively mitigating control delays while suppressing multi-resonant behaviors. This demonstrates a decisive advantage over traditional approaches: our method achieves stable performance in a system inherently more difficult to control, without requiring additional sensors, predictive controllers, or complex modifications.

4. Conclusions

This study addresses the issue of current harmonic pollution caused by rectifier-type loads by designing an APF system integrated with a control delay compensation mechanism. The system employs an LLCL filter topology, which, owing to its superior high-frequency attenuation characteristics and potential for compact modular design, effectively enhances overall filtering performance. From a control perspective, the inherent computation and PWM delays in digital control systems are explicitly modeled, and a negative-feedback delay compensator is designed to improve system stability and phase margin under dynamic operating conditions. Simulation analyses are conducted under four operational scenarios: a baseline system without APF, an APF system without considering delay, an APF system with delay but without compensation, and the complete system with the delay compensator implemented. Results indicate that, without delay compensation, the system exhibits divergent responses, as illustrated by the rapidly increasing amplitudes in the grid and compensation currents, demonstrating system instability. With the proposed delay compensation mechanism, the waveforms show significant improvement, the control response converges stably, and the final current THD is reduced to 4.99%. In this study, the THD of the grid current is employed as the performance metric for evaluating harmonic suppression. Under the given simulation conditions, the compensated system achieves a grid current THD well below 5%, demonstrating effective mitigation of harmonic distortion. These results validate the effectiveness of the proposed LLCL-type APF architecture and the delay compensation strategy in improving power quality.

Furthermore, we also briefly discuss the practical implementation and potential limitations of the proposed method. The delay compensation strategy is straightforward to implement, requiring no additional sensors or predictive controllers, making it suitable for typical LLCL-type APF systems. Its effectiveness depends on accurate knowledge of system parameters, and performance may be sensitive to variations or uncertainties in these parameters.

In future work, we plan to further extend the proposed LLCL-type APF control strategy to address additional practical scenarios. Specifically, studies will explore its application to systems with variable switching frequencies and multi-phase grid-connected converters, aiming to further enhance robustness and practical applicability. While experimental implementation would provide additional verification, the primary focus of the current and near-term studies remains on comprehensive simulation-based analysis, which has already demonstrated the method’s effectiveness under a wide range of operating conditions. These future investigations will continue to deepen understanding of the proposed delay compensation strategy and its potential for broader practical deployment.